Preparation method of back contact solar cell

Abstract

The invention provides a preparation method of a back contact solar cell, and belongs to the technical field of solar photovoltaic.The preparation method comprises the steps that an organic polymer mask layer is formed in a target area, and then a polycrystalline silicon layer in a non-target area is removed through a fluorine-containing gas etching process; the polycrystalline silicon layer in the area needing to be removed can be conveniently removed by utilizing the difference of selective etching of fluorine-containing gas etching on organic polymer and polycrystalline silicon, the oxide layer or the polycrystalline silicon layer is used as an etching stop layer, extra consumption of a silicon substrate material is reduced, the oxide layer and the polycrystalline silicon layer below a mask cannot be corroded, and the performance of the device is improved. Electric leakage of a finished battery is avoided, and the efficiency and the performance of the solar battery are improved.

Description

Technical Field

[0001] The invention belongs to the technical field of solar photovoltaics, and in particular relates to a method for preparing a back-contact solar cell. Background Art

[0002] The biggest feature of the back-contact cell is that the emitter and metal contact are both on the back of the cell, and there is no metal electrode blocking the front, so it has a higher short-circuit current Isc. At the same time, the back can allow for wider metal grid lines to reduce the series resistance Rs and thus increase the fill factor FF. Moreover, this unobstructed front cell not only has high conversion efficiency, but also looks more beautiful. At the same time, the full back electrode assembly is easier to assemble. However, the preparation method of the back-contact solar cell is relatively complicated and the steps are cumbersome, requiring multiple steps of graphic processing and chemical solution cleaning.

[0003] Chemical solution etching will produce side corrosion due to isotropic corrosion, which reduces the integrity and resolution of the pattern, as well as the performance of the battery. In addition, chemical solution etching will cause environmental pollution, so the used liquid solution needs to be treated and discharged after the process is completed, which increases production costs.

[0004] Different from chemical solution etching, gas etching can significantly reduce side corrosion and improve battery performance due to the directionality of gas energy impact.

[0005] In view of this, the present invention is proposed. Summary of the invention

[0006] In order to solve the above technical problems, the present invention proposes a method for preparing a back-contact solar cell.

[0007] To achieve the above object, the present invention provides the following technical solutions:

[0008] A method for preparing a back-contact solar cell, using method one or method two for preparation;

[0009] The method 1 comprises the following steps:

[0010] Providing a silicon substrate;

[0011] Preparing a tunneling layer on the back side of the silicon substrate;

[0012] preparing an intrinsic amorphous silicon layer on the tunneling layer;

[0013] Performing high-temperature diffusion on the intrinsic amorphous silicon layer to prepare a doped polysilicon layer and a doped silicon oxide layer (BSG layer or PSG layer), wherein the doped silicon oxide layer is located above the doped polysilicon layer;

[0014] forming an organic polymer mask layer in target areas of the doped polysilicon layer and the doped silicon oxide layer;

[0015] Using a first fluorine-containing gas to etch and remove the doped silicon oxide layer in non-target areas;

[0016] Using a second fluorine-containing gas to etch and remove the doped polysilicon layer in non-target areas;

[0017] removing the organic polymer mask layer and cleaning it;

[0018] The second method comprises the following steps:

[0019] Providing a silicon substrate;

[0020] Preparing a tunneling layer on the back side of the silicon substrate;

[0021] preparing a doped amorphous silicon layer on the tunneling layer;

[0022] Performing annealing to convert the doped amorphous silicon layer into a doped polysilicon layer;

[0023] Oxidizing the surface of the doped polysilicon layer to form a doped silicon oxide layer (BSG layer or PSG layer);

[0024] forming an organic polymer mask layer in target areas of the doped polysilicon layer and the doped silicon oxide layer;

[0025] Using a first fluorine-containing gas to etch and remove the doped silicon oxide layer in non-target areas;

[0026] Using a second fluorine-containing gas to etch and remove the doped polysilicon layer in non-target areas;

[0027] The organic polymer mask layer is removed and cleaned.

[0028] In the present invention, the temperature of the high temperature diffusion is preferably 750°C to 1100°C.

[0029] Furthermore, at least two of the composition, concentration and pressure of the first fluorine-containing gas are different from those of the second fluorine-containing gas.

[0030] In the present invention, the first fluorine-containing gas is used to remove the doped silicon oxide layer in the non-target area and the second fluorine-containing gas is used to remove the doped polysilicon layer in the non-target area. The ...

[0031] Further, the etching gas in the first fluorine-containing gas includes HF, or a mixed gas of one of F2, XeF2, CIF, CIF3, IF5, BrF5, BrF3 and water vapor, or a mixed gas of a combination of more than one gas and water vapor, or a combination of one or more of CF4, C2F6, C3F8, C4F8, C4F6, C5F8, CHF3.

[0032] Furthermore, the etching gas in the second fluorine-containing gas includes one or more of Cl2, CF4, HCl, HBr, SF6, C4F6, CHF3, NF3, O2, or one or more of F2, XeF2, CIF, CIF3, IF5, BrF5, BrF3.

[0033] Furthermore, the first fluorine-containing gas and the second fluorine-containing gas contain a diluent gas or a carrier gas, and the diluent gas or the carrier gas includes one or a combination of more than one of He, Ar, and N2.

[0034] Furthermore, the material of the organic polymer mask layer is epoxy or acrylic adhesive; the material of the tunneling layer is one or more of silicon oxynitride, silicon carbide, silicon nitride, aluminum oxide and silicon oxide.

[0035] These fluorine-containing gases have a selectivity of at least 100 for silicon oxide and amorphous silicon, so that even a very small thickness of silicon oxide can achieve a good protection effect on the underlying amorphous silicon layer. The protective effect of silicon oxide during gas etching is much greater than that during chemical solution etching. This is because chemical solution etching of silicon usually uses strong alkaline solutions such as NaOH, KOH or TMAH to corrode silicon, and these strong alkaline solutions are also corrosive to silicon oxide. For example, the corrosion rate of SiO2 in 44% KOH solution at 85°C is 1.4nm / min. In order to ensure the protection of the underlying amorphous silicon / polycrystalline silicon during chemical solution etching, a thicker and denser SiO2 layer is required, which undoubtedly increases the process time and production cost. In fluorine-containing gas etching, even very thin SiO2 will not be corroded, and has better selectivity.

[0036] Furthermore, the material of the organic polymer mask layer is epoxy or acrylic adhesive.

[0037] In the present invention, an organic polymer mask layer is formed in the target area, and then a fluorine-containing gas etching process is used to remove the doped polysilicon layer in the non-target area. By utilizing the difference in the selective etching of the organic polymer and polysilicon by the fluorine-containing gas fluorine etching, the polysilicon layer in the area to be removed can be conveniently removed, while the oxide layer and the polysilicon layer under the mask area are well protected. Based on this, the present invention utilizes the difference in the selective etching of the organic polymer and polysilicon by the fluorine-containing gas etching to remove the corresponding film layer on the area not covered by the protective layer. First, using fluorine-containing gas etching instead of chemical solution etching to remove the corresponding film layer (i.e., the organic polymer mask) avoids the undercutting phenomenon of chemical solution etching. Gas etching has strong directionality and higher etching accuracy. Second, in addition to lateral corrosion, chemical solution etching will also cause vertical corrosion to the oxide layer and polysilicon layer under the mask, which may cause leakage of the finished battery. Fluorine-containing gas etching does not have this problem. Third, the selectivity of chemical solution etching is not as good as that of fluorine-containing gas etching. Gas etching can accurately use the oxide layer or polysilicon layer as the etching stop layer, which will reduce the additional consumption of silicon substrate materials. The above three aspects all help to improve the efficiency and performance of the battery.

[0038] Furthermore, the intrinsic amorphous silicon layer may also be a doped amorphous silicon layer. If it is a doped amorphous silicon layer, it only needs to be annealed to convert the doped amorphous silicon layer into a doped polysilicon layer, and the surface of the polysilicon layer is oxidized to form a silicon oxide layer, which may contain a small amount of dopant, and the dopant type is boron or phosphorus, depending on the doping type of the doped amorphous silicon.

[0039] Furthermore, after removing the doped polysilicon layer in the non-target area, the method for preparing a back-contact solar cell further includes: removing the tunneling layer portion in the non-target area.

[0040] Furthermore, a third fluorine-containing gas is used to etch and remove the tunnel layer portion in the non-target area.

[0041] Furthermore, the pressure of etching using the first fluorine-containing gas, the second fluorine-containing gas and the third fluorine-containing gas is 0.2 torr to 8 torr, and the etching temperature is room temperature.

[0042] Furthermore, the third fluorine-containing gas is the same as the first fluorine-containing gas.

[0043] Furthermore, when gas etching is used to remove the tunneling layer portion of the non-target area, the etching gas is fluorine-containing gas + water vapor. The process of removing the tunneling layer portion of the non-target area is basically the same as the process of removing the doped polysilicon layer of the non-target area. At this time, only a small amount of water vapor needs to be added to the introduced gas, and the doped polysilicon layer and the tunneling layer portion covered by the doped polysilicon layer are removed successively using the same fluorine-containing gas etching equipment, thereby simplifying the process and improving efficiency.

[0044] Compared with chemical solution etching, when gas etching is used, a scrubber will be arranged in the discharge pipeline, and the exhaust gas will undergo a neutralization process before being discharged into the atmosphere. The treatment process is simple and the cost is low.

[0045] The present invention also provides a back-contact solar cell prepared by the above preparation method.

[0046] Compared with the prior art, the present invention has the following advantages and technical effects:

[0047] In the present invention, an organic polymer mask is printed in the target area, and then a fluorine-containing gas etching process is used to remove the doped polysilicon layer in the non-target area. By utilizing the difference in the selective etching of the organic polymer and polysilicon by the fluorine-containing gas etching, the polysilicon layer in the area to be removed can be conveniently removed, while the oxide layer and the polysilicon layer under the mask area are well protected.

[0048] The present invention utilizes the difference in the selective etching of organic polymers and polysilicon by fluorine-containing gas etching to remove the corresponding film layer on the area not covered by the protective layer. Firstly, the use of fluorine-containing gas etching instead of chemical solvent etching to remove the corresponding film layer (i.e., the organic polymer mask) avoids the loss of chemical solution etching in the lateral direction. The fluorine-containing gas etching has strong directionality and higher etching accuracy. Secondly, in addition to the loss in the lateral direction, chemical solution etching will also cause corrosion to the oxide layer and polysilicon layer under the mask in the longitudinal direction, which may cause leakage of the finished battery. The fluorine-containing gas etching used in the present invention does not have this problem. Thirdly, the selectivity of chemical solution etching is not as good as that of gas etching. The fluorine-containing gas etching of the present invention can accurately use the oxide layer or polysilicon layer as the stop layer of etching, which will reduce the additional consumption of silicon substrate materials. The above three aspects are helpful to improve the efficiency and performance of solar cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0050] Figure 1 It is a schematic structural diagram of a back contact solar cell of the present invention;

[0051] Figure 2 is a schematic diagram of the structure of a silicon substrate;

[0052] Figure 3 It is a schematic diagram of the structure after a tunneling layer + an amorphous silicon layer is deposited on the back side of a silicon substrate by the method of the present invention;

[0053] Figure 4 This is a schematic diagram of the structure after a doped polysilicon layer is formed on a silicon substrate using the method of the present invention and a BSG layer is formed on the surface;

[0054] Figure 5 A schematic diagram of the structure after an organic polymer mask is printed on a target area of ​​a surface using the method of the present invention;

[0055] Figure 6 This is a schematic diagram of the structure after the BSG layer in the non-target area is removed by the method of the present invention;

[0056] Figure 7 This is a schematic diagram of the structure after the doped polysilicon layer in the non-target area is removed by the dry etching process of the method of the present invention;

[0057] Figure 8 A schematic diagram of the structure after the mask is removed by the method of the present invention;

[0058] Fig. 9 A schematic diagram of the structure after the tunneling layer in the non-target area is removed by the method of the present invention;

[0059] Fig.10 Schematic diagram of the structure of the solar cell of Comparative Example 1. DETAILED DESCRIPTION

[0060] Various exemplary embodiments of the present invention will now be described in detail. This detailed description should not be considered as limiting the present invention, but should be understood as a more detailed description of certain aspects, features, and embodiments of the present invention.

[0061] It should be understood that the terms described in the present invention are only for describing special embodiments and are not intended to limit the present invention. In addition, for the numerical range in the present invention, it should be understood that each intermediate value between the upper and lower limits of the scope is also specifically disclosed. Each smaller range between the intermediate value in any stated value or stated range and any other stated value or intermediate value in the described range is also included in the present invention. The upper and lower limits of these smaller ranges can be independently included or excluded in the scope.

[0062] Unless otherwise indicated, all technical and scientific terms used herein have the same meanings as those generally understood by those skilled in the art. Although the present invention describes only preferred methods and materials, any methods and materials similar or equivalent to those described herein may also be used in the implementation or testing of the present invention. All documents mentioned in this specification are incorporated by reference to disclose and describe the methods and / or materials associated with the documents. In the event of a conflict with any incorporated document, the content of this specification shall prevail.

[0063] It will be apparent to those skilled in the art that various modifications and variations may be made to the specific embodiments of the present invention description without departing from the scope or spirit of the present invention. Other embodiments derived from the present invention description will be apparent to those skilled in the art. The present invention description and examples are exemplary only.

[0064] The words “include,” “including,” “have,” “contain,” etc. used in this document are open-ended terms, meaning including but not limited to.

[0065] The processes in the present invention that are not described in detail are conventional technical means in the art and are not the focus of the present invention, so they will not be described in detail here.

[0066] The room temperature in the embodiments of the present invention refers to 25±2°C.

[0067] All raw materials used in the examples of the present invention are commercially available.

[0068] An embodiment of the present invention provides a method for preparing a back-contact solar cell, and the method for preparing a solar cell comprises the following steps:

[0069] Providing a silicon substrate;

[0070] Preparing a tunneling layer on the back side of the silicon substrate;

[0071] preparing an intrinsic amorphous silicon layer on the tunneling layer;

[0072] Performing high-temperature diffusion on the intrinsic amorphous silicon layer to prepare a doped polysilicon layer and a boron-doped silicon oxide layer (BSG layer), wherein the boron-doped silicon oxide layer is located above the doped polysilicon layer;

[0073] Printing an organic polymer mask on target areas of the doped polysilicon layer and the boron-doped silicon oxide layer, and drying;

[0074] Removing the boron-doped silicon oxide layer from non-target areas;

[0075] removing the doped polysilicon layer from non-target areas;

[0076] The organic polymer mask is removed and cleaned.

[0077] When the above technical solution is adopted, an organic polymer mask is printed in the target area, and then a gas etching process is used to remove the doped polysilicon layer in the non-target area. By utilizing the difference in the selective etching of the organic polymer and polysilicon by gas fluorine etching, the polysilicon layer in the area to be removed can be conveniently removed, while the oxide layer and polysilicon layer under the mask area are well protected. Based on this, the present invention utilizes the difference in the selective etching of the organic polymer and polysilicon by fluorine-containing gas etching to remove the corresponding film layer on the area not covered by the protective layer. First, using gas etching instead of chemical solution etching to remove the corresponding film layer avoids the loss of chemical solution etching in the lateral direction. Gas etching has strong directionality and higher etching accuracy. Second, in addition to the loss in the lateral direction, chemical solution etching will also cause corrosion to the oxide layer and polysilicon layer under the mask in the vertical direction, which may cause leakage of the finished battery. Gas etching does not have this problem. Third, the selectivity of chemical solution etching is not as good as gas etching. Gas etching can accurately use the oxide layer or polysilicon layer as the etching stop layer, which will reduce the additional consumption of silicon base materials. The above three aspects all help to improve the efficiency and performance of the battery.

[0078] In some embodiments, the intrinsic amorphous silicon layer may also be a doped amorphous silicon layer. If it is a doped amorphous silicon layer, it only needs to be annealed to convert the doped amorphous silicon layer into a doped polysilicon layer, and the surface of the polysilicon layer is oxidized to form a silicon oxide layer, which may contain a small amount of dopant, and the dopant type is boron or phosphorus, depending on the doping type of the doped amorphous silicon.

[0079] In some embodiments, the process of removing the doped polysilicon layer is fluorine-containing gas etching, such as F2, XeF2, CIF, CIF3, IF5, BrF5, BrF3, with an etching pressure of 0.2 to 8 torr and an etching temperature of room temperature.

[0080] These fluorine-containing gases have a selectivity of at least 100 for silicon oxide and amorphous silicon, so that even a very small thickness of silicon oxide can achieve a good protection effect on the underlying amorphous silicon layer. The protective effect of silicon oxide during gas etching is much greater than that during chemical solution etching. This is because chemical solution etching of silicon usually uses strong alkaline solutions such as NaOH, KOH or TMAH to corrode silicon, and these strong alkaline solutions are also corrosive to silicon oxide. For example, the corrosion rate of SiO2 in 44% KOH solution at 85°C is 1.4nm / min. In order to ensure the protection of the underlying amorphous silicon / polycrystalline silicon during chemical solution etching, a thicker and denser SiO2 layer is required, which undoubtedly increases the process time and production cost. In fluorine-containing gas etching, even very thin SiO2 will not be corroded, and has better selectivity.

[0081] In some embodiments, the material of the tunneling layer is one or more of silicon oxynitride, silicon carbide, silicon nitride, aluminum oxide, and silicon oxide.

[0082] In some embodiments, after removing the doped polysilicon layer in the non-target area, the method for preparing the solar cell further includes: removing the portion of the tunneling layer covered by the doped polysilicon layer; wherein the process of removing the portion of the tunneling layer covered by the doped polysilicon layer is basically the same as the process of removing the doped polysilicon layer. At this time, only a small amount of water vapor needs to be added to the introduced gas, and the flow rate of the water vapor is 0.1 to 10 sccm. Using the same etching equipment, the doped polysilicon layer and the portion of the tunneling layer covered by the doped polysilicon layer are removed successively, thereby simplifying the process and improving efficiency.

[0083] In some embodiments, a method is provided as follows Figure 1 The back-contact solar cell shown has a positive electrode and a negative electrode both arranged on the back side. The positive electrode and the negative electrode are respectively in contact with the doped polysilicon below through the opening of the back passivation layer. The doped polysilicon layer is arranged on the tunneling layer on the back surface.

[0084] Some embodiments of the present invention also provide a method for preparing the above-mentioned back-contact solar cell, and the method for preparing the solar cell comprises the following steps:

[0085] Provide a silicon substrate (such as Figure 2 As shown). The silicon substrate can be an n-type semiconductor substrate or a p-type semiconductor substrate. The silicon substrate can be single crystal silicon or polycrystalline silicon. The front and back of the silicon substrate are consistent with the front and back of the solar cell, the front side is the side facing the sunlight, and the back side is the backlight side. The following describes the preparation method of the solar cell by taking the n-type silicon substrate as an example.

[0086] In practical applications, the silicon substrate is first de-damaged and polished. Figure 2 The silicon substrate in the double-sided polishing process. Polishing is carried out using an alkaline solution with additives (alkaline polishing additives), which can make the silicon surface tower base flat after polishing, and the tower bases are well connected, reducing the difficulty of cleaning after alkaline polishing.

[0087] like Figure 3As shown, a tunneling layer and an amorphous silicon layer are formed on the back of the silicon substrate. The tunneling layer is formed on the back of the silicon substrate in its entirety. The tunneling layer can produce a tunneling effect, allowing majority carriers to pass through while hindering minority carriers from passing through. The material of the tunneling layer may include various materials through which majority carriers can tunnel. For example, oxides, nitrides, semiconductors, and conductive polymers. Specifically, the material of the tunneling layer may be one or more of silicon oxynitride, silicon carbide, silicon nitride, aluminum oxide, and silicon oxide. Preferably, the material of the tunneling layer may be silicon oxide, which has good passivation properties, and carriers can easily tunnel through the silicon oxide layer. The thickness of the tunneling layer may be 0.5 nm to 5 nm.

[0088] The process for forming the tunnel layer may be a physical vapor deposition process, or a chemical vapor deposition process such as atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD) or plasma chemical vapor deposition (PECVD). When the tunnel layer is a silicon oxide layer, the process for forming the tunnel layer may also be a thermal oxidation process or a chemical oxidation process.

[0089] In practical applications, the pressure when forming the tunneling layer can be set lower than the atmospheric pressure to reduce the growth rate of the tunneling layer. For example, when a tunneling layer is formed on the back side of a silicon substrate using a thermal oxidation process, the working pressure of the thermal oxidation process can be set lower than the atmospheric pressure. At this time, although the working temperature of the thermal oxidation process is relatively high (600°C or higher), due to the low working pressure, the tunneling layer can maintain a low growth rate, which can significantly reduce the thickness of the tunneling layer. Specifically, the working temperature of the thermal oxidation process can be set to 600°C to 800°C, and the working pressure can be set to 600 Torr or lower to effectively control the thickness of the tunneling layer.

[0090] The above-mentioned deposition process or thermal oxidation process for forming the tunnel layer can be performed in a deposition device. In view of the requirement of the process of forming the tunnel layer for a low-pressure environment, the tunnel layer can be manufactured in a low-pressure chemical vapor deposition device.

[0091] An amorphous silicon layer is formed on the tunneling layer. The amorphous silicon layer may be an intrinsic amorphous silicon layer or a doped amorphous silicon layer. The doped amorphous silicon layer is of a first conductivity type, which may be n-type doped or p-type doped. The thickness of the amorphous silicon layer may be 100 nm to 500 nm.

[0092] The process for forming the amorphous silicon layer may be physical vapor deposition (PVD), low pressure chemical vapor deposition (LPCVD) or plasma chemical vapor deposition (PECVD), etc. When the amorphous silicon layer is a doped amorphous silicon layer, the doped amorphous silicon layer may be prepared by in-situ doping.

[0093] The device for forming the amorphous silicon layer may be an LPCVD device. In this case, the tunneling layer and the amorphous silicon layer may be formed continuously using the same LPCVD device. In this case, the two steps are completed using the same device, which can simplify the process flow, shorten the manufacturing time, and reduce the manufacturing cost.

[0094] When the tunneling layer and the amorphous silicon layer are formed by using an LPCVD device, the temperature difference between the operating temperature for forming the tunneling layer and the operating temperature for forming the amorphous silicon layer can be set within the range of 0°C to 200°C. Preferably, the temperature difference can be within the range of 0°C to 100°C. At this time, the operating temperature difference between the two processes is small, which can reduce the time required to change the operating temperature, thereby further improving the efficiency of continuously forming the tunneling layer and the amorphous silicon layer. In addition, when the temperature difference is small, the two process parameters change less, and it is easier to maintain a relatively difficult-to-control temperature.

[0095] The intrinsic amorphous silicon layer is diffused at high temperature to form a doped polysilicon layer ( Figure 4 ), a BSG layer is formed on the surface. During the high-temperature treatment of boron diffusion, the intrinsic amorphous silicon layer can be converted into a boron-doped polysilicon layer, and its outer layer will diffuse to form borosilicate glass (BSG layer). In some embodiments, the silicon substrate is placed in a boron diffusion furnace, and a boron source (boron trichloride (BCl3) and / or boron tribromide (BBr3)) is used for boron diffusion treatment at a temperature of 900°C to 1050°C for 1h to 3h. The volume proportion of the boron source in the boron diffusion atmosphere in the boron diffusion furnace is 5% to 30%.

[0096] In some embodiments, a doped amorphous silicon layer is deposited, and no diffusion process is required. Only annealing treatment is required to convert the doped amorphous silicon layer into a doped polycrystalline silicon layer. The surface of the polycrystalline silicon layer is oxidized to form a silicon oxide layer. The silicon oxide layer may contain a small amount of dopant, and the dopant type is boron or phosphorus, depending on the doping type of the doped amorphous silicon.

[0097] Printing an organic polymer mask on the target area of ​​the surface ( Figure 5 ), the organic polymer mask is not resistant to alkali corrosion and can be easily removed in an alkaline solution, for example, 1.5% to 5% NaOH or KOH solution can completely remove the organic polymer mask within 30 seconds to 5 minutes. The printed pattern of the organic polymer mask corresponds to the electrode design pattern, and the ratio of the printed width to the electrode design width is between 1:1 and 1:5, which is convenient for subsequent alignment and positioning during click printing. The mask printing height is between 1μm and 10μm. Since the fluorine-containing gas etching has a selectivity ratio of more than 100 for the organic polymer mask and silicon oxide, a very thick mask is not required to achieve a good protection effect, which also saves the material cost of the mask and the subsequent cleaning pressure.

[0098] Remove the BSG layer in non-target areas ( Figure 6 ), the BSG layer in the non-target area is removed by wet etching or fluorine-containing gas etching process. When wet etching is used, the BSG layer is removed by HF solution. The removal method can be chain-type single-sided removal of the BSG layer in the non-target area on the back side, or the silicon wafer can be immersed in the HF solution by tank immersion to simultaneously remove the BSG layer in the non-target area on the back side and the oxide layer formed on the front side during the diffusion process. The concentration of the HF solution is 1% to 5%, and the process time is 1 to 5 minutes.

[0099] The reaction gas for removing the BSG layer by the fluorine-containing gas etching process is VHF or XeF2 containing water vapor. Anhydrous hydrogen fluoride vapor (VHF) is introduced in combination with anhydrous ethanol vapor etching. The gas system is composed of HF, ethanol and N2, of which HF accounts for 30% to 70%. The reaction temperature is 25°C to 60°C, the N2 flow rate is 5 to 15 sccm, and the reaction time is 5 seconds to 5 minutes.

[0100] Water vapor reacts with XeF2 to generate HF to corrode the BSG layer, 2XeF2+2H2O=2Xe↑+O2↑+4HF

[0101] Fluorine-containing gas etching process removes the doped polysilicon layer in non-target areas ( Figure 7 ), the reaction gas of the fluorine-containing gas etching process for removing the doped polysilicon layer is one of F2, XeF2, CIF, CIF3, IF5, BrF5 and BrF3, the etching pressure is 0.2-8 torr, the reaction temperature is room temperature, and the reaction time is 5 seconds to 5 minutes. Among them, the XeF2 flow rate is 10-50 sccm, and the carrier gas N2 flow rate is 20-200 sccm. The reaction can be carried out continuously or in a pulse cycle. The pulse cycle mode is to fill the reaction chamber with gas in a cyclic pulse mode, delaying 0.5-2 minutes. After the etching reaction is carried out for 5-60 seconds, the reaction chamber is evacuated, the etching tail gas is discharged, and the next cycle is carried out until the etching meets the actual needs. The advantage of this is that the fluorine-containing gas can be fully utilized to react with the silicon layer, reducing the gas consumption, thereby reducing the production cost.

[0102] The dry etching process for removing the BSG layer in the non-target area and the dry etching process for removing the doped polysilicon layer can be integrated in different workstations of the same dry etching equipment, sharing the XeF2 and N2 gas pipelines. After the dry etching for removing the BSG layer in the non-target area is completed in the first reaction chamber, it enters the second reaction chamber for dry etching to remove the doped polysilicon layer.

[0103] Remove the mask ( Figure 8), the removal of the organic polymer mask adopts an alkaline etchant, the etching temperature is 25°C to 80°C, and the etching time is 1min to 5min; wherein the alkaline etchant includes one or more of NaOH, KOH and organic alkaline reagents. Under this etching parameter, the organic polymer mask can be removed quickly and efficiently, and the removal described here can include that the organic polymer mask is completely or partially dissolved in the alkaline solution, and the non-dissolved part floats in the solution in the form of strips or flocs, and is collected by the filter through overflow cleaning.

[0104] In some embodiments, the method for preparing a solar cell further includes: cleaning after removing the organic polymer mask.

[0105] Cleaning includes deionized water cleaning and alkali + hydrogen peroxide or ozone cleaning. Deionized water cleaning is used to rinse the residual alkali solution on the surface of the silicon wafer; alkali + hydrogen peroxide / ozone cleaning is to remove the residual organic matter or organic groups on the surface of the silicon wafer, and decompose the organic matter by the oxidation of hydrogen peroxide or ozone. The alkali cleaning temperature here is 25℃~80℃, and the cleaning time is 1min~5min; wherein, the alkali includes one or more of NaOH, KOH and organic alkali reagents, and the alkali concentration is 1%~3% (mass fraction).

[0106] Remove the tunneling layer in non-target areas ( Fig. 9 ), this step is optional, use low concentration HF to remove the tunneling layer, the mass concentration is 0.2% to 2%, or use a mixed solution of HCl + HF, where the concentration of HCl is 1% to 5% (mass fraction) and the concentration of HF is 0.2% to 1% (mass fraction). The mixed solution can further enhance the cleaning effect. The silicon substrate under the tunneling layer serves as a stop layer for HF corrosion.

[0107] After removing the tunneling layer, the next step of LPCVD deposition of the tunneling layer + amorphous silicon layer can be carried out, and then phosphorus diffusion, which is opposite to the boron diffusion to form p-type doping, is carried out to form n-type doping. The process of LPCVD deposition of the tunneling layer and the amorphous silicon layer is basically the same as the above, and will not be repeated here.

[0108] The removal of the mask and the removal of the tunneling layer can be performed in different tanks of the same cleaning equipment.

[0109] The technical solution of the present invention is further illustrated by the following examples.

[0110] Example 1

[0111] An n-type silicon substrate is provided, and damage removal and double-side polishing are performed, and a silicon oxide tunneling layer with a thickness of 1 nm and an intrinsic amorphous silicon layer with a thickness of 200 nm are sequentially deposited on the back side of the silicon substrate by LPCVD;

[0112] The n-type silicon substrate is placed in a boron diffusion furnace, and BCl3 is used as a boron source (the volume of the boron source in the atmosphere accounts for 20%). Boron is diffused on the back of the n-type silicon substrate at 980°C for 2 hours to form p-type B-doped polysilicon (i.e., a boron-doped polysilicon layer). A 50nm thick BSG (borosilicate glass) is diffused on the outer layer of the boron-doped polysilicon layer.

[0113] Printing a corrosion-resistant organic polymer mask slurry on a target area on the back side BSG of an n-type silicon substrate, and drying it to form a patterned blocking mask layer; the corrosion-resistant organic polymer slurry is a waxy resin material, and the corrosion-resistant slurry is characterized by being acid-resistant but not alkali-resistant, such as 0915A of SunChemical Company of the United States; the grid line printing width of the patterned blocking mask layer is 280 μm, and the height after drying is 14.4 μm;

[0114] Chain single-sided HF was used to remove the BSG layer in the non-target area, the HF solution concentration was 3% (mass fraction), and the process time was 1.5 minutes;

[0115] The boron-doped polysilicon layer under the BSG layer in the non-target area is removed by etching with fluorine-containing gas. The etching gas is XeF2, the etching pressure is 3 torr, the etching temperature is room temperature, and the reaction time is 20 seconds. Among them, the XeF2 flow rate is 10 sccm, and the carrier gas N2 flow rate is 50 sccm.

[0116] The patterned blocking mask layer was removed by using a 3.5% (mass fraction) NaOH solution at a reaction temperature of 50° C. for a reaction time of 150 seconds;

[0117] A silicon oxide layer with a thickness of 1 nm and an intrinsic amorphous silicon layer with a thickness of 200 nm are sequentially deposited on the back of an n-type silicon substrate by LPCVD; the n-type silicon substrate is placed in a phosphorus diffusion furnace, POCl3 is used as a phosphorus source (the volume of the phosphorus source in the atmosphere accounts for 20%), and phosphorus is diffused on the back of the n-type silicon substrate at a temperature of 780° C. for 2 hours to form n-type P-doped polysilicon (i.e., phosphorus-doped polysilicon layer), and a 60 nm thick PSG (phosphorus silicon glass) is diffused on the outer layer of the phosphorus-doped polysilicon layer;

[0118] Laser ablation is performed on the PSG layer on the boron-doped polysilicon region on the back of the n-type silicon substrate. The area of ​​the laser ablation region is larger than the boron-doped polysilicon region. Chain acid polishing (HF+HNO3) equipment is used to remove silicon oxide, phosphosilicate glass, polysilicon and borosilicate glass coated on the front of the n-type silicon substrate. Then, the front of the n-type silicon substrate is texturized using NaOH in a tank cleaning machine. The back of the n-type silicon substrate will not be etched by alkali due to the protection of the phosphosilicate glass layer and the borosilicate glass layer. Finally, a mixed solution of HF and HCl is used for cleaning.

[0119] Aluminum oxide layers are prepared on the front and back sides of the n-type silicon substrate by ALD, and the thickness of the aluminum oxide layers is 5 nm;

[0120] A silicon nitride passivation anti-reflection layer is prepared on the front and back sides of the n-type silicon substrate by using a tubular PECVD method; wherein the thickness of the passivation anti-reflection layer on the front side of the n-type silicon substrate is 75 nm, and the thickness of the passivation anti-reflection layer on the back side of the n-type silicon substrate is 100 nm;

[0121] Using laser to open holes in the passivation anti-reflection layer on the back of the n-type silicon substrate, respectively forming a first electrode contact hole connected to the boron-doped polysilicon layer and a second electrode contact hole connected to the phosphorus-doped polysilicon layer;

[0122] forming a first electrode at the first electrode contact hole and a second electrode at the second electrode contact hole by screen printing; the first electrode is connected to the boron-doped polysilicon layer, and the second electrode is connected to the phosphorus-doped polysilicon layer;

[0123] The fill factor of the solar cell prepared in this embodiment is 82.8%, the photoelectric conversion efficiency is 25.8%, the open circuit voltage is 737mV, and the short circuit current is 42.3mA / cm 2 , the reverse current Irev2 is 0.3A.

[0124] Example 2

[0125] The preparation method of the solar cell of this embodiment is basically the same as that of embodiment 1, with the only difference being that this embodiment uses a p-type silicon substrate, and the area of ​​the boron-doped polysilicon region is 30% smaller than that of embodiment 1 to obtain a larger emitter region (n-type P-doped polysilicon).

[0126] The fill factor of the solar cell prepared in this embodiment is 82.7%, the photoelectric conversion efficiency is 25.67%, the open circuit voltage is 734mV, and the short circuit current is 42.1mA / cm 2 , the reverse current Irev2 is 0.6A.

[0127] Example 3

[0128] The same as Example 1, except that a fluorine-containing gas is used to etch and remove the boron-doped polysilicon layer below the BSG layer in the non-target area, the etching gas is BrF3, the etching pressure is 8 torr, the etching temperature is room temperature, and the reaction time is 20 seconds. Among them, the BrF3 flow rate is 10 sccm, and the carrier gas N2 flow rate is 50 sccm.

[0129] The fill factor of the solar cell prepared in this embodiment is 82.3%, the photoelectric conversion efficiency is 25.52%, the open circuit voltage is 733mV, and the short circuit current is 42mA / cm 2, the reverse current Irev2 is 0.5A.

[0130] Example 4

[0131] The same as Example 1, except that the boron-doped polysilicon layer below the BSG layer in the non-target area is etched away using a fluorine-containing gas, the etching gas is CIF, the etching pressure is 0.2 torr, the etching temperature is room temperature, and the reaction time is 20 seconds. Among them, the CIF flow rate is 10 sccm, and the carrier gas N2 flow rate is 50 sccm.

[0132] The fill factor of the solar cell prepared in this embodiment is 82.4%, the photoelectric conversion efficiency is 25.51%, the open circuit voltage is 731mV, and the short circuit current is 42.2mA / cm 2 , the reverse current Irev2 is 0.1A.

[0133] Example 5

[0134] An n-type silicon substrate is provided, and damage removal and double-side polishing are performed, and a silicon carbide tunneling layer with a thickness of 1.5 nm and an intrinsic amorphous silicon layer with a thickness of 300 nm are sequentially deposited on the back side of the silicon substrate by LPCVD;

[0135] The n-type silicon substrate is placed in a boron diffusion furnace, and BCl3 is used as a boron source (the volume of the boron source in the atmosphere accounts for 20%). Boron diffusion is performed on the back of the n-type silicon substrate at 980°C for 2.5 hours to form p-type B-doped polysilicon (i.e., a boron-doped polysilicon layer). A 55nm thick BSG (borosilicate glass) is diffused on the outer layer of the boron-doped polysilicon layer.

[0136] Printing a corrosion-resistant organic polymer mask slurry on a target area on the back side BSG of an n-type silicon substrate, and drying it to form a patterned blocking mask layer; the corrosion-resistant organic polymer slurry is a waxy resin material, and the corrosion-resistant slurry is characterized by being acid-resistant but not alkali-resistant, such as 0915A of SunChemical Company of the United States; the grid line printing width of the patterned blocking mask layer is 180 μm, and the height after drying is 11.6 μm;

[0137] Chain single-sided HF was used to remove the BSG layer in non-target areas, the HF solution concentration was 3wt%, and the process time was 2 minutes;

[0138] The boron-doped polysilicon layer below the BSG layer in the non-target area is removed by etching with a fluorine-containing gas. The etching gas is F2, the etching pressure is 1 torr, the etching temperature is room temperature, and the reaction time is 10 seconds. The volume ratio of F2 in the F2+N2 mixed gas is 20%, and the carrier gas N2 flow rate is 20 sccm.

[0139] The patterned blocking mask layer was removed using a 3 wt % NaOH solution at a reaction temperature of 55° C. for 180 seconds;

[0140] A silicon oxide layer with a thickness of 1 nm and a phosphorus-doped amorphous silicon layer with a thickness of 250 nm are sequentially deposited on the back of an n-type silicon substrate by LPCVD; the n-type silicon substrate is placed in an annealing furnace and annealed at 800° C. for 2 h to form n-type P-doped polysilicon (i.e., phosphorus-doped polysilicon layer), and a 65 nm thick PSG (phosphorus silicon glass) is diffused on the outer layer of the phosphorus-doped polysilicon layer;

[0141] Laser ablation is performed on the PSG layer on the boron-doped polysilicon region on the back of the n-type silicon substrate. The area of ​​the laser ablation region is larger than the boron-doped polysilicon region. Chain acid polishing (HF+HNO3) equipment is used to remove silicon oxide, phosphosilicate glass, polysilicon and borosilicate glass coated on the front of the n-type silicon substrate. Then, the front of the n-type silicon substrate is texturized using NaOH in a tank cleaning machine. The back of the n-type silicon substrate will not be etched by alkali due to the protection of the phosphosilicate glass layer and the borosilicate glass layer. Finally, a mixed solution of HF and HCl is used for cleaning.

[0142] Aluminum oxide layers (AlOx) were prepared on the front and back sides of the n-type silicon substrate by ALD, and the thickness of the aluminum oxide layers was 6 nm.

[0143] A silicon nitride (SiNx) passivation anti-reflection layer is prepared on the front and back sides of an n-type silicon substrate by using a tubular PECVD method; wherein the thickness of the passivation anti-reflection layer on the front side of the n-type silicon substrate is 80 nm, and the thickness of the passivation anti-reflection layer on the back side of the n-type silicon substrate is 90 nm;

[0144] Using laser to open holes in the passivation anti-reflection layer on the back of the n-type silicon substrate, respectively forming a first electrode contact hole connected to the boron-doped polysilicon layer and a second electrode contact hole connected to the phosphorus-doped polysilicon layer;

[0145] forming a first electrode at the first electrode contact hole and a second electrode at the second electrode contact hole by screen printing; the first electrode is connected to the boron-doped polysilicon layer, and the second electrode is connected to the phosphorus-doped polysilicon layer;

[0146] The fill factor of the solar cell prepared in this embodiment is 82.4%, the photoelectric conversion efficiency is 25.73%, the open circuit voltage is 736mV, and the short circuit current is 42.3mA / cm 2 , the reverse current Irev2 is 0.6A.

[0147] Example 6

[0148] An n-type silicon substrate is provided, and damage removal and double-side polishing are performed, a silicon oxide tunneling layer with a thickness of 1.2 nm is formed on the back side of the silicon substrate by thermal oxidation at 850° C., and a p-type boron-doped amorphous silicon layer with a thickness of 350 nm is deposited on the back side of the n-type silicon substrate by LPCVD;

[0149] The n-type silicon substrate is placed in an annealing furnace, and the back side of the n-type silicon substrate is annealed at 1000°C for 3 hours to form p-type B-doped polysilicon (i.e., boron-doped polysilicon layer), and a 60nm thick BSG (borosilicate glass) is diffused on the outer layer of the boron-doped polysilicon layer;

[0150] Printing a corrosion-resistant organic polymer mask slurry on a target area on the back side BSG of an n-type silicon substrate, and drying it to form a patterned blocking mask layer; the corrosion-resistant organic polymer slurry is a waxy resin material, and the corrosion-resistant slurry is characterized by being acid-resistant but not alkali-resistant, such as 0915A of SunChemical Company of the United States; the grid line printing width of the patterned blocking mask layer is 300 μm, and the height after drying is 15 μm;

[0151] Chain single-sided HF was used to remove the BSG layer in non-target areas, the HF solution concentration was 5wt%, and the process time was 1 minute;

[0152] The boron-doped polysilicon layer under the BSG layer in the non-target area is removed by etching with a fluorine-containing gas. The etching gas is BrF3, the etching pressure is 1.5 torr, the etching temperature is room temperature, and the reaction time is 40 seconds.

[0153] The patterned blocking mask layer was removed using a 3 wt % NaOH solution at a reaction temperature of 55° C. for 180 seconds;

[0154] A silicon oxide layer with a thickness of 1.2 nm and an intrinsic amorphous silicon layer with a thickness of 350 nm are sequentially deposited on the back of an n-type silicon substrate by LPCVD; the n-type silicon substrate is placed in a phosphorus diffusion furnace, POCl3 is used as a phosphorus source (the volume of the phosphorus source in the atmosphere accounts for 20%), and phosphorus is diffused on the back of the n-type silicon substrate at a temperature of 810° C. for 1.5 h to form n-type P-doped polysilicon (i.e., phosphorus-doped polysilicon layer), and a 48 nm thick PSG (phosphorus silicon glass) is diffused on the outer layer of the phosphorus-doped polysilicon layer;

[0155] Laser ablation is performed on the PSG layer on the boron-doped polysilicon region on the back of the n-type silicon substrate. The area of ​​the laser ablation region is larger than the boron-doped polysilicon region. Chain acid polishing (HF+HNO3) equipment is used to remove silicon oxide, phosphosilicate glass, polysilicon and borosilicate glass coated on the front of the n-type silicon substrate. Then, the front of the n-type silicon substrate is texturized using NaOH in a tank cleaning machine. The back of the n-type silicon substrate will not be etched by alkali due to the protection of the phosphosilicate glass layer and the borosilicate glass layer. Finally, a mixed solution of HF and HCl is used for cleaning.

[0156] Aluminum oxide layers (AlOx) were prepared on the front and back sides of the n-type silicon substrate by ALD, and the thickness of the aluminum oxide layers was 6 nm.

[0157] A silicon nitride (SiNx) passivation anti-reflection layer is prepared on the front and back sides of an n-type silicon substrate by using a tubular PECVD method; wherein the thickness of the passivation anti-reflection layer on the front side of the n-type silicon substrate is 75 nm, and the thickness of the passivation anti-reflection layer on the back side of the n-type silicon substrate is 80 nm;

[0158] Using laser to open holes in the passivation anti-reflection layer on the back of the n-type silicon substrate, respectively forming a first electrode contact hole connected to the boron-doped polysilicon layer and a second electrode contact hole connected to the phosphorus-doped polysilicon layer;

[0159] forming a first electrode at the first electrode contact hole and a second electrode at the second electrode contact hole by screen printing; the first electrode is connected to the boron-doped polysilicon layer, and the second electrode is connected to the phosphorus-doped polysilicon layer;

[0160] The fill factor of the solar cell prepared in this embodiment is 82.5%, the photoelectric conversion efficiency is 25.55%, the open circuit voltage is 736mV, and the short circuit current is 42.0mA / cm 2 , the reverse current Irev2 is 1.1A.

[0161] Example 7

[0162] A p-type silicon substrate is provided, and damage removal and double-side polishing are performed, and a silicon oxide tunneling layer with a thickness of 1.5 nm and an intrinsic amorphous silicon layer with a thickness of 320 nm are sequentially deposited on the back side of the silicon substrate by LPCVD;

[0163] The p-type silicon substrate is placed in a boron diffusion furnace, and BCl3 is used as a boron source (the volume of the boron source in the atmosphere accounts for 20%). Boron is diffused on the back of the p-type silicon substrate at 1000°C for 2 hours to form p-type B-doped polysilicon (i.e., a boron-doped polysilicon layer). A 52nm thick BSG (borosilicate glass) is diffused on the outer layer of the boron-doped polysilicon layer.

[0164] Printing a corrosion-resistant organic polymer mask slurry on a target area on the back side BSG of a p-type silicon substrate, and drying it to form a patterned blocking mask layer; the corrosion-resistant organic polymer slurry is a waxy resin material, and the corrosion-resistant slurry is characterized by being acid-resistant but not alkali-resistant, such as 0915A of SunChemical Company of the United States; the grid line printing width of the patterned blocking mask layer is 300 μm, and the height after drying is 14.5 μm;

[0165] Place the p-type silicon substrate in an HF bath to remove the BSG layer on the front side and the BSG layer on the non-target area on the back side. The HF solution concentration is 3.5% and the process time is 1.5 minutes.

[0166] Fluorine-containing gas is used to etch away the boron-doped polysilicon layer below the BSG layer in the non-target area. The etching gas is XeF2, the etching pressure is 0.5 torr, the etching temperature is room temperature, and the reaction is carried out in a pulse cycle. The reaction chamber is inflated and delayed for 0.5 minutes. After the etching reaction is carried out for 5 seconds, the reaction chamber is evacuated to discharge the etching tail gas, and then the next cycle is carried out. The reaction is carried out for 2 cycles.

[0167] The patterned blocking mask layer was removed using a 3 wt % NaOH solution at a reaction temperature of 60° C. for 160 seconds;

[0168] A silicon oxide layer with a thickness of 1.5 nm and an intrinsic amorphous silicon layer with a thickness of 300 nm are sequentially deposited on the back of a p-type silicon substrate by LPCVD; the p-type silicon substrate is placed in a phosphorus diffusion furnace, POCl3 is used as a phosphorus source (the volume of the phosphorus source in the atmosphere accounts for 20%), and phosphorus is diffused on the back of the p-type silicon substrate at a temperature of 810° C. for 1 hour to form n-type P-doped polysilicon (i.e., phosphorus-doped polysilicon layer), and a 40 nm thick PSG (phosphorus silicon glass) is diffused on the outer layer of the phosphorus-doped polysilicon layer;

[0169] Laser ablation is performed on the PSG layer on the boron-doped polysilicon area on the back of the silicon substrate. The area of ​​the laser ablation area is larger than the boron-doped polysilicon area. Chain acid polishing (HF+HNO3) equipment is used to remove the silicon oxide, phosphosilicate glass, polysilicon and borosilicate glass plated on the front of the silicon substrate. Then, the silicon substrate is put into a tank cleaning machine and NaOH is used to texturize the front of the silicon substrate. The back of the silicon substrate will not be etched by alkali due to the protection of the phosphosilicate glass layer and the borosilicate glass layer. Finally, it is cleaned with a mixed solution of HF and HCl.

[0170] Aluminum oxide layers (AlOx) were prepared on the front and back sides of the silicon substrate by ALD, and the thickness of the aluminum oxide layers was 6 nm.

[0171] A silicon nitride (SiNx) passivation anti-reflection layer is prepared on the front and back sides of a p-type silicon substrate by using a tubular PECVD method; wherein the thickness of the passivation anti-reflection layer on the front side of the p-type silicon substrate is 70 nm, and the thickness of the passivation anti-reflection layer on the back side of the p-type silicon substrate is 75 nm;

[0172] Silver paste is printed on the back of the substrate by screen printing, and a first electrode and a second electrode are formed after drying and sintering; the first electrode is connected to the boron-doped polysilicon layer, and the second electrode is connected to the phosphorus-doped polysilicon layer;

[0173] The fill factor of the solar cell prepared in this embodiment is 82.8%, the photoelectric conversion efficiency is 25.8%, the open circuit voltage is 737mV, and the short circuit current is 42.2mA / cm 2 , the reverse current Irev2 is 0.8A.

[0174] Example 8

[0175] A p-type silicon substrate is provided, and damage removal and double-side polishing are performed, and a silicon oxide tunneling layer with a thickness of 1.1 nm and an intrinsic amorphous silicon layer with a thickness of 240 nm are sequentially deposited on the back side of the silicon substrate by LPCVD;

[0176] The p-type silicon substrate is placed in a boron diffusion furnace, and BCl3 is used as a boron source (the volume of the boron source in the atmosphere accounts for 20%). Boron is diffused on the back of the p-type silicon substrate at 950°C for 3 hours to form p-type B-doped polysilicon (i.e., a boron-doped polysilicon layer). A 65nm thick BSG (borosilicate glass) is diffused on the outer layer of the boron-doped polysilicon layer.

[0177] Printing a corrosion-resistant organic polymer mask slurry on a target area on the back side BSG of a p-type silicon substrate, and drying it to form a patterned blocking mask layer; the corrosion-resistant organic polymer slurry is a waxy resin material, and the corrosion-resistant slurry is characterized by being acid-resistant but not alkali-resistant, such as 0915A of SunChemical Company of the United States; the grid line printing width of the patterned blocking mask layer is 200 μm, and the height after drying is 13.7 μm;

[0178] The BSG layer in the non-target area on the back of the substrate was removed by anhydrous hydrogen fluoride vapor (VHF) combined with anhydrous ethanol vapor etching. The gas system consisted of HF, ethanol and N2, of which HF accounted for 50%. The reaction temperature was 45°C, the N2 flow rate was 5 sccm, and the reaction time was 3 minutes.

[0179] Fluorine-containing gas is used to etch away the boron-doped polysilicon layer below the BSG layer in the non-target area. The etching gas is XeF2, the etching pressure is 1.5 torr, the etching temperature is room temperature, and the reaction is carried out in a pulse cycle. The reaction chamber is inflated and delayed for 1 minute. After the etching reaction is carried out for 10 seconds, the reaction chamber is evacuated and the etching tail gas is discharged, and the next cycle is carried out. The reaction is carried out for 2 cycles;

[0180] The tunneling layer below the boron-doped polysilicon layer is etched away using XeF2 gas containing water vapor, the reaction temperature is room temperature, and the reaction time is 5 seconds;

[0181] The patterned blocking mask layer was removed using a 4 wt % NaOH solution at a reaction temperature of 60° C. for 200 seconds;

[0182] A silicon oxide layer with a thickness of 1.2 nm and an intrinsic amorphous silicon layer with a thickness of 230 nm are sequentially deposited on the back of a p-type silicon substrate by LPCVD; the p-type silicon substrate is placed in a phosphorus diffusion furnace, POCl3 is used as a phosphorus source (the volume of the phosphorus source in the atmosphere accounts for 20%), and phosphorus is diffused on the back of the p-type silicon substrate at a temperature of 800° C. for 1.5 h to form n-type P-doped polysilicon (i.e., phosphorus-doped polysilicon layer), and a 48 nm thick PSG (phosphorus silicon glass) is diffused on the outer layer of the phosphorus-doped polysilicon layer;

[0183] Laser ablation is performed on the PSG layer on the boron-doped polysilicon area on the back of the silicon substrate. The area of ​​the laser ablation area is larger than the boron-doped polysilicon area. Chain acid polishing (HF+HNO3) equipment is used to remove the silicon oxide, phosphosilicate glass, polysilicon and borosilicate glass plated on the front of the silicon substrate. Then, the silicon substrate is put into a tank cleaning machine and NaOH is used to texturize the front of the silicon substrate. The back of the silicon substrate will not be etched by alkali due to the protection of the phosphosilicate glass layer and the borosilicate glass layer. Finally, it is cleaned with a mixed solution of HF and HCl.

[0184] Aluminum oxide layers (AlOx) were prepared on the front and back sides of the silicon substrate by ALD, and the thickness of the aluminum oxide layers was 5 nm.

[0185] A silicon nitride (SiNx) passivation anti-reflection layer is prepared on the front and back sides of a p-type silicon substrate by using a tubular PECVD method; wherein the thickness of the passivation anti-reflection layer on the front side of the p-type silicon substrate is 72 nm, and the thickness of the passivation anti-reflection layer on the back side of the p-type silicon substrate is 90 nm;

[0186] Silver paste is printed on the back of the substrate by screen printing, and a first electrode and a second electrode are formed after drying and sintering; the first electrode is connected to the boron-doped polysilicon layer, and the second electrode is connected to the phosphorus-doped polysilicon layer;

[0187] The fill factor of the solar cell prepared in this embodiment is 82.5%, the photoelectric conversion efficiency is 25.75%, the open circuit voltage is 736mV, and the short circuit current is 42.3mA / cm 2 , the reverse current Irev2 is 0.7A.

[0188] Example 9

[0189] A 1.2nm thick silicon oxide tunneling layer is formed on the back of the p-type silicon substrate by thermal oxidation at 880°C, and an intrinsic amorphous silicon layer with a thickness of 270nm is deposited on the back of the silicon substrate by LPCVD;

[0190] The p-type silicon substrate is placed in a boron diffusion furnace, and BCl3 is used as a boron source (the volume of the boron source in the atmosphere accounts for 20%). Boron diffusion is performed on the back of the p-type silicon substrate at a temperature of 1000°C for 2.5 hours to form p-type B-doped polysilicon (i.e., a boron-doped polysilicon layer), and a 56nm thick BSG (borosilicate glass) is diffused on the outer layer of the boron-doped polysilicon layer;

[0191] Printing a corrosion-resistant organic polymer mask slurry on a target area on the back side BSG of a p-type silicon substrate, and drying it to form a patterned blocking mask layer; the corrosion-resistant organic polymer slurry is a waxy resin material, and the corrosion-resistant slurry is characterized by being acid-resistant but not alkali-resistant, such as 0915A of SunChemical Company of the United States; the grid line printing width of the patterned blocking mask layer is 170 μm, and the height after drying is 12 μm;

[0192] Place the p-type silicon substrate in an HF bath to remove the BSG layer on the front side and the BSG layer on the non-target area on the back side. The HF solution concentration is 4% and the process time is 2 minutes.

[0193] The boron-doped polysilicon layer under the BSG layer in the non-target area is removed by etching with a fluorine-containing gas. The etching gas is CIF3, the etching pressure is 6 torr, and the etching temperature is room temperature.

[0194] The patterned blocking mask layer was removed using a 3.5% NaOH solution at a reaction temperature of 50°C for 160 seconds. Organic residues on the surface of the silicon substrate were further removed using a 1% NaOH and 2% H2O2 mixed solution at a reaction temperature of 50°C for 150 seconds. The substrate was then cleaned with O3 for 10 minutes.

[0195] A silicon oxide layer with a thickness of 1.1 nm and an intrinsic amorphous silicon layer with a thickness of 260 nm are sequentially deposited on the back of a p-type silicon substrate by LPCVD; the p-type silicon substrate is placed in a phosphorus diffusion furnace, POCl3 is used as a phosphorus source (the volume of the phosphorus source in the atmosphere accounts for 20%), and phosphorus is diffused on the back of the p-type silicon substrate at a temperature of 810° C. for 2 hours to form n-type P-doped polysilicon (i.e., phosphorus-doped polysilicon layer), and a 60 nm thick PSG (phosphorus silicon glass) is diffused on the outer layer of the phosphorus-doped polysilicon layer;

[0196] Laser ablation is performed on the PSG layer on the boron-doped polysilicon area on the back of the silicon substrate. The area of ​​the laser ablation area is larger than the boron-doped polysilicon area. Chain acid polishing (HF+HNO3) equipment is used to remove the silicon oxide, phosphosilicate glass, polysilicon and borosilicate glass plated on the front of the silicon substrate. Then, the silicon substrate is put into a tank cleaning machine and NaOH is used to texturize the front of the silicon substrate. The back of the silicon substrate will not be etched by alkali due to the protection of the phosphosilicate glass layer and the borosilicate glass layer. Finally, it is cleaned with a mixed solution of HF and HCl.

[0197] Aluminum oxide layers (AlOx) were prepared on the front and back sides of the silicon substrate by ALD, and the thickness of the aluminum oxide layers was 6 nm.

[0198] A silicon nitride (SiNx) passivation anti-reflection layer is prepared on the front and back sides of a p-type silicon substrate by using a tubular PECVD method; wherein the thickness of the passivation anti-reflection layer on the front side of the p-type silicon substrate is 80 nm, and the thickness of the passivation anti-reflection layer on the back side of the p-type silicon substrate is 85 nm;

[0199] Silver paste is printed on the back of the substrate by screen printing, and a first electrode and a second electrode are formed after drying and sintering; the first electrode is connected to the boron-doped polysilicon layer, and the second electrode is connected to the phosphorus-doped polysilicon layer;

[0200] The fill factor of the solar cell prepared in this embodiment is 82.7%, the photoelectric conversion efficiency is 25.88%, the open circuit voltage is 736mV, and the short circuit current is 42.4mA / cm 2 , the reverse current Irev2 is 0.4A.

[0201] Comparative Example 1

[0202] Fig.10This is a schematic diagram of the structure of the solar cell of Comparative Example 1. The difference from Example 1 is that the wet alkali etching of the polysilicon during the cleaning process further etches into the substrate to a deeper depth of about 2 to 6 μm. With the current and future trend of thinning, this reduces the absorption of light by the silicon wafer and affects the efficiency of the battery. In addition, wet alkali etching is an immersion etching, and the BSG layer in the target area will also be corroded by the alkali. After a long wet process, areas where the BSG layer is not dense enough may be drilled, causing local damage to the doped polysilicon below. In the subsequent process of forming heterogeneously doped polysilicon, heterogeneous dopants enter, and the finished battery will leak electricity here. The solar cell prepared in this comparative example has a fill factor of 82.0%, a photoelectric conversion efficiency of 25.31%, an open circuit voltage of 730 mV, and a short circuit current of 42 mA / cm 2 , the reverse current Irev2 is 5 A. From the reverse current data, it can be seen that wet etching will cause leakage.

[0203] Since the above embodiment adopts the fluorine-containing gas etching process, the tunneling layer on the surface of the substrate becomes the stop layer for etching polysilicon, and the silicon substrate will not be corroded downward. The organic polymer mask on the target area serves as a mask layer in the dry etching process. In addition, the BSG layer under the organic polymer mask can also play a protective role in the dry etching process of removing the doped polysilicon layer, so the target area will not be corroded during the etching of polysilicon, which greatly improves the reliability of the battery.

[0204] The above are only preferred specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for preparing a back contact solar cell, characterized in that: Prepared by method one or method two; The method 1 comprises the following steps: Providing a silicon substrate; Preparing a tunneling layer on the back side of the silicon substrate; preparing an intrinsic amorphous silicon layer on the tunneling layer; Performing high-temperature diffusion on the intrinsic amorphous silicon layer to prepare a doped polysilicon layer and a doped silicon oxide layer, wherein the doped silicon oxide layer is a BSG or PSG layer, and the doped silicon oxide layer is located above the doped polysilicon layer; forming an organic polymer mask layer in target areas of the doped polysilicon layer and the doped silicon oxide layer; Using a first fluorine-containing gas to etch and remove the doped silicon oxide layer in non-target areas; Using a second fluorine-containing gas to etch and remove the doped polysilicon layer in non-target areas; removing the organic polymer mask layer and cleaning it; The second method comprises the following steps: Providing a silicon substrate; Preparing a tunneling layer on the back side of the silicon substrate; preparing a doped amorphous silicon layer on the tunneling layer; Performing annealing to convert the doped amorphous silicon layer into a doped polysilicon layer; Oxidizing the surface of the doped polysilicon layer to form a doped silicon oxide layer, wherein the doped silicon oxide layer is a BSG or PSG layer; forming an organic polymer mask layer in target areas of the doped polysilicon layer and the doped silicon oxide layer; Using a first fluorine-containing gas to etch and remove the doped silicon oxide layer in non-target areas; Using a second fluorine-containing gas to etch and remove the doped polysilicon layer in non-target areas; The organic polymer mask layer is removed and cleaned.

2. The method for preparing a back contact solar cell according to claim 1, characterized in that: At least two of the composition, concentration and pressure of the first fluorine-containing gas are different from those of the second fluorine-containing gas.

3. The method for preparing a back contact solar cell according to claim 1, characterized in that: The etching gas in the first fluorine-containing gas includes HF, or a mixed gas of one of F2, XeF2, CIF, CIF3, IF5, BrF5, BrF3 and water vapor, or a mixed gas of a combination of more than one gas and water vapor, or a combination of one or more of CF4, C2F6, C3F8, C4F8, C4F6, C5F8, CHF3.

4. The method for preparing a back contact solar cell according to claim 1, characterized in that: The etching gas in the second fluorine-containing gas includes one or more of Cl2, CF4, HCl, HBr, SF6, C4F6, CHF3, NF3, O2, or one or more of F2, XeF2, CIF, CIF3, IF5, BrF5, BrF3.

5. The method for preparing a back contact solar cell according to claim 1, characterized in that: The first fluorine-containing gas and the second fluorine-containing gas contain a diluent gas or a carrier gas, and the diluent gas or the carrier gas includes one or a combination of more than one of He, Ar, and N2.

6. The method for preparing a back contact solar cell according to claim 1, characterized in that: The material of the organic polymer mask layer is epoxy or acrylic adhesive; the material of the tunneling layer is one or more of silicon oxynitride, silicon carbide, silicon nitride, aluminum oxide and silicon oxide.

7. The method for preparing a back contact solar cell according to claim 1, characterized in that: After removing the doped polysilicon layer in the non-target area, the method for preparing a back-contact solar cell further includes: removing the tunneling layer in the non-target area.

8. The method for preparing a back contact solar cell according to claim 7, characterized in that: The tunnel layer in the non-target area is etched and removed by using a third fluorine-containing gas; the etching gas in the third fluorine-containing gas is a mixed gas of fluorine-containing gas and water vapor.

9. A back-contact solar cell prepared by the preparation method according to any one of claims 1 to 8.

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