Semiconductor drive device and power conversion device

Abstract

This semiconductor drive device (100) is provided with: a timing generation unit (12) that generates gate ON command signals for each of a plurality of gate terminals on the basis of ON / OFF command signals from the outside; and a gate command waveform generation unit (13) that generates a first gate command waveform corresponding to at least one first gate terminal among the plurality of gate terminals and a second gate command waveform corresponding to at least one second gate terminal on the basis of the gate ON command signal. A waveform control unit (20) that controls one or both of the first gate command waveform and the second gate command waveform when the multi-gate semiconductor switching element (20) transitions from the non-conductive state to the conductive state and / or transitions from the conductive state to the non-conductive state; and a signal amplification unit (14) that uses either or both of the first gate command waveform and the second gate command waveform as an input waveform, and amplifies the input waveform such that the output waveform follows the input waveform.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor drive device and a power conversion device. Background Art

[0002] As one of the countermeasures against global warming, energy conservation through power electronics technology is increasingly expected. In particular, in order to improve the efficiency of power conversion devices by turning on / off a plurality of semiconductor switching elements, it is required to reduce the loss of semiconductor switching elements constituting the power conversion device.

[0003] Representative semiconductor switching elements include voltage-driven semiconductor switching elements such as IGBT (Insulated Gate Bipolar Transistor) and MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), and diodes that are connected in parallel with the semiconductor switching elements to perform a rectifying function.

[0004] As a means of improving the trade-off between the conduction loss and the switching loss of a semiconductor switch element, there is an application of a dual-gate semiconductor switch element having two independent gate terminals. The dual-gate semiconductor switch element is characterized in that, for example, during a shutdown operation, one gate terminal is disconnected sufficiently earlier than the other gate terminal and then the other gate terminal is disconnected. According to the control method, the shutdown operation is performed in a state where a portion of the carriers in the dual-gate semiconductor switch element are extracted in advance, so that the carrier extraction time can be shortened, and thus the shutdown loss can be reduced.

[0005] Furthermore, by setting the time difference between the on / off actions of the two to be short so that the timing of turning on / off the other gate terminal after turning on / off one gate terminal is within the switching action period, the effect of making the switching characteristics transiently variable, namely the active gate effect, can be obtained.

[0006] For example, as an example of the active gate effect of a single-gate semiconductor switch element, there is a method of switching the gate resistance during the turn-on operation. It is known that the trade-off relationship between the turn-on loss of the semiconductor switch element and the recovery voltage change rate dV / dt of the diode of the opposite arm can be improved by applying the switching method. In contrast, in a dual-gate semiconductor switch element, by driving based on the time difference of the two gate terminals, an effect similar to the above-mentioned switching method can be obtained.

[0007] As a method of driving a dual-gate conductor switch element by providing a time difference between two gate terminals, for example, in a semiconductor device and a control method of a semiconductor device disclosed in Patent Document 1, the following structure is shown: a delay unit is provided to delay a signal inputted from the semiconductor device to a control signal input terminal by a delay time L, and a logical AND unit is provided to calculate a logical AND of a signal inputted to the control signal input terminal and a signal delayed in the delay unit, and the output of the delay unit and the output of the logical AND unit are connected to two gate terminals of the dual-gate IGBT, respectively. In the structure of the semiconductor device disclosed in Patent Document 1, when the time difference between the voltage waveforms provided to the two gate terminals is set short, the above-mentioned active gate effect can be obtained.

[0008] In addition, in the semiconductor device and the driving method of the semiconductor device described in Patent Document 2, the following method is disclosed: when a dual-gate IGBT transitions from a non-conducting state to a conducting state, a voltage greater than a threshold voltage is applied to the first gate terminal in advance of a first specified time compared to the second gate terminal, and when transitioning from the conducting state to the non-conducting state, a voltage less than the threshold voltage is applied to the second gate terminal in advance of a second specified time compared to the first gate terminal, and the first specified time and the second specified time are variably controlled so that the time variation of the collector voltage generated when transitioning from the non-conducting state to the conducting state and when transitioning from the conducting state to the non-conducting state is approximately constant.

[0009] When the time difference between the voltage waveforms applied to the two gate electrodes is set short in the above configuration, the robustness against the voltage change rate dV / dt caused by noise, the load current of the surge voltage, the temperature, etc. can be improved by changing the time difference between the voltage waveforms.

[0010] Patent Document 1: Japanese Patent Application Publication No. 2019-103286

[0011] Patent Document 2: Japanese Patent Application Publication No. 2020-162022 Summary of the invention

[0012] Problem that the invention aims to solve

[0013] However, in a semiconductor device and a control method for a semiconductor device described in, for example, Patent Document 1, when the time difference is set short so that the timing of turning on / off one gate terminal of a dual-gate IGBT after turning on / off the other gate terminal is within the switching action period in order to obtain the above-mentioned active gate effect, the following problems arise: a first problem of increased noise and surge voltage due to the delayed control signal input terminal being turned on within the switching action period; and a second problem related to the general problem of active gate drive generated in the driving method of turning on the delayed control signal input terminal within the switching action period, namely, the robustness to various conditions such as load current, temperature, and gate threshold voltage deviation.

[0014] The present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to provide a semiconductor drive device and a power conversion device having excellent robustness, which improve the trade-off between noise and surge voltage generated in the switching operation of a multi-gate semiconductor switch element and switching loss.

[0015] Solutions for solving problems

[0016] The semiconductor driving device according to the present disclosure is a semiconductor driving device for driving a multi-gate semiconductor switching element having a plurality of gate terminals, and includes:

[0017] a timing generating unit for generating gate-on command signals for the plurality of gate terminals respectively based on an on / off command signal from the outside;

[0018] a gate command waveform generating unit, which generates a first gate command waveform corresponding to at least one first gate terminal of the plurality of gate terminals and a second gate command waveform corresponding to at least one second gate terminal, respectively, based on the gate turn-on command signal, and controls the waveforms of either or both of the first gate command waveform and the second gate command waveform when the multi-gate semiconductor switch element transitions from a non-conducting state to a conducting state and from a conducting state to a non-conducting state; and

[0019] The signal amplifier receives one or both of the first gate command waveform and the second gate command waveform as input waveforms and amplifies the input waveforms so that the output waveforms follow the input waveforms.

[0020] The power conversion device according to the present disclosure comprises:

[0021] any one of an inverter device for converting DC power into AC power, having a multi-gate semiconductor switching element as a semiconductor switching element, a boost converter device for boosting the voltage of DC power, a buck converter device for bucking the voltage of DC power, an AC-DC converter device for converting AC power into DC power, a boost inverter device including the boost converter device and the inverter device, and a buck inverter device including the buck converter device and the inverter device; and

[0022] The above-mentioned semiconductor driving device drives the multi-gate semiconductor switching element.

[0023] Effects of the Invention

[0024] According to the semiconductor drive device and the power conversion device using the semiconductor drive device involved in the present disclosure, a structure is set to realize the gate drive of the dual-gate semiconductor switching element by feedforward control following the gate command waveform, so that the change rate of the gate terminal voltage can be freely suppressed. As a result, even if it is driven based on a short time difference between the gate terminals in the dual-gate semiconductor switching element, it is possible to suppress noise and surge voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a block diagram showing the structure of the semiconductor driving device according to the first embodiment.

[0026] Figure 2A This is a circuit diagram showing an example of a specific configuration of a signal amplifier in the semiconductor driving device according to the first embodiment.

[0027] Figure 2B This is a circuit diagram showing an example of a specific configuration of a signal amplifier in the semiconductor driving device according to the first embodiment.

[0028] Figure 2C This is a circuit diagram showing an example of a specific configuration of a signal amplifier in the semiconductor driving device according to the first embodiment.

[0029] Figure 2D This is a circuit diagram showing an example of a specific configuration of a signal amplifier in the semiconductor driving device according to the first embodiment.

[0030] Figure 3A This is a diagram showing an example of a specific configuration of a gate command generating unit in the semiconductor driving device according to the first embodiment.

[0031] Figure 3B This is a diagram showing an example of a specific configuration of a gate command generating unit in the semiconductor driving device according to the first embodiment.

[0032] Figure 3C This is a diagram showing an example of a specific configuration of a gate command generating unit in the semiconductor driving device according to the first embodiment.

[0033] Figure 3D This is a diagram showing an example of a specific configuration of a gate command generating unit in the semiconductor driving device according to the first embodiment.

[0034] Figure 3E This is a diagram showing an example of a specific configuration of a gate command generating unit in the semiconductor driving device according to the first embodiment.

[0035] Figure 3F This is a diagram showing an example of a specific configuration of a gate command generating unit in the semiconductor driving device according to the first embodiment.

[0036] Figure 4A This is a diagram showing an example of a specific configuration of a gate command generating unit in the semiconductor driving device according to the first embodiment.

[0037] Figure 4B This is a diagram showing an example of a specific configuration of a gate command generating unit in the semiconductor driving device according to the first embodiment.

[0038] Figure 5 This is a diagram showing an example of a timing chart of each signal in the semiconductor driving device according to the first embodiment.

[0039] Figure 6 This is a diagram showing an example of a timing chart of each signal in the semiconductor driving device according to the first modification of the first embodiment.

[0040] Figure 7 This is a diagram showing an example of a timing chart of each signal in the semiconductor driving device according to the second modification of the first embodiment.

[0041] Figure 8 This is a block diagram showing the structure of a semiconductor driving device according to the second embodiment.

[0042] Fig. 9 This is a block diagram showing the structure of a power conversion device according to the third embodiment.

[0043] Fig.10 This is a block diagram showing the structure of a power conversion device according to the fourth embodiment.

[0044] Fig.11 This is a block diagram showing the structure of a power conversion device according to the fifth embodiment.

[0045] Fig.12This is a circuit diagram showing a configuration example of a gate driving unit in a semiconductor driving device according to a comparative example.

[0046] Fig.13 This is a schematic waveform diagram for explaining a problem of turn-on driving when a short time difference is given to two gate terminals in a semiconductor driving device according to a comparative example.

[0047] Fig.14 This is a diagram showing an example of hardware of the semiconductor drive device according to the first embodiment and the power conversion devices according to the second to fifth embodiments. DETAILED DESCRIPTION

[0048] Implementation method 1.

[0049] Embodiment 1 is described below based on the figures. In the following description, the same or equivalent components are indicated by adding the same reference numerals. In addition, the description of the isolation components (e.g., elements such as a clamping diode and a short-circuit protection circuit for gate voltage protection, represented by an optical coupler, an optical fiber module, a pulse transformer, etc.) for insulating the on / off command signal from the upper level input to the semiconductor drive device 100 is omitted.

[0050] <Structure of Semiconductor Driving Device According to Embodiment 1>

[0051] Figure 1 is a block diagram showing the structure of the semiconductor driving device 100 according to the first embodiment. Figure 1 In the embodiment of the present invention, as an example of the semiconductor driving device 100, a structure for driving an IGBT module 25 composed of a dual-gate IGBT 20 and a diode 21 is illustrated. Regarding the driving voltage applied to the gate terminal of the dual-gate IGBT 20, that is, the gate voltage Vge, the positive side voltage is VP and the negative side voltage is VN based on the emitter potential FG.

[0052] The semiconductor driving device 100 according to the first embodiment includes a timing generating unit 12, a gate command waveform generating unit 13, a signal amplifier 14, and a driving voltage generating unit 15. The gate command waveform generating unit 13 further includes a first gate command waveform generating unit 13A and a second gate command waveform generating unit 13B. The signal amplifier 14 further includes a first signal amplifier 14A and a second signal amplifier 14B.

[0053] The timing generation unit 12 generates the driving timing of the first gate terminal Gs as the switch gate of the dual-gate IGBT 20 and the driving timing of the second gate terminal Gc as the control gate of the dual-gate IGBT 20, respectively, based on the on / off command signal Sgd input from the outside of the semiconductor drive device 100, and outputs them as the first gate on command signal Sg1 and the second gate on command signal Sg2. In addition, the first gate on command signal Sg1 is a signal corresponding to the first gate terminal Gs of the dual-gate IGBT 20, and the second gate on command signal Sg2 is a signal corresponding to the second gate terminal Gc of the dual-gate IGBT 20.

[0054] The gate command waveform generating unit 13 generates a first gate command waveform Vgr1 in the first gate command waveform generating unit 13A based on the first gate-on command signal Sg1 output from the timing generating unit 12. In addition, the gate command waveform generating unit 13 generates a second gate command waveform Vgr2 in the second gate command waveform generating unit 13B based on the second gate-on command signal Sg2 output from the timing generating unit 12.

[0055] The signal amplifier 14 amplifies the first gate command waveform Vgr1 and the second gate command waveform Vgr2 output from the gate command waveform generator 13, respectively, and outputs them to the dual-gate IGBT 20 provided outside the semiconductor drive device 100. That is, the first signal amplifier 14A amplifies the input first gate command waveform Vgr1 to output the first gate voltage VgeS, and the second signal amplifier 14B amplifies the input second gate command waveform Vgr2 to output the second gate voltage VgeC to the dual-gate IGBT 20 provided outside the semiconductor drive device 100. The first gate voltage VgeS is applied to the first gate terminal Gs of the dual-gate IGBT 20, and the second gate voltage VgeC is applied to the second gate terminal Gc of the dual-gate IGBT 20.

[0056] The semiconductor drive device 100 involved in embodiment 1 is characterized in that it is set as the following structure: the gate command waveform is pre-generated as a desired waveform in the gate command waveform generating unit 13, and the gate command waveform is amplified in the signal amplifying unit 14, thereby making the dual-gate IGBT 20 follow the gate command waveform, that is, realizing the gate drive of the dual-gate semiconductor switching element through feedforward control.

[0057] <Configuration of Each Component of the Semiconductor Driving Device According to Embodiment 1>

[0058] The following describes the specific structures of the components constituting the semiconductor drive device 100 according to Embodiment 1, namely, the timing generation unit 12, the gate command waveform generation unit 13, and the signal amplifier 14. In addition, the components are not limited to the structures shown in the figure, and the structures shown in the figure can be combined, or components can be added or other structures that achieve the same function can be used.

[0059] <Specific Configuration Example of the Signal Amplifier 14>

[0060] Figure 2A , Figure 2B , Figure 2C , Figure 2D Each of the circuit diagrams shows an example of a specific structure of the first signal amplifier 14A and the second signal amplifier 14B in the signal amplifier 14 of the semiconductor driving device 100 according to the first embodiment. Figure 2A , Figure 2B , Figure 2C , Figure 2D In order to simplify the structure, the base resistor is omitted, and a base resistor is added as needed. The signal amplifier 14 takes one or both of the first gate command waveform and the second gate command waveform as input waveforms, and amplifies the input waveforms so that the output waveforms follow the input waveforms.

[0061] The above-mentioned “amplifying the input waveform so that the output waveform follows the input waveform” will be described below.

[0062] As the semiconductor driving device 100, it is desired to provide a gate command waveform as an input signal to the gate terminal. However, when the load capacitance connected to the semiconductor driving device 100 is large, the output voltage waveform changes compared to the waveform of the input signal. For example, in the gate command waveform, a Miller period (a plateau-like stagnation period) will appear according to the dynamic change of the load capacitance, and the signal amplifier 14 flows a large current during the Miller period to operate in a manner consistent with the gate command waveform, that is, in a follow-up manner. On the contrary, if the load impedance increases, the signal amplifier 14 reduces the current to operate in a manner consistent with the gate command waveform, that is, in a follow-up manner. For example, if the signal amplifier 14 is Figure 2A The structure automatically adjusts the current so that Figure 2A The output voltage on the right side is Figure 2A The base voltage on the left side of is consistent. It can be said that the adjustment amplifies the input waveform in such a way that the output waveform follows the input waveform. Therefore, the voltage amplification factor of the signal amplifier 14 can also be 1.

[0063] Figure 2A1 is a circuit diagram showing the structure of the signal amplifier 14P. The signal amplifier 14P is composed of a complementary emitter follower circuit including an NPN transistor Q1 and a PNP transistor Q2. Fig.12 In the constant voltage driving circuit of the comparative example shown, the gate current is limited by the gate resistor. In the structure of the signal amplifier 14P of the semiconductor driving device 100 according to the first embodiment, the gate current is automatically adjusted so that the output waveform follows the input voltage waveform.

[0064] In the signal amplifier 14P, the output voltage drops by an amount corresponding to the threshold voltage of the NPN transistor Q1 and the PNP transistor Q2, and the maximum value of the gate current is limited by the current driving performance of the NPN transistor Q1 and the PNP transistor Q2, so a waveform difference may occur between the input voltage waveform and the output waveform. As a method for preventing the occurrence of the inconvenience of the output waveform being distorted due to the threshold voltage of the NPN transistor Q1 and the PNP transistor Q2, a known method such as adding a diode for compensating the threshold voltage to the base terminal may be applied.

[0065] Figure 2B 1 is a circuit diagram showing the structure of the signal amplifier 14Q. The signal amplifier 14Q is composed of complementary emitter follower circuits including NPN transistor Q1 and PNP transistor Q2, and NPN transistor Q3 and PNP transistor Q4. The above-mentioned signal amplifier 14P is composed of a one-stage complementary emitter follower circuit, while the signal amplifier 14Q is characterized by being composed of a two-stage complementary emitter follower circuit. According to the structure of the signal amplifier 14Q, the current driving force of the signal amplifier 14 is further increased.

[0066] Figure 2C 1 is a circuit diagram showing the structure of the signal amplifier 14R. The signal amplifier 14R is configured by adding a voltage follower circuit using an operational amplifier OP1 (operational amplifier) ​​to the front stage of the complementary emitter follower circuit composed of an NPN transistor Q1 and a PNP transistor Q2. The structure of the signal amplifier 14R has the following effect: the base current of the NPN transistor Q1 and the PNP transistor Q2 of the complementary emitter follower circuit of the rear stage is prevented from being consumed, thereby changing the input voltage waveform.

[0067] Figure 2D1 is a circuit diagram showing the structure of the signal amplifier 14S. The signal amplifier 14S is formed by adding a gate resistor R2 to the disconnected side of a complementary emitter follower circuit composed of an NPN transistor Q1 and a PNP transistor Q2. According to the structure of the signal amplifier 14S, the signal amplifier 14S is applied during the turn-on operation, which has a high effect on the semiconductor drive device 100 involved in the first embodiment, and the conventional constant voltage drive is used during the turn-off operation, thereby simplifying the structure of the gate command waveform generator 13.

[0068] <Specific Configuration Example I of Gate Command Waveform Generator 13>

[0069] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F Each of the circuit diagrams is a circuit diagram showing an example of a specific structure of a first gate command waveform generating unit 13A and a second gate command waveform generating unit 13B in the gate command waveform generating unit 13 of the semiconductor driving device 100 according to Embodiment 1. The gate command waveform generating unit 13 is characterized in that the waveform is controlled by controlling either or both of the differential value of the first gate command waveform and the differential value of the second gate command waveform.

[0070] Figure 3A 13P. The gate command waveform generating unit 13P generates a CR charging and discharging waveform based on the resistor R3 and the capacitor C1, that is, a voltage whose second-order differential value is less than zero (d 2 V / dt 2 <0) as the gate command waveform. The resistor R4 functions as a base resistor for limiting the base current of the subsequent signal amplifier 14. In addition, at least one portion of the gate command waveform may include a charging voltage shape or a discharging voltage shape generated by the electrostatic capacitor and the resistor.

[0071] Figure 3B The gate command waveform generating unit 13Q is a circuit diagram showing the gate command waveform generating unit 13Q. The gate command waveform generating unit 13Q is formed by using constant current diodes DS1 and DS2 instead of Figure 3A The gate command waveform generator 13P has a resistor R3 as shown. The gate command waveform generator 13Q generates a ramp waveform with a constant slope, that is, a voltage with a second-order differential value of zero (d 2 V / dt 2 =0).

[0072] Figure 3C 1 is a circuit diagram showing the gate command waveform generating unit 13R. The gate command waveform generating unit 13R is connected to Figure 3AThe gate command waveform generator 13P shown in the figure has a structure in which Zener diodes DZ1 and DZ2 and a resistor R5 are provided in parallel with a resistor R3. The gate command waveform generator 13R functions to increase the slope of the gate command waveform by increasing the charging current and discharging current of the capacitor C1 immediately after the start of turning on and immediately after the start of turning off.

[0073] Figure 3D 1 is a circuit diagram showing a gate command waveform generating unit 13S. The gate command waveform generating unit 13S is a circuit diagram showing a gate command waveform generating unit 13S. Figure 3B The gate command waveform generation unit 13Q shown in FIG. Figure 3C The gate command waveform generating unit 13R shown in FIG. Figure 3A The gate command waveform generator 13P shown in FIG. Figure 3B The gate command waveform generating unit 13Q shown in the figure has a structure in which the constant current diodes DS1 and DS2 are provided in parallel with the Zener diodes DZ1 and DZ2 and the resistor R5.

[0074] Figure 3E 1 is a circuit diagram showing a gate command waveform generating unit 13T. The gate command waveform generating unit 13T is a structure that assumes the following: Figure 3A The resistor R3 of the gate command waveform generating unit 13P shown in FIG. 1 is connected in parallel with a diode D2 and a resistor R5, so that the gate command waveform during the turn-off operation is set to a rectangular wave shape, and the gate command waveform is connected to the resistor R3 of the gate command waveform generating unit 13P shown in FIG. Figure 2D The signal amplifier 14S shown is combined to make the shutdown operation a constant voltage drive.

[0075] Figure 3F 1 is a circuit diagram showing a gate command waveform generating unit 13U. The gate command waveform generating unit 13U is a circuit diagram showing a gate command waveform generating unit 13U. Figure 3B The gate command waveform generation unit 13Q shown in FIG. Figure 3E The gate command waveform generating unit 13T shown in FIG. Figure 3A The gate command waveform generating unit 13P shown in FIG. Figure 3B The gate command waveform generating unit 13P shown has a structure in which a diode D2 and a resistor R5 are added in parallel to the resistor R3.

[0076] <Specific Configuration Example II of Gate Command Waveform Generator 13>

[0077] The above FIG. 3A to FIG. 3F The configuration examples of the gate command waveform generator 13 shown in FIG. 1 are configurations using resistors, capacitors, and diodes. Figure 4A and Figure 4BEach example of the gate command waveform generating unit 13 shown is a configuration example using an operational amplifier, a comparator, or the like.

[0078] Figure 4A 1 is a circuit diagram showing a gate command waveform generator 13V. The gate command waveform generator 13V is a structure formed by combining a logic inverting circuit INV1 with an integrating circuit composed of an operational amplifier OP2 (operational amplifier), a resistor R6, a resistor R7, and a capacitor C2. The gate command waveform generator 13V generates a gate command waveform as an input signal. Figure 3B The gate command waveform generating unit 13P shown in FIG. 1 is a ramp-shaped waveform with a constant slope, that is, a voltage with a second-order differential value of zero (d 2 V / dt 2 =0).

[0079] Figure 4B : is a circuit diagram showing a gate command waveform generating unit 13W. The gate command waveform generating unit 13W includes: a window comparator, which is composed of comparators CP1 and CP2, and determines a reference range of greater than VrefL and less than VrefH; a voltage limiting circuit, which is composed of a Zener diode DZ3 and an NPN transistor Q3; two identical ramp-type waveform generating circuits of constant current diodes DS3 and DS4 and capacitor C3, and constant current diodes DS5 and DS6 and capacitor C4; and resistors R8 and R9. With regard to the waveform generated by the gate command waveform generating unit 13W, when the ramp-type waveform used as a reference is within the reference range of greater than VrefL and less than VrefH, a platform-type waveform determined by the Zener voltage of DZ3, that is, a waveform in which the first-order differential value of the voltage is zero (dV / dt=0) can be set in the output ramp-type waveform.

[0080] <Operation of Semiconductor Driving Device According to Embodiment 1>

[0081] Figure 5 1 is a diagram showing an example of a timing chart of each signal indicating the operation of the semiconductor drive device 100 according to the first embodiment. As a specific configuration of the gate command waveform generating unit 13 of the semiconductor drive device 100 according to the first embodiment, Figure 3A The gate command waveform generating unit 13P shown in FIG. The gate command waveform generating unit 13P generates a CR charging and discharging waveform based on the resistor R3 and the capacitor C1, that is, a voltage whose second-order differential value is less than zero (d 2 V / dt 2 <0) as the gate command waveform. In addition, at least one portion of the gate command waveform may include a charging voltage shape or a discharging voltage shape generated by the electrostatic capacitance and the resistor.

[0082] Figure 5 The waveforms shown are, from the upper side, the on-off command signal Sgd, the first gate on-command signal Sg1, the second gate on-command signal Sg2, the first gate command waveform Vgr1 and the second gate command waveform Vgr2, the first gate voltage VgeS, the second gate voltage VgeC, the collector current Ic, and the collector voltage Vce.

[0083] The operation of the semiconductor driving device 100 according to the first embodiment will be described below with reference to Figure 5 to explain.

[0084] <Turning On Operation of Semiconductor Drive Device According to Embodiment 1>

[0085] First, a series of actions of each signal when the on / off command signal Sgd changes from off to on, i.e., during the opening action, will be described. At time t5, the on / off command signal Sgd from the outside changes from off to on. That is, the on / off command signal Sgd changes from the Lo state to the Hi state. At time t5, based on the closing action of the on / off command signal Sgd, the timing generation unit 12 outputs the first gate on command signal Sg1. That is, the first gate on command signal Sg1 changes from the Lo state to the Hi state.

[0086] At time t6, based on the on-off command signal Sgd's on-action, the timing generator 12 outputs the second gate on-command signal Sg2. The second gate on-command signal Sg2 is outputted delayed by a preset time, ie, a time difference of t6-t5, relative to the first gate on-command signal Sg1.

[0087] At time t5, the first gate command waveform generator 13A generates the first gate command waveform Vgr1 based on the turn-on operation of the first gate turn-on command signal Sg1. The first gate command waveform Vgr1 starts to rise from time t5, but since the circuit structure of the gate command waveform generator 13P is applied as the first gate command waveform generator 13A, it presents a waveform as if the rate of increase of the voltage is limited, that is, the second-order differential value of the voltage is less than zero (d 2 V / dt 2 <0).

[0088] At time t6, based on the turn-on action of the second gate turn-on command signal Sg2, the second gate command waveform generator 13B generates the second gate command waveform Vgr2. The second gate command waveform Vgr2 starts to rise from time t6, but since the circuit structure of the gate command waveform generator 13P is applied as the second gate command waveform generator 13B, it presents a waveform as if the rate of increase of the voltage is limited, that is, the second-order differential value of the voltage is less than zero (d2 V / dt 2 The second gate command waveform Vgr2 is outputted with a delay of a preset time, that is, a time difference of t6-t5, relative to the first gate command waveform Vgr1.

[0089] At time t5, the first signal amplifier 14A amplifies the input first gate command waveform Vgr1 and outputs the first gate voltage VgeS. The first gate voltage VgeS reflects the waveform of the first gate command waveform Vgr1 and presents a waveform in which the rate of increase of the voltage is limited, that is, the second-order differential value of the voltage is less than zero (d 2 V / dt 2 <0).

[0090] At time t6, the second signal amplifier 14B amplifies the input second gate command waveform Vgr2 and outputs the second gate voltage VgeC. The second gate voltage VgeC reflects the waveform of the second gate command waveform Vgr2 and presents a waveform in which the rate of increase of the voltage is limited, that is, the second-order differential value of the voltage is less than zero (d 2 V / dt 2 In addition, the second gate voltage VgeC is outputted with a delay of a predetermined time, that is, a time difference of t6-t5, relative to the first gate voltage VgeS.

[0091] The first gate voltage VgeS and the second gate voltage VgeC are respectively output to the first gate terminal Gs and the second gate terminal Gc of the double-gate IGBT 20 provided outside the semiconductor driving device 100 .

[0092] At time t7 when the first gate voltage VgeS becomes equal to or higher than the threshold voltage Vth, the collector current Ic of the dual-gate IGBT 20 rises from the zero state before time t7 and becomes a constant value at time t8 when the second gate voltage VgeC becomes equal to or higher than the threshold voltage Vth.

[0093] At time t7 when the first gate voltage VgeS becomes equal to or higher than the threshold voltage Vth, the collector voltage Vce of the dual-gate IGBT 20 decreases from the state of VB+Vf before time t7, and becomes the on-voltage Von which is a constant value at time t8 when the second gate voltage VgeC becomes equal to or higher than the threshold voltage Vth.

[0094] The above is a series of operations of each signal when the on / off command signal Sgd changes from off to on, that is, when the on operation is performed.

[0095] <Shutdown Operation of Semiconductor Driving Device According to Embodiment 1>

[0096] Next, a series of operations of each signal when the on / off command signal Sgd changes from on to off, that is, when the shutdown operation is performed, will be described.

[0097] At time t9, the on / off command signal Sgd from the outside changes from on to off. That is, the on / off command signal Sgd changes from the Hi state to the Lo state. At time t9, based on the off action of the on / off command signal Sgd, the timing generation unit 12 turns off the first gate on command signal Sg1. That is, the first gate on command signal Sg1 changes from the Hi state to the Lo state.

[0098] At time t10, the timing generator 12 turns off the second gate-on command signal Sg2 based on the turning off of the on / off command signal Sgd. The turning off of the second gate-on command signal Sg2 is delayed by a preset time, that is, a time difference of t10-t9, relative to the turning off of the first gate-on command signal Sg1.

[0099] At time t9, based on the turning-off action of the first gate-on command signal Sg1, the first gate command waveform generator 13A turns off the first gate command waveform Vgr1. The first gate command waveform Vgr1 starts to drop from time t9, but since the circuit structure of the gate command waveform generator 13P is used as the first gate command waveform generator 13A, it presents a waveform in which the voltage reduction rate is limited, that is, the second-order differential value of the voltage is greater than zero (d 2 V / dt 2 >0).

[0100] At time t10, based on the turning-off action of the second gate-on command signal Sg2, the second gate command waveform generator 13B turns off the second gate command waveform Vgr2. The second gate command waveform Vgr2 starts to decrease from time t10, but since the circuit structure of the gate command waveform generator 13P is used as the second gate command waveform generator 13B, it presents a waveform in which the voltage reduction rate is limited, that is, the second-order differential value of the voltage is greater than zero (d 2 V / dt 2 >0). In addition, the turn-off operation of the second gate command waveform Vgr2 is delayed by a predetermined time, that is, a time difference of t10-t9, relative to the turn-off operation of the first gate command waveform Vgr1.

[0101] At time t9, the first signal amplifier 14A amplifies the input first gate command waveform Vgr1 and outputs the first gate voltage VgeS. The first gate voltage VgeS reflects the waveform of the first gate command waveform Vgr1 and presents a waveform in which the voltage reduction rate is limited, that is, the second-order differential value of the voltage is greater than zero (d 2V / dt 2 >0).

[0102] At time t10, the second signal amplifier 14B amplifies the input second gate command waveform Vgr2 and outputs the second gate voltage VgeC. The second gate voltage VgeC reflects the waveform of the second gate command waveform Vgr2 and presents a waveform in which the voltage reduction rate is limited, that is, the second-order differential value of the voltage is greater than zero (d 2 V / dt 2 In addition, the turn-off operation of the second gate voltage VgeC is delayed by a predetermined time, that is, a time difference of t10-t9, relative to the turn-off operation of the first gate voltage VgeS and is output.

[0103] The first gate voltage VgeS and the second gate voltage VgeC are respectively output to the first gate terminal Gs and the second gate terminal Gc of the double-gate IGBT 20 provided outside the semiconductor driving device 100 .

[0104] At time t10 when the second gate-on command signal Sg2 starts turning off, the collector current Ic of the dual-gate IGBT 20 decreases from a constant state until then, and becomes zero at time t12 when the second gate voltage VgeC becomes smaller than the threshold voltage Vth.

[0105] At time t9 when the first gate-on command signal Sg1 starts turning off, the collector voltage Vce of the dual-gate IGBT 20 rises from the state of the on-voltage Von until then, and returns to a constant value VB+Vf at time t12 when the second gate voltage VgeC becomes lower than the threshold voltage Vth.

[0106] The above is a series of operations of each signal when the on / off command signal Sgd changes from on to off, that is, when the shutdown operation is performed.

[0107] In the semiconductor driving device 100 according to the first embodiment, Figure 5 As shown, by setting the increase rate of the first gate command waveform Vgr1 and the second gate command waveform Vgr2 during the opening operation to be limited, that is, the second-order differential value of the voltage is less than zero (d 2 V / dt 2 <0), it is possible to suppress an increase in the collector current change rate dIc / dt generated when the second gate terminal Gc serving as the control gate performs an on-operation, and as a result, it is possible to suppress noise during switching operation.

[0108] In addition, in the semiconductor driving device 100 according to the first embodiment, Figure 5As shown, by setting the reduction rate of the first gate command waveform Vgr1 and the second gate command waveform Vgr2 during the shutdown operation to a waveform that limits the second order differential value of the voltage to be greater than zero (d 2 V / dt 2 >0), it is possible to suppress the decrease in the collector current change rate dIc / dt generated when the second gate terminal Gc as the control gate performs a disconnection operation. As a result, it is possible to suppress the surge voltage. In addition, by making the CR time constants of the two gate command waveforms, namely the first gate command waveform Vgr1 and the second gate command waveform Vgr2, the same, the above-mentioned effect of improving robustness is achieved.

[0109] Comparative example.

[0110] Fig.12 This is an example of a constant voltage drive circuit that realizes a constant voltage drive method applied to a semiconductor drive device according to a comparative example. Fig.13 Schematic waveforms are shown when a semiconductor drive device according to a comparative example drives a dual-gate IGBT 20 by providing a short time difference between two gate voltage waveforms. Problems in the semiconductor drive device according to the comparative example will be described below.

[0111] The structure of a semiconductor driving device based on a comparative example is disclosed, for example, in Patent Document 1. In the semiconductor driving device based on the comparative example, when the time difference is set short so that the timing of turning on / off the other gate terminal of the dual-gate IGBT 20 after turning on / off one gate terminal is within the switching operation period in order to obtain the above-mentioned active gate effect, the following two problems arise.

[0112] First, the first problem will be explained. Fig.12 The constant voltage drive circuit shown is from Fig.12 The rectangular wave signal input from the left side of the gate is amplified by a buffer circuit composed of an NPN transistor Q1 and a PNP transistor Q2 via a base resistor R10. In a constant voltage driving method such as the comparative example, the gate current value is limited by gate resistors R11 and R12.

[0113] Fig.13 Schematic waveforms are shown when the semiconductor driving device according to the comparative example is operated by a constant voltage driving method and a short time difference is given to two gate voltage waveforms to drive the dual-gate IGBT 20. Fig.13 In FIG. 1 , the driving waveform of the single-gate IGBT in the comparative example is indicated by a dotted line, and the driving waveform of the dual-gate IGBT 20 in the comparative example is indicated by a solid line.

[0114] In the dual-gate IGBT 20 driven by the semiconductor drive device according to the comparative example, a short time difference (t2-t1) is given to the gate voltages applied to the switch gate Gs that performs the switching operation and the control gate Gc that controls the amount of carrier injection. At time t3 when the switch gate Gs exceeds the threshold voltage Vth, the collector current Ic starts to flow, but the collector current Ic flows into a part of the cells connected to the switch gate Gs. Therefore, in order to obtain the collector current change rate dIc / dt equivalent to that of the single-gate IGBT, it is necessary to apply a larger gate voltage Vge at a larger voltage change rate dVge / dt.

[0115] After the collector current Ic starts to flow in, when the control gate Gc of the dual-gate IGBT 20 reaches the threshold voltage Vth at time t4, current flows through the entire dual-gate IGBT 20, thereby improving the conduction performance, and the effect of the collector voltage Vce becomes rapid, resulting in an effect of reducing switching losses. At the same time, the collector current change rate dIc / dt increases after time t4 due to the improvement of the conduction performance, but it is known that the increase in dIc / dt will cause an increase in noise due to the increase in the cathode-anode voltage change rate dV / dt caused by the recovery action of the relative arm diode constituting the inverter. In addition, it is known that the surge voltage increases during the shutdown action due to the same reason. As described above, the increase in noise and surge voltage when the control gate Gc delayed during the switching action performs the turn-on action is the first problem of the semiconductor drive device based on the comparative example.

[0116] In the driving method of the semiconductor driving device according to the comparative example, in which the control gate Gc is turned on with delay during the switching operation period, a second problem of the semiconductor driving device according to the comparative example occurs, namely, a general problem of active gate driving, i.e., a deterioration in robustness against various conditions such as load current, temperature, and gate threshold voltage deviation. The second problem is caused by the fact that the time difference between the two gate voltages near the Miller voltage level is not constant with respect to the change of the Miller voltage level caused by the above-mentioned various conditions.

[0117] As an obvious example of the second problem, there is a case where the gate resistance of the control gate Gc of the dual-gate IGBT 20 is made smaller than the gate resistance of the switch gate Gs in order to shorten the switching period. In this case, the problem of robustness becomes significant because the voltage level dependence of the time difference between the two gate voltages becomes large.

[0118] <Effects of Implementation Method 1>

[0119] As described above, according to the semiconductor driving device involved in embodiment 1, the above-mentioned problems generated in the comparative example can be eliminated, and the trade-off between the noise and surge voltage generated in the switching action of the multi-gate semiconductor switching element and the switching loss can be improved, thereby achieving the effect of obtaining a semiconductor driving device with excellent robustness.

[0120] Modification 1 of Implementation Example 1.

[0121] Figure 6 1 is a diagram showing an example of a timing diagram of each signal in the semiconductor driving device according to the first modification of the first embodiment. As a specific structure of the gate command waveform generating unit 13 of the semiconductor driving device according to the first modification of the first embodiment, Figure 3D The gate command waveform generating unit 13S shown in FIG. 1 generates a gate command waveform having a ramp shape in a part of the gate command waveform, that is, a second-order differential value of the voltage is zero (d 2 V / dt 2 =0).

[0122] Figure 6 The waveforms shown are, from the upper side, the on-off command signal Sgd, the first gate on-command signal Sg1, the second gate on-command signal Sg2, the first gate command waveform Vgr1 and the second gate command waveform Vgr2, the first gate voltage VgeS, the second gate voltage VgeC, the collector current Ic, and the collector voltage Vce.

[0123] <Operation of Semiconductor Driving Device According to Modification 1 of Implementation Example 1>

[0124] The operation of the semiconductor driving device according to the first modification of the first embodiment will be described below with reference to Figure 6 to explain.

[0125] <Turning On Operation of Semiconductor Drive Device According to Modification 1 of Implementation Example 1>

[0126] First, a series of operations of each signal when the on / off command signal Sgd changes from off to on, that is, during the opening operation, will be described.

[0127] At time t13, the on / off command signal Sgd from the outside changes from off to on. That is, the on / off command signal Sgd changes from the Lo state to the Hi state. At time t13, based on the on action of the on / off command signal Sgd, the timing generation unit 12 outputs the first gate on command signal Sg1. That is, the first gate on command signal Sg1 changes from the Lo state to the Hi state.

[0128] At time t14, based on the on-off command signal Sgd's on-action, the timing generator 12 outputs the second gate on-command signal Sg2. The second gate on-command signal Sg2 is outputted delayed by a preset time, ie, a time difference of t14-t13, relative to the first gate on-command signal Sg1.

[0129] At time t13, the first gate command waveform generator 13A generates the first gate command waveform Vgr1 based on the turn-on operation of the first gate turn-on command signal Sg1. The first gate command waveform Vgr1 starts to rise from time t13, but since the circuit structure of the gate command waveform generator 13S is used as the first gate command waveform generator 13A, a ramp-shaped waveform is generated in a part of the first gate command waveform Vgr1 as if the rate of increase of the voltage is limited, that is, the second-order differential value of the voltage is zero (d 2 V / dt 2 =0).

[0130] At time t14, based on the turn-on action of the second gate turn-on command signal Sg2, the second gate command waveform generator 13B generates the second gate command waveform Vgr2. The second gate command waveform Vgr2 starts to rise from time t14, but since the circuit structure of the gate command waveform generator 13S is applied as the second gate command waveform generator 13B, a ramp-shaped waveform is generated in a part of the second gate command waveform Vgr2 as if the rate of increase of the voltage is limited, that is, the second-order differential value of the voltage is zero (d 2 V / dt 2 =0). In addition, the second gate command waveform Vgr2 is outputted with a delay of a preset time, that is, a time difference of t14-t13, relative to the first gate command waveform Vgr1.

[0131] At time t13, the first signal amplifier 14A amplifies the input first gate command waveform Vgr1 and outputs the first gate voltage VgeS. The first gate voltage VgeS reflects the waveform of the first gate command waveform Vgr1, and a ramp-shaped waveform is generated in a part of the first gate voltage VgeS as if the voltage increase rate is limited, that is, the second-order differential value of the voltage is zero (d 2 V / dt 2 =0).

[0132] At time t14, the second signal amplifier 14B amplifies the input second gate command waveform Vgr2 and outputs the second gate voltage VgeC. The second gate voltage VgeC reflects the waveform of the second gate command waveform Vgr2, and a ramp-shaped waveform is generated in a part of the second gate voltage VgeC as if the voltage increase rate is limited, that is, the second-order differential value of the voltage is zero (d 2 V / dt 2 =0). In addition, the second gate voltage VgeC is outputted with a delay of a predetermined time, that is, a time difference of t14-t13, relative to the first gate voltage VgeS.

[0133] The first gate voltage VgeS and the second gate voltage VgeC are respectively output to the first gate terminal Gs and the second gate terminal Gc of the double-gate IGBT 20 provided outside the semiconductor driving device 100 .

[0134] At time t15 when the first gate voltage VgeS is equal to or higher than the threshold voltage Vth, the collector current Ic of the dual-gate IGBT 20 rises from the zero state before time t15 and becomes a constant value at time t16 when the second gate voltage VgeC is equal to or higher than the threshold voltage Vth.

[0135] At time t15 when the first gate voltage VgeS becomes equal to or higher than the threshold voltage Vth, the collector voltage Vce of the dual-gate IGBT 20 decreases from the state of VB+Vf before time t15, and becomes a constant value of the on-voltage Von at time t16 when the second gate voltage VgeC becomes equal to or higher than the threshold voltage Vth.

[0136] The above is a series of operations of each signal when the on / off command signal Sgd changes from off to on, that is, when the on operation is performed.

[0137] <Shutdown Operation of Semiconductor Drive Device According to Modification 1 of Implementation Example 1>

[0138] Next, a series of operations of each signal when the on / off command signal Sgd changes from on to off, that is, when the shutdown operation is performed, will be described.

[0139] At time t17, the on / off command signal Sgd from the outside changes from on to off. That is, the on / off command signal Sgd changes from the Hi state to the Lo state. At time t17, based on the on / off command signal Sgd being on, the timing generation unit 12 turns off the first gate on command signal Sg1. That is, the first gate on command signal Sg1 changes from the Hi state to the Lo state.

[0140] At time t18, the timing generator 12 turns off the second gate-on command signal Sg2 based on the turning-off action of the on / off command signal Sgd. The turning-off action of the second gate-on command signal Sg2 is delayed by a preset time, that is, a time difference of t18-t17, relative to the turning-off action of the first gate-on command signal Sg1.

[0141] At time t17, the first gate command waveform generator 13A turns off the first gate command waveform Vgr1 based on the turning-off action of the first gate-on command signal Sg1. The first gate command waveform Vgr1 starts to drop from time t17, but since the circuit structure of the gate command waveform generator 13S is used as the first gate command waveform generator 13A, a ramp-shaped waveform is generated in a part of the first gate command waveform Vgr1 as if the voltage reduction rate is limited, that is, the second-order differential value of the voltage is zero (d 2 V / dt 2 =0).

[0142] At time t18, based on the turning-off action of the second gate-on command signal Sg2, the second gate command waveform generator 13B turns off the second gate command waveform Vgr2. The second gate command waveform Vgr2 starts to drop from time t18, but since the circuit structure of the gate command waveform generator 13S is used as the second gate command waveform generator 13B, a ramp-shaped waveform is generated in a part of the second gate command waveform Vgr2 as if the voltage reduction rate is limited, that is, the second-order differential value of the voltage is zero (d 2 V / dt 2 =0). In addition, the OFF operation of the second gate command waveform Vgr2 is delayed by a preset time, that is, a time difference of t18-t17, relative to the OFF operation of the first gate command waveform Vgr1.

[0143] At time t17, the first signal amplifier 14A amplifies the input first gate command waveform Vgr1 and outputs the first gate voltage VgeS. The first gate voltage VgeS reflects the waveform of the first gate command waveform Vgr1, and a ramp-shaped waveform is generated in a part of the first gate voltage VgeS as if the voltage reduction rate is limited, that is, the second-order differential value of the voltage is zero (d 2 V / dt 2 =0).

[0144] At time t18, the second signal amplifier 14B amplifies the input second gate command waveform Vgr2 and outputs the second gate voltage VgeC. The second gate voltage VgeC reflects the waveform of the second gate command waveform Vgr2, and a portion of the second gate voltage VgeC has a ramp shape as a waveform in which the voltage reduction rate is limited, that is, the second-order differential value of the voltage is zero (d 2 V / dt 2 =0). In addition, the second gate voltage VgeC is turned off with a delay of a preset time, that is, a time difference of t18-t17, relative to the first gate voltage VgeS.

[0145] The first gate voltage VgeS and the second gate voltage VgeC are respectively output to the first gate terminal Gs and the second gate terminal Gc of the double-gate IGBT 20 provided outside the semiconductor drive device according to the first modification of the first embodiment.

[0146] At time t19 when the first gate voltage VgeS becomes lower than the threshold voltage Vth, the collector current Ic of the dual-gate IGBT 20 decreases from a constant state until then, and becomes zero at time t20 when the second gate voltage VgeC becomes lower than the threshold voltage Vth.

[0147] At time t19 when the first gate voltage VgeS becomes lower than the threshold voltage Vth, the collector voltage Vce of the dual-gate IGBT 20 rises from the state of the on-voltage Von until then, and returns to the constant value VB+Vf at time t20 when the second gate voltage VgeC becomes lower than the threshold voltage Vth.

[0148] The above is a series of operations of each signal when the on / off command signal Sgd changes from on to off, that is, when the shutdown operation is performed.

[0149] <Effects of Modification 1 of Implementation Example 1>

[0150] As described above, in the semiconductor drive device according to the first modification of the first embodiment, by setting the gate command waveform to have a waveform such as the increase rate of the gate command waveform during the turn-on operation, that is, the second-order differential value of the voltage is zero (d 2 V / dt 2 =0), suppressing the increase of the collector current change rate dIc / dt generated when the control gate Gc is turned on, and as a result, it is possible to suppress the noise during the switching operation. In the semiconductor drive device according to the first modification of the first embodiment, in particular, by making the second-order differential value of the voltage zero (d 2 V / dt 2=0), the time difference between the two gate voltages can be controlled to be independent of the voltage level, so the robustness is optimal. In addition, the same effect is achieved for the turn-off operation, so the description is omitted.

[0151] Modification 2 of Implementation Example 1.

[0152] Figure 7 FIG. 1 is a diagram showing an example of a timing diagram of each signal in a semiconductor driving device according to a second modification of the first embodiment. As a specific configuration of a gate command waveform generating unit of a semiconductor driving device according to the second modification of the first embodiment, Figure 4B The gate command waveform generating unit 13W is shown. The gate command waveform generating unit 13W generates a waveform in which a plateau waveform having a first-order differential value of voltage of zero (dV / dt=0) is provided in a part of a ramp-shaped waveform.

[0153] Right now, Figure 7 The semiconductor driving device according to the second variation of the first embodiment shown in FIG. Figure 6 In the variation 1 of the illustrated embodiment 1, the timing of the rise and fall of the signals in the two gate-on commands, namely the first gate-on command signal Sg1 and the second gate-on command signal Sg2, are made consistent, and a platform period is provided in the middle, i.e., in a part, of the ramp-shaped waveform.

[0154] Figure 7 The waveforms shown are, from the upper side, the on-off command signal Sgd, the first gate on-command signal Sg1, the second gate on-command signal Sg2, the first gate command waveform Vgr1 and the second gate command waveform Vgr2, the first gate voltage VgeS, the second gate voltage VgeC, the collector current Ic, and the collector voltage Vce.

[0155] <Operation of Semiconductor Driving Device According to Modification 2 of Embodiment 1>

[0156] The operation of the semiconductor driving device according to the second modification of the first embodiment will be described below with reference to Figure 7 to explain.

[0157] <Turning On Operation of Semiconductor Drive Device According to Modification 2 of Implementation Example 1>

[0158] First, a series of actions of each signal when the on / off command signal Sgd changes from off to on, i.e., during the opening action, will be described. At time t21, the on / off command signal Sgd from the outside changes from off to on. That is, the on / off command signal Sgd changes from the Lo state to the Hi state. At time t21, based on the on action of the on / off command signal Sgd, the timing generation unit 12 outputs the first gate on command signal Sg1. That is, the first gate on command signal Sg1 changes from the Lo state to the Hi state.

[0159] At time t21, based on the on-operation of the on / off command signal Sgd, the timing generating unit 12 outputs the second gate on-command signal Sg2. The second gate on-command signal Sg2 is output simultaneously with the first gate on-command signal Sg1.

[0160] At time t21, the first gate command waveform generator 13A generates the first gate command waveform Vgr1 based on the turn-on action of the first gate turn-on command signal Sg1. The first gate command waveform Vgr1 starts to rise from time t21, but since the circuit structure of the gate command waveform generator 13S is used as the first gate command waveform generator 13A, the first gate command waveform Vgr1 has a ramp shape as a waveform that limits the rate of voltage reduction after a steeply inclined rising waveform, that is, the second-order differential value of the voltage is zero (d 2 V / dt 2 =0).

[0161] At time t21, based on the turn-on action of the second gate turn-on command signal Sg2, the second gate command waveform generator 13B generates the second gate command waveform Vgr2. The second gate command waveform Vgr2 rises from time t22, but since the circuit structure of the gate command waveform generator 13W is applied as the second gate command waveform generator 13B, a portion of the second gate command waveform Vgr2 presents a waveform in which a platform-type waveform having a first-order differential value of voltage of zero (dV / dt=0) is provided in a portion of a waveform having a ramp-type shape as a waveform in which the rate of increase of the voltage is limited.

[0162] At time t21, the first signal amplifier 14A amplifies the input first gate command waveform Vgr1 and outputs a first gate voltage VgeS. The first gate voltage VgeS reflects the waveform of the first gate command waveform Vgr1 and has a ramp-shaped waveform in which a voltage increase rate is limited in a part of the first gate voltage VgeS.

[0163] At time t23, the second signal amplifier 14B amplifies the input second gate command waveform Vgr2 to output the second gate voltage VgeC. The second gate voltage VgeC reflects the waveform of the second gate command waveform Vgr2, and a portion of the second gate voltage VgeC presents a waveform in which a plateau waveform having a first-order differential value of voltage of zero (dV / dt=0) is provided in a portion of a ramp-shaped waveform as a waveform in which the rate of increase of the voltage is limited.

[0164] The first gate voltage VgeS and the second gate voltage VgeC are respectively output to the first gate terminal Gs and the second gate terminal Gc of the double-gate IGBT 20 provided outside the semiconductor drive device according to the second modification of the first embodiment.

[0165] At time t22 when the first gate voltage VgeS becomes equal to or higher than the threshold voltage Vth, the collector current Ic of the dual-gate IGBT 20 rises from the zero state before time t22 and becomes a constant value at time t23 when the second gate voltage VgeC becomes equal to or higher than the threshold voltage Vth.

[0166] At time t22 when the first gate voltage VgeS becomes equal to or higher than the threshold voltage Vth, the collector voltage Vce of the dual-gate IGBT 20 decreases from the state of VB+Vf until then, and becomes the on-voltage Von which is a constant value after time t23.

[0167] The above is a series of operations of each signal when the on / off command signal Sgd changes from off to on, that is, when the on operation is performed.

[0168] <Shutdown Operation of Semiconductor Drive Device According to Modification 2 of Implementation Example 1>

[0169] Next, a series of operations of each signal when the on / off command signal Sgd changes from on to off, that is, when the shutdown operation is performed, will be described.

[0170] At time t24, the on / off command signal Sgd from the outside changes from on to off. That is, the on / off command signal Sgd changes from the Hi state to the Lo state. At time t24, based on the on / off command signal Sgd being on, the timing generation unit 12 turns off the first gate on command signal Sg1. That is, the first gate on command signal Sg1 changes from the Hi state to the Lo state.

[0171] At time t24 , based on the OFF operation of the ON / OFF command signal Sgd, the timing generating unit 12 turns off the second gate ON command signal Sg2 .

[0172] At time t24, based on the turning-off action of the first gate-on command signal Sg1, the first gate command waveform generator 13A turns off the first gate command waveform Vgr1. The first gate command waveform Vgr1 starts to drop from time t24, but since the circuit structure of the gate command waveform generator 13S is used as the first gate command waveform generator 13A, the first gate command waveform Vgr1 has a ramp shape as a waveform that limits the rate of voltage reduction after a steeply sloped falling waveform, that is, the second-order differential value of the voltage is zero (d 2 V / dt 2 =0).

[0173] At time t24, based on the turning-off action of the second gate-on command signal Sg2, the second gate command waveform generator 13B turns off the second gate command waveform Vgr2. The second gate command waveform Vgr2 starts to drop from time t24, but since the circuit structure of the gate command waveform generator 13W is applied as the second gate command waveform generator 13B, a portion of the second gate command waveform Vgr2 presents a waveform in which a platform period is provided in the middle of the waveform having a ramp shape as a waveform in which the rate of reduction of the voltage is limited, that is, a portion.

[0174] At time t24, the first signal amplifier 14A amplifies the input first gate command waveform Vgr1 and outputs a first gate voltage VgeS. The first gate voltage VgeS reflects the waveform of the first gate command waveform Vgr1, and has a waveform in which a ramp-shaped waveform is provided as a waveform with a limited voltage reduction rate as a part of the first gate voltage VgeS.

[0175] At time t25, the second signal amplifier 14B amplifies the input second gate command waveform Vgr2 to output the second gate voltage VgeC. The second gate voltage VgeC reflects the waveform of the second gate command waveform Vgr2, and a portion of the second gate voltage VgeC presents a waveform in which a plateau period is provided in the middle of a ramp-shaped waveform as a waveform in which the rate of reduction of the voltage is limited, that is, in a portion.

[0176] The first gate voltage VgeS and the second gate voltage VgeC are respectively output to the first gate terminal Gs and the second gate terminal Gc of the double-gate IGBT 20 provided outside the semiconductor drive device according to the first modification of the first embodiment.

[0177] At time t25 when the first gate voltage VgeS becomes lower than the threshold voltage Vth, the collector current Ic of the dual-gate IGBT 20 decreases from a constant state until then, and becomes zero at time t25 when the second gate voltage VgeC becomes lower than the threshold voltage Vth.

[0178] At time t25 when the first gate voltage VgeS becomes lower than the threshold voltage Vth, the collector voltage Vce of the dual-gate IGBT 20 rises from the state of the on-voltage Von until then, and returns to the constant value VB+Vf at time t26 when the second gate voltage VgeC becomes lower than the threshold voltage Vth.

[0179] The above is a series of operations of each signal when the on / off command signal Sgd changes from on to off, that is, when the shutdown operation is performed.

[0180] <Effects of Modification Example 2 of Implementation Example 1>

[0181] As described above, in the semiconductor driving device of the second modification example according to the first embodiment, the conduction performance is increased by making the rising and falling slopes of the first gate-on command signal Sg1 and the second gate-on command signal Sg2 steeper, thereby suppressing the conduction. Figure 7 The ramp waveform shown in FIG. 1 has the effect of passivating the rise and fall of the collector current Ic generated by the time difference drive. On the other hand, as the collector current Ic increases, a platform period is set in a part of the second gate turn-on command signal Sg2 to reduce the conduction performance, thereby suppressing the increase of the time change rate after the rise of the collector current, that is, dIc / dt.

[0182] Implementation method 2.

[0183] <Structure of Semiconductor Driving Device According to Embodiment 2>

[0184] Figure 8 1 is a block diagram showing the structure of a semiconductor drive device 100A according to Embodiment 2. The semiconductor drive device 100A according to Embodiment 2 includes a timing generator 12, a gate command waveform generator 13, a signal amplifier 14, and a drive voltage generator 15. The gate command waveform generator 13 includes a first gate command waveform generator 13C. The signal amplifier 14 further includes a first signal amplifier 14A and a constant voltage driver 16.

[0185] The difference in structure between the semiconductor drive device 100A involved in embodiment 2 and the semiconductor drive device 100 involved in embodiment 1 is that the gate command waveform generating unit 13 of the semiconductor drive device 100 involved in embodiment 1 is composed of a first gate command waveform generating unit 13A and a second gate command waveform generating unit 13B, whereas the gate command waveform generating unit 13 of the semiconductor drive device 100A involved in embodiment 2 is only composed of a first gate command waveform generating unit 13C.

[0186] In the semiconductor driving device 100A according to the second embodiment, in the two gate voltages, namely the first gate voltage VgeS and the second gate command waveform Vgr2, the first gate voltage VgeS is driven to follow the gate command waveform, and the second gate voltage VgeC is driven to a constant voltage. Since the second gate voltage VgeC is driven to a constant voltage, the constant voltage driving unit 16 may also be composed of Fig.12 The constant voltage circuit shown.

[0187] <Effects of Implementation Method 2>

[0188] As described above, according to the semiconductor driving device 100A according to the second embodiment, although the above-mentioned degradation of the robustness becomes significant, there is an effect of improving the effect of the active gate.

[0189] Implementation method 3.

[0190] <Structure of Power Conversion Device According to Embodiment 3>

[0191] Fig. 9 2 is a block diagram showing the structure of the power conversion device 200 according to the third embodiment. Fig. 9 As shown, the power conversion device 200 includes: a power converter 30 having a total of six dual-gate semiconductor switch elements 50a, 50b, 50c, 50d, 50e, and 50f; a smoothing capacitor 40; and any one of the semiconductor drive device 100 according to the first embodiment and the semiconductor drive device 100A according to the second embodiment for driving each of the dual-gate semiconductor switch elements 50a to 50f in the power converter 30. As an example of the power conversion device 200 according to the third embodiment, an inverter device that converts DC power from a DC power supply 60 into AC power and supplies the AC power to an AC motor 70 is exemplified.

[0192] <Effects of Implementation Method 3>

[0193] In the power conversion device 200 involved in embodiment 3, by using the semiconductor drive device 100 involved in the above-mentioned embodiment 1 or the semiconductor drive device 100A involved in embodiment 2 for signal generation for driving the dual-gate semiconductor switch elements 50a to 50f, an inverter device that takes into account both energy saving based on the low loss effect of the dual-gate semiconductor switch elements and low noise such as radiation noise generated in the device can be provided.

[0194] In addition, as an example of the power conversion device 200 involved in embodiment 3, a three-phase inverter device that outputs two levels of positive and negative AC voltage is shown, but it can also be an inverter device capable of multi-level voltage output by connecting any number of dual-gate semiconductor switching elements in series and parallel.

[0195] Implementation method 4.

[0196] Fig.10 2 is a block diagram showing the configuration of a power conversion device 200A according to Embodiment 4. Hereinafter, only differences from the power conversion device 200 according to Embodiment 3 will be briefly described.

[0197] <Structure of Power Conversion Device According to Embodiment 4>

[0198] The power conversion device 200A according to the fourth embodiment includes: a power converter 31 configured to include a plurality of dual-gate semiconductor switch elements 51a and 51b; and any one of the semiconductor drive device 100 according to the first embodiment and the semiconductor drive device 100A according to the second embodiment for driving the dual-gate semiconductor switch elements 51a and 51b in the power converter 31. When the semiconductor drive device 100A according to the second embodiment is applied, the power conversion device 200A operates as a boost converter device that boosts the DC voltage of the DC power supply 60 and supplies the boosted voltage to the DC load 70A.

[0199] The power converter 31 includes a branch circuit formed by connecting dual-gate semiconductor switching elements 51 a and 51 b in series, a smoothing capacitor 41 on the input side, a smoothing capacitor 42 on the output side, and a boost reactor 43 .

[0200] In the power conversion device 200A according to the fourth embodiment, by using either the semiconductor drive device 100 according to the first embodiment or the semiconductor drive device 100A according to the second embodiment, it is possible to provide a boost converter device that achieves both energy saving due to the low loss effect of the dual-gate semiconductor switching element and noise reduction such as radiation noise generated from the inverter. Furthermore, by utilizing the low loss effect to increase the drive frequency of the boost converter device while maintaining the same loss, it is possible to achieve miniaturization of the boost reactor 43.

[0201] Furthermore, although a boost converter device is described as an example of the power conversion device 200A according to the fourth embodiment, the present invention can also be similarly applied to a buck converter device or a boost-buck converter device in which a boost converter device and a buck converter device are combined.

[0202] Implementation method 5.

[0203] <Structure of Power Conversion Device According to Embodiment 5>

[0204] Fig.11 2 is a block diagram showing the structure of a power conversion device 200B according to Embodiment 5. Hereinafter, only the differences from Embodiment 3 will be briefly described. The power conversion device 200B according to Embodiment 5 includes: a power converter 30, Fig. 9 The power conversion device 200 according to the third embodiment shown in the figure; the power converter 31 is connected to the DC side of the power converter 30, forming Fig.10 A power conversion device 200A according to the third embodiment shown in the figure; and any one of the semiconductor drive devices 100 and 100A shown in the first and second embodiments for driving the double-gate semiconductor switching elements 50a to 50f.

[0205] The power conversion device 200B boosts the DC voltage of the DC power supply 60 through the power converter 31, and the boosted DC power is converted into AC power through the power converter 30 and supplied to the AC motor 74. The power conversion device 200B operates as a boost inverter system, for example, applied to electric vehicles. In addition, the power converter 30 in the power conversion device 200B can also be an inverter device capable of multi-level voltage output. In addition, the power converter 31 in the power conversion device 200B is not limited to a boost converter, and can also be applied to a buck converter device, or a buck-boost converter device composed of a boost converter device and a buck converter device.

[0206] The power conversion device 200B according to the fifth embodiment can provide a boost inverter system that achieves both energy saving due to the low loss effect of the dual-gate semiconductor switching element and low noise such as radiation noise generated from the inverter device by using any of the semiconductor drive devices 100 and 100A shown in the first and second embodiments. Furthermore, by utilizing the low loss effect and increasing the drive frequency of the converter under the same loss condition, the boost reactor 43 can be miniaturized.

[0207] In the above-mentioned embodiments 1 to 5, all multi-gate semiconductor switch elements are described by taking a double-gate IGBT as an example. However, as a multi-gate semiconductor switch element, all multi-gate IGBTs such as a triple-gate IGBT can be applied. In addition, it can also be a hybrid element in which a part is replaced with a single-gate IGBT or a single-gate MOSFET structure. In addition, the multi-gate semiconductor switch element can also be any of an RC (Reverse-Conducting)-IGBT and a hybrid element in which an IGBT and a MOSFET are configured in parallel. In addition, the first gate terminal Gs (switch gate) can be composed of multiple components, and the second gate terminal Gc (control gate) can also be composed of multiple components.

[0208] In the configurations of the semiconductor drive devices 100, 100A and the power conversion devices 200, 200A, 200B according to the first to fifth embodiments, a portion of the semiconductor drive devices 100, 100A and the power conversion devices 200, 200A, 200B is described as a functional block. Fig.14 800 is a hardware structure for storing semiconductor drive devices 100, 100A and power conversion devices 200, 200A, 200B. Hardware 800 is composed of a processor 801 and a storage device 802. Although not shown, the storage device 802 includes a volatile storage device such as a random access memory and a non-volatile auxiliary storage device such as a flash memory.

[0209] In addition, an auxiliary storage device such as a hard disk may be provided instead of the flash memory. The processor 801 executes a program input from the storage device 802. In this case, the program is input from the auxiliary storage device to the processor 801 via the volatile storage device. In addition, the processor 801 may output data such as calculation results to the volatile storage device of the storage device 802. Data may also be stored in the auxiliary storage device via the volatile storage device.

[0210] The present disclosure describes various illustrative embodiments and examples, but various features, methods, and functions described in one or more embodiments are not limited to application in specific embodiments and can be applied to the embodiments alone or in various combinations.

[0211] Therefore, numerous modifications not shown in the examples are conceivable within the technical scope disclosed in the present specification, including, for example, the modification, addition or omission of at least one structural element, and the extraction and combination of at least one structural element with structural elements of other embodiments.

[0212] (Explanation of Reference Numerals)

[0213] 12: timing generator; 13, 13P, 13Q, 13R, 13S, 13T, 13U, 13V, 13W: gate command waveform generator; 13A, 13C: first gate command waveform generator; 13B: second gate command waveform generator; 14, 14P, 14Q, 14R, 14S: signal amplifier; 14A: first signal amplifier; 14B: second signal amplifier; 15: drive voltage generator; 16: constant voltage driver; 20: dual gate type IGBT; 21: diode; 25: IGBT module; 30, 31: power converter; 40, 41, 42: smoothing capacitor; 43: boost reactor; 50a, 50b, 50c, 50d, 50e, 50f, 51a, 51b: double-gate semiconductor switch element; 60: DC power supply; 70, 74: AC motor; 70A: load; 100, 100A: semiconductor drive device; 200, 200A, 200B: power converter; 8 00: Hardware; 801: Processor; 802: Storage device; C1, C2, C3, C4: Capacitor; D2: Diode; DS1, DS2, DS3, DS4, DS5, DS6: Constant current diode; DZ1, DZ2, DZ3: Zener diode; Gs: First gate terminal; Gc: Second gate terminal; OP1, OP2: Operational amplifier; Q1, Q3: NPN transistor; Q2, Q4: PNP transistor; R2, R11, R12: Gate Resistors; R3, R4, R5, R6, R7, R8, R9: resistors; R10: base resistor; Sgd: on / off command signal; Sg1: first gate on command signal; Sg2: second gate on command signal; Vce: collector voltage; Vge: gate voltage; VgeS: first gate voltage; VgeC: second gate voltage; Vgr1: first gate command waveform; Vgr2: second gate command waveform; Von: on voltage; Vth: threshold voltage

Claims

1. A semiconductor driving device for driving a multi-gate semiconductor switching element having a plurality of gate terminals, comprising: a timing generating unit for generating gate-on command signals for the plurality of gate terminals respectively based on an on / off command signal from the outside; a gate command waveform generating unit, which generates a first gate command waveform corresponding to at least one first gate terminal of the plurality of gate terminals and a second gate command waveform corresponding to at least one second gate terminal, respectively, based on the gate turn-on command signal, and controls the waveforms of either or both of the first gate command waveform and the second gate command waveform when the multi-gate semiconductor switch element transitions from a non-conducting state to a conducting state and from a conducting state to a non-conducting state; and The signal amplifier receives one or both of the first gate command waveform and the second gate command waveform as input waveforms and amplifies the input waveforms so that the output waveforms follow the input waveforms.

2. The semiconductor driving device according to claim 1, characterized in that: The gate command waveform generating unit controls the waveform by controlling one or both of a differential value of the first gate command waveform and a differential value of the second gate command waveform.

3. The semiconductor driving device according to claim 2, characterized in that: The gate command waveform generating unit controls the multi-gate semiconductor switch element to transition from a non-conducting state to a conducting state so that either or both of the second-order differential value of the first gate command waveform and the second gate command waveform are less than zero.

4. The semiconductor driving device according to claim 2, characterized in that: The gate command waveform generating unit controls the multi-gate semiconductor switch element to transition from a conducting state to a non-conducting state so that either or both of the second order differential value of the first gate command waveform and the second order differential value of the second gate command waveform are greater than zero.

5. The semiconductor driving device according to claim 2, characterized in that: When the multi-gate semiconductor switch element transitions from a non-conducting state to a conducting state, the gate command waveform generating unit performs control in such a manner that one or both of the second-order differential value of the first gate command waveform and the second-order differential value of the second gate command waveform include a portion less than zero and a portion that becomes zero.

6. The semiconductor driving device according to claim 2, characterized in that: The gate command waveform generating unit performs control in such a manner that, when the multi-gate semiconductor switch element transitions from a conducting state to a non-conducting state, one or both of the second-order differential value of the first gate command waveform and the second-order differential value of the second gate command waveform include a portion greater than zero and a portion that becomes zero.

7. The semiconductor driving device according to claim 2, characterized in that: When the multi-gate semiconductor switch element transitions from a non-conducting state to a conducting state, the gate command waveform generating unit performs control in such a manner that either or both of the second-order differential value of the first gate command waveform and the second-order differential value of the second gate command waveform include a portion less than zero and a portion whose first-order differential value is zero.

8. The semiconductor driving device according to claim 2, characterized in that: When the multi-gate semiconductor switch element transitions from a conducting state to a non-conducting state, the gate command waveform generating unit performs control in such a manner that one or both of the second-order differential value of the first gate command waveform and the second-order differential value of the second gate command waveform include a portion greater than zero and a portion whose first-order differential value is zero.

9. The semiconductor driving device according to claim 1, characterized in that: A voltage equal to or higher than a threshold voltage is applied to at least the first gate terminal of the multi-gate semiconductor switch element earlier in time than to other gate terminals including the second gate terminal.

10. The semiconductor driving device according to claim 1, characterized in that: A voltage lower than a threshold voltage is applied to at least the first gate terminal of the multi-gate semiconductor switch element earlier in time than to other gate terminals including the second gate terminal.

11. The semiconductor driving device according to claim 1, characterized in that: The first gate command waveform and the second gate command waveform have the same waveform shape with a preset time difference.

12. The semiconductor driving device according to claim 3 or 4, characterized in that: A portion of at least one gate command waveform includes a charging voltage shape or a discharging voltage shape generated by the electrostatic capacitance and the resistance.

13. The semiconductor driving device according to claim 2, characterized in that: The gate command waveform generating unit controls so that a portion of at least one gate command waveform when the multi-gate semiconductor switch element transitions from a non-conductive state to a conductive state includes a shape in which a first-order differential value of the gate command waveform decreases discontinuously.

14. The semiconductor driving device according to claim 2, characterized in that: The gate command waveform generating unit controls so that a portion of at least one gate command waveform when the multi-gate semiconductor switch element transitions from a conducting state to a non-conducting state includes a shape in which a first-order differential value of the gate command waveform increases discontinuously.

15. The semiconductor driving device according to claim 3 or 4, characterized in that: The signal amplifier includes one or both of a complementary emitter follower circuit and a complementary source follower circuit.

16. The semiconductor driving device according to any one of claims 1 to 15, characterized in that: The gate command waveform generating unit includes at least one operational amplifier.

17. The semiconductor driving device according to any one of claims 1 to 16, characterized in that: The multi-gate semiconductor switch element is any one of a multi-gate IGBT, an RC-IGBT, and a hybrid element in which an IGBT and a MOSFET are arranged in parallel.

18. A power conversion device comprising: any one of an inverter device for converting DC power into AC power, having a multi-gate semiconductor switching element as a semiconductor switching element, a boost converter device for boosting the voltage of DC power, a buck converter device for bucking the voltage of DC power, an AC-DC converter device for converting AC power into DC power, a boost inverter device including the boost converter device and the inverter device, and a buck inverter device including the buck converter device and the inverter device; and The semiconductor driving device according to any one of claims 1 to 17 drives the multi-gate semiconductor switching element.

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