Single event upset reinforced magnetic random access memory read circuit

Abstract

The invention discloses a single event upset reinforced magnetic random access memory reading circuit, and belongs to the field of nonvolatile memories. Interlocked transistors are added on the basis of a traditional 6T reading circuit, meanwhile, a PMOS tube and an NMOS tube are introduced, and errors caused by the single event upset effect can be effectively corrected. The method has the following advantages that single event effect sensitive nodes are considered, zero upset nodes do not exist in the reinforcement method, meanwhile, 1 upset can be rapidly corrected, the single event upset resistance is higher, and the method can be used for reliable storage of data in the space radiation environment.

Description

Technical Field

[0001] The invention relates to the technical field of non-volatile memory, and in particular to a single particle upset reinforced magnetic random access memory reading circuit. Background Art

[0002] Magnetic random access memory stores data by magnetic field. The storage unit is composed of free magnetic layer, tunnel gate layer and fixed magnetic layer. When the magnetic field directions of the free layer and the fixed layer are parallel, the storage unit presents low resistance, otherwise it presents high resistance. By detecting the resistance of the storage unit, it can be determined whether the stored data is "0" or "1".

[0003] Magnetic random access memory has the advantages of unlimited read and write times, fast write speed, low power consumption and good compatibility with traditional processes. Therefore, it is considered by the industry as one of the potential access devices for building the next generation of non-volatile cache and main memory. In addition, because its storage unit has natural radiation resistance, magnetic random access memory has extremely high space application value. However, the peripheral circuits of magnetic random access memory are transistors using traditional processes. These transistors are still affected by high-energy particles such as protons, electrons, and heavy ions in the space radiation environment, resulting in radiation effects, which in turn lead to functional failure.

[0004] At present, the single-particle flip of transistors in the peripheral circuits of magnetic random access memory has always been an important factor restricting its space application. Therefore, a method is urgently needed to solve the single-particle flip of magnetic random access memory and eliminate the above-mentioned influence, which is of great significance for the space application of magnetic random access memory. Summary of the invention

[0005] The object of the present invention is to provide a single-particle upset-hardened magnetic random access memory read circuit to solve the problems in the background technology.

[0006] In order to solve the above technical problems, the present invention provides a single particle upset reinforced magnetic random access memory reading circuit, comprising: a magnetic tunnel junction MTJ1, a magnetic tunnel junction MTJ2, NMOS tubes N1 to N9 and PMOS tubes P1 to P8;

[0007] The source of the PMOS tube P3 is connected to VCC, and the drain is connected to the source of the PMOS tube P7; the drain of the PMOS tube P7 is connected to the drain of the NMOS tube N5; the source of the NMOS tube N5 is grounded;

[0008] The source of the PMOS tube P4 is connected to VCC, and the drain is connected to the source of the PMOS tube P8; the drain of the PMOS tube P8 is connected to the drain of the NMOS tube N6; the source of the NMOS tube N6 is grounded;

[0009] The source of the PMOS tube P1 is connected to VCC, and the drain is connected to the drain of the NMOS tube N1; the source of the NMOS tube N1 is connected to the drain of the NMOS tube N7; the source of the NMOS tube N7 is connected to the fixed magnetic layer of the magnetic tunnel junction MTJ1; the variable magnetic layer of the magnetic tunnel junction MTJ1 is connected to the drain of the NMOS tube N9; the source of the NMOS tube N9 is grounded; the source of the PMOS tube P5 is connected to VCC, and the drain is connected to the drain of the NMOS tube N3; the source of the NMOS tube N3 is connected to the drain of the NMOS tube N7;

[0010] The source of the PMOS tube P6 is connected to VCC, and the drain is connected to the drain of the NMOS tube N4; the source of the NMOS tube N4 is connected to the drain of the NMOS tube N8; the source of the NMOS tube N8 is connected to the fixed magnetic layer of the magnetic tunnel junction MTJ2; the variable magnetic layer of the magnetic tunnel junction MTJ2 is connected to the drain of the NMOS tube N9; the source of the NMOS tube N9 is grounded; the source of the PMOS tube P2 is connected to VCC, and the drain is connected to the drain of the NMOS tube N2; the source of the NMOS tube N2 is connected to the drain of the NMOS tube N8;

[0011] The gate of the PMOS tube P3 is connected to the drain of the PMOS tube P4 and the gate of the NMOS tube N3; the gate of the PMOS tube P7 is connected to the gate of the PMOS tube P5, the gate of the NMOS tube N7, the gate of the NMOS tube N6, and the drain of the NMOS tube N8; the gate of the PMOS tube P1 and the gate of the NMOS tube N9 are connected to the clock signal; the gate of the NMOS tube N1 is connected to the anti-clock signal;

[0012] The gate of PMOS tube P4 is connected to the drain of PMOS tube P3 and the gate of NMOS tube N4; the gate of PMOS tube P8 is connected to the gate of PMOS tube P6, the gate of NMOS tube N8, the gate of NMOS tube N5 and the drain of NMOS tube N7; the gate of PMOS tube P2 is connected to the clock signal; the gate of NMOS tube N2 is connected to the inverse of the clock signal.

[0013] In one embodiment, the growth structure of the magnetic tunnel junctions MTJ1 and MTJ2 is ferromagnetic layer-nonmagnetic insulating layer-ferromagnetic layer, and the method of storing data utilizes the different resistance values ​​when the ferromagnetic layers are parallel and non-parallel.

[0014] In one embodiment, before data is read, under the control of a clock signal, PMOS tube P1, NMOS tube N1, NMOS tube N7, NMOS tube N8, PMOS tube P2 and NMOS tube N2 are turned on, and the drain of NMOS tube N7 and the drain of NMOS tube N8 are charged to VCC at the same time; during discharge, the resistances of magnetic tunnel junctions MTJ1 and MTJ2 are different, and the discharge speeds are inconsistent. Discharging to the "0" potential first will turn on the transistor on the opposite potential, and charging the opposite potential will eventually form a stable state of one "0" and one "1".

[0015] In one implementation, the PMOS tube P7 and the NMOS tube N5, the PMOS tube P1 and the NMOS tube N1, the PMOS tube P5 and the NMOS tube N3, the PMOS tube P6 and the NMOS tube N4, the PMOS tube P2 and the NMOS tube N2, the PMOS tube P8 and the NMOS tube N6 only have two states of being turned on and turned off at the same time when working, and have no effect on the reading and writing functions of the circuit.

[0016] In one embodiment, the characteristic size range of all PMOS tubes and NMOS tubes is 7nm-130μm; due to the symmetry of the circuit design, the magnetic layers of the magnetic tunnel junctions MTJ1 and MTJ2 are also parallel and anti-parallel, respectively.

[0017] The single-particle upset-hardened magnetic random access memory reading circuit provided by the present invention has the following advantages:

[0018] (1) The single-particle upset resistance is increased by adding N and P transistors. The method is simple and compatible with the traditional transistor manufacturing process. The reinforcement method has a sufficient process basis and the reinforcement result is highly reliable.

[0019] (2) The added N and P transistors can prevent the transmission of single-particle pulses, thus completely avoiding the circuit from generating a "0" level flip;

[0020] (3) The reinforcement method can effectively correct the errors caused by the "1" level flip and can be used to improve the single-particle flip reliability of the space magnetic random access memory reading circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of the reinforcement structure of the present invention;

[0022] Figure 2 It is a reinforcement principle analysis diagram of the reinforcement structure of the present invention;

[0023] Figure 3 It is a simulation test result diagram of the reinforcement structure of the present invention. DETAILED DESCRIPTION

[0024] The following is a further detailed description of a single-particle upset-hardened magnetic random access memory read circuit proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0025] The present invention provides a single-particle upset reinforced magnetic random access memory read circuit, which adds interlocked transistors on the basis of the traditional 6T read circuit, and introduces PMOS and NMOS at the same time, which can effectively correct errors caused by single-particle upset effects. The present invention takes single-particle effect sensitive nodes into consideration, and the reinforced design does not have "0" flip nodes, while "1" flips can be quickly corrected, and the single-particle upset resistance is stronger, and can be used for reliable data storage in space radiation environments.

[0026] The single-particle upset reinforced magnetic random access memory reading circuit provided by the present invention is as follows Figure 1 As shown, it includes a magnetic tunnel junction MTJ1, a magnetic tunnel junction MTJ2, NMOS tubes N1 to N9 and PMOS tubes P1 to P8; the specific connection is performed as follows;

[0027] The source of the PMOS tube P3 is connected to VCC, and the drain is connected to the source of the PMOS tube P7; the drain (β) of the PMOS tube P7 is connected to the drain of the NMOS tube N5; and the source of the NMOS tube N5 is grounded.

[0028] The source of the PMOS tube P4 is connected to VCC, and the drain is connected to the source of the PMOS tube P8; the drain (ε) of the PMOS tube P8 is connected to the drain of the NMOS tube N6; and the source of the NMOS tube N6 is grounded.

[0029] The source of the PMOS tube P1 is connected to VCC, and the drain (γ) is connected to the drain of the NMOS tube N1; the source of the NMOS tube N1 is connected to the drain of the NMOS tube N7; the source of the NMOS tube N7 is connected to the fixed magnetic layer of the magnetic tunnel junction MTJ1; the variable magnetic layer of the magnetic tunnel junction MTJ1 is connected to the drain of the NMOS tube N9; the source of the NMOS tube N9 is grounded; the source of the PMOS tube P5 is connected to VCC, and the drain is connected to the drain of the NMOS tube N3; the source of the NMOS tube N3 is connected to the drain of the NMOS tube N7.

[0030] The source of the PMOS tube P6 is connected to VCC, and the drain (δ) is connected to the drain of the NMOS tube N4; the source of the NMOS tube N4 is connected to the drain of the NMOS tube N8; the source of the NMOS tube N8 is connected to the fixed magnetic layer of the magnetic tunnel junction MTJ2; the variable magnetic layer of the magnetic tunnel junction MTJ2 is connected to the drain of the NMOS tube N9; the source of the NMOS tube N9 is grounded; the source of the PMOS tube P2 is connected to VCC, and the drain is connected to the drain of the NMOS tube N2; the source of the NMOS tube N2 is connected to the drain of the NMOS tube N8.

[0031] The gate of the PMOS tube P3 is connected to the drain of the PMOS tube P4 and the gate of the NMOS tube N3; the gate of the PMOS tube P7 is connected to the gate of the PMOS tube P5, the gate of the NMOS tube N7, the gate of the NMOS tube N6, and the drain of the NMOS tube N8 (Qb); the gate of the PMOS tube P1, the gate of the NMOS tube N9 are connected to the clock signal CLK; the gate of the NMOS tube N1 is connected to the inverse of the clock signal.

[0032] The gate of the PMOS tube P4 is connected to the drain of the PMOS tube P3 and the gate of the NMOS tube N4; the gate of the PMOS tube P8 is connected to the gate of the PMOS tube P6, the gate of the NMOS tube N8, the gate of the NMOS tube N5, and the drain of the NMOS tube N7 (Q); the gate of the PMOS tube P2 is connected to the clock signal CLK; the gate of the NMOS tube N2 is connected to the inverse of the clock signal CLK.

[0033] The growth structure of the magnetic tunnel junction MTJ is ferromagnetic layer / non-magnetic insulating layer / ferromagnetic layer, and the method of storing data utilizes the different resistance values ​​when the ferromagnetic layers are parallel and non-parallel.

[0034] Before data is read, under the control of the clock signal CLK, the PMOS tube P1, NMOS tube N1, NMOS tube N7, NMOS tube N8, PMOS tube P2 and NMOS tube N2 are turned on, and the node Q and node Qb are charged to VCC at the same time. During discharge, due to the different resistances of the magnetic tunnel junctions MTJ1 and MTJ2, the discharge speed is inconsistent. Discharging to the "0" potential first will turn on the transistor on the opposite potential, thereby charging the opposite potential and finally forming a stable state of one "0" and one "1".

[0035] The single-particle sensitive nodes of the present invention are the drain of the PMOS tube that is turned off and the source of the NMOS tube that is turned off. The nodes that may generate single-particle pulse currents are the β, γ, δ, ε, Q, Qb, S and Sb nodes. Among them, the PMOS tube P7 and the NMOS tube N5, the PMOS tube P1 and the NMOS tube N1, the PMOS tube P5 and the NMOS tube N3, the PMOS tube P6 and the NMOS tube N4, the PMOS tube P2 and the NMOS tube N2, the PMOS tube P8 and the NMOS tube N6 only have two states of being turned on and turned off at the same time when working, and have no influence on the read-write function of the circuit, that is, β, γ, δ and ε are sensitive nodes with no influence.

[0036] The single particle flip of the Sb and S nodes described in the present invention will not affect the storage value of the storage unit. Taking the ferromagnetic layers of the magnetic tunnel junctions MTJ1 and MTJ2 as antiparallel and parallel, respectively, as an example, the node Q is at a "1" level and the node Qb is at a "0" level. Since the NMOS tube N4 cuts off the transmission of the pulse at the node Qb, the circuit has no "0" flip node.

[0037] The "1" flip described in the present invention takes the magnetic layers of the magnetic tunnel junctions MTJ1 and MTJ2 as antiparallel and parallel, respectively, as an example, the node Q is at the "1" level, and the node Qb is at the "0" level. The "1" flip will turn on the PMOS tube P6, but due to the presence of the NMOS tube N4, the transmission of the pulse current is cut off, and the potential of the node Qb will not be pulled up to the "1" potential by VCC. Due to the presence of the interlocking transistors P5, N7 and P6, N8, the generated single particle flip will recover quickly and will not affect data reading.

[0038] The test of the current structure of the present invention comprises the following steps:

[0039] a. According to Figure 1 The transistor and the MTJ unit are connected in the connection mode, the VCC constant voltage source power supply voltage is set to 1.1V, and the clock signal CLK clock period is set to 10ns, where the high level is 1.1V and the low level is 0V, each for 5ns. The non-periodicity of the clock signal CLK is set to 10ns, where the high and low levels are opposite to the clock.

[0040] b. When PMOS tube P7 and NMOS tube N5, PMOS tube P1 and NMOS tube N1, PMOS tube P5 and NMOS tube N3, PMOS tube P6 and NMOS tube N4, PMOS tube P2 and NMOS tube N2, PMOS tube P8 and NMOS tube N6 are turned off, the pulse of the sensitive node cannot be transmitted, so only Sb, S, Qb ​​and Q need to be simulated. Sensitive node analysis is as follows: Figure 2As shown, the black transistors (P4, P5, P6, P7, N3, N5, N8, N9, MTJ1, MTJ2) are on, the gray transistors (P1, P2, P3, P8, N1, N2, N4, N6, N7) are off, the black line level is "1", the gray level is "0", the magnetic tunnel junction MTJ1 is in an anti-parallel state, and the magnetic tunnel junction MTJ2 is in a parallel state.

[0041] c. For the current pulse simulation of single-particle upset, the following double exponential function is used:

[0042]

[0043] Where Q inj represents the total charge collected at the sensitive node; τ1 represents the collection time constant; τ2 represents the ion track establishment time constant. inj The value of is generally between -2pc and 2pc, with negative and positive values ​​at the sensitive nodes of the N and P transistors, respectively. The typical values ​​of τ1 and τ1 are generally 150ps and 50ps.

[0044] d. Call the double exponential pulse current source in the analogLib library, and set the double exponential pulse current source to introduce negative current pulses at points Q and S at 27.5s, and introduce positive current pulses at points Sb and Qb at 37.5s.

[0045] e. Open the ADE L simulation tool that comes with the software, set the tran simulation time to 50ns, and export the waveforms of CLK, S, Sb, Q, Qb and Qinj. The exported results are as follows: Figure 3 shown.

[0046] f. From the simulation results, the pulse charge injected at the S and Sb points will introduce an instantaneous change in the level, but the level will return to normal within a single pulse time, and the level change of S and Sb will not affect the output Q and Qb of the circuit, that is, it will not change the stored data.

[0047] g. After the negative charge pulse is introduced at Q, the level "1" decreases immediately, but because the NMOS tube N4 is turned off, the CLK high level will not charge Qb, so the Qb point will not flip. Since the PMOS tube P5 and the NMOS tube N3 are turned on and connected to CLK, the flip at Q is quickly restored and the stored data will not be changed. After simulation, the circuit results have the effect of resisting single-particle flip.

[0048] The present invention is applicable to a reading circuit using a magnetic tunnel junction MTJ as a storage unit; the characteristic size range of the transistor used is 7nm-130μm. Due to the symmetry of the circuit design, it is also applicable to the parallel and anti-parallel states of the magnetic layers of MTJ1 and MTJ2 respectively.

[0049] In this example, Cadence Virtuoso software is used to simulate the proposed reinforcement structure. The N and P transistors used are based on a process library with a characteristic length of 40nm, and the MTJ uses an open source model built by the School of Integrated Circuit Science and Engineering of Beihang University.

[0050] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A single event upset hardened magnetic random access memory read circuit, characterized in that: include: Magnetic tunnel junction MTJ1, magnetic tunnel junction MTJ2, NMOS tubes N1 to N9 and PMOS tubes P1 to P8; The source of the PMOS tube P3 is connected to VCC, and the drain is connected to the source of the PMOS tube P7; the drain of the PMOS tube P7 is connected to the drain of the NMOS tube N5; the source of the NMOS tube N5 is grounded; The source of the PMOS tube P4 is connected to VCC, and the drain is connected to the source of the PMOS tube P8; the drain of the PMOS tube P8 is connected to the drain of the NMOS tube N6; the source of the NMOS tube N6 is grounded; The source of the PMOS tube P1 is connected to VCC, and the drain is connected to the drain of the NMOS tube N1; the source of the NMOS tube N1 is connected to the drain of the NMOS tube N7; the source of the NMOS tube N7 is connected to the fixed magnetic layer of the magnetic tunnel junction MTJ1; the variable magnetic layer of the magnetic tunnel junction MTJ1 is connected to the drain of the NMOS tube N9; the source of the NMOS tube N9 is grounded; the source of the PMOS tube P5 is connected to VCC, and the drain is connected to the drain of the NMOS tube N3; the source of the NMOS tube N3 is connected to the drain of the NMOS tube N7; The source of the PMOS tube P6 is connected to VCC, and the drain is connected to the drain of the NMOS tube N4; the source of the NMOS tube N4 is connected to the drain of the NMOS tube N8; the source of the NMOS tube N8 is connected to the fixed magnetic layer of the magnetic tunnel junction MTJ2; the variable magnetic layer of the magnetic tunnel junction MTJ2 is connected to the drain of the NMOS tube N9; the source of the NMOS tube N9 is grounded; the source of the PMOS tube P2 is connected to VCC, and the drain is connected to the drain of the NMOS tube N2; the source of the NMOS tube N2 is connected to the drain of the NMOS tube N8; The gate of the PMOS tube P3 is connected to the drain of the PMOS tube P4 and the gate of the NMOS tube N3; the gate of the PMOS tube P7 is connected to the gate of the PMOS tube P5, the gate of the NMOS tube N7, the gate of the NMOS tube N6, and the drain of the NMOS tube N8; the gate of the PMOS tube P1 and the gate of the NMOS tube N9 are connected to the clock signal; the gate of the NMOS tube N1 is connected to the anti-clock signal; The gate of PMOS tube P4 is connected to the drain of PMOS tube P3 and the gate of NMOS tube N4; the gate of PMOS tube P8 is connected to the gate of PMOS tube P6, the gate of NMOS tube N8, the gate of NMOS tube N5 and the drain of NMOS tube N7; the gate of PMOS tube P2 is connected to the clock signal; the gate of NMOS tube N2 is connected to the inverse of the clock signal.

2. The single event upset hardened magnetic random access memory read circuit according to claim 1, characterized in that: The growth structure of the magnetic tunnel junctions MTJ1 and MTJ2 is ferromagnetic layer-nonmagnetic insulating layer-ferromagnetic layer, and the method of storing data utilizes the different resistance values ​​when the ferromagnetic layers are parallel and non-parallel.

3. The single event upset hardened magnetic random access memory read circuit according to claim 1, characterized in that: Before data is read, under the control of the clock signal, PMOS tube P1, NMOS tube N1, NMOS tube N7, NMOS tube N8, PMOS tube P2 and NMOS tube N2 are turned on, and the drain of NMOS tube N7 and the drain of NMOS tube N8 are charged to VCC at the same time; when discharging, the resistance of magnetic tunnel junctions MTJ1 and MTJ2 is different, and the discharge speed is inconsistent. Discharging to the "0" potential first will turn on the transistor on the opposite potential, and charging the opposite potential will eventually form a stable state of one "0" and one "1".

4. The single event upset hardened magnetic random access memory read circuit according to claim 1, characterized in that: When the PMOS tube P7 and NMOS tube N5, PMOS tube P1 and NMOS tube N1, PMOS tube P5 and NMOS tube N3, PMOS tube P6 and NMOS tube N4, PMOS tube P2 and NMOS tube N2, PMOS tube P8 and NMOS tube N6 are working, there are only two states: simultaneously turned on and turned off, which has no effect on the reading and writing functions of the circuit.

5. The single event upset hardened magnetic random access memory read circuit according to claim 1, characterized in that: The characteristic size range of all PMOS and NMOS tubes is 7nm-130μm; due to the symmetry of the circuit design, the magnetic layers of the magnetic tunnel junctions MTJ1 and MTJ2 are also parallel and anti-parallel respectively.

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