Operation method of memory, memory and memory system

Abstract

The invention provides an operation method of a memory, the memory and a memory system, and relates to the technical field of semiconductor chips. The operation method comprises the following steps: in an erasing stage, applying an erasing voltage to a word line, and applying an erasing voltage to a selection grid line coupled with a target selection tube; in the selection tube programming stage, passing voltage is applied to the word line, and programming voltage is applied to the selection grid line coupled to the target selection tube. According to the invention, the working stability of the bottom selection tube is improved, so that the time for programming the memory is shortened.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a memory operation method, a memory, and a memory system. Background Art

[0002] At present, with the continuous development of three-dimensional flash memory (3D NAND), the density of storage cells is getting higher and higher. In order to improve the performance of the product, manufacturers hope that the programming time is as short as possible during programming. However, the size of complementary metal oxide semiconductor (CMOS) circuit design is also shrinking. The reduction in the area of ​​peripheral circuits limits the driving ability of the array voltage, resulting in an increase in programming time. The programming operation requires gradually increasing the voltage to the target value within a specified time to correctly program the storage cell. If the array voltage does not rise quickly enough, the programming time will increase.

[0003] Therefore, how to reduce the programming time when the density of storage cells is getting higher and higher and the size of CMOS circuit design is getting smaller and smaller is a technical problem that needs to be solved urgently. Summary of the invention

[0004] The embodiments disclosed in the present application provide a memory operation method, a memory and a memory system, aiming to solve the problem of unstable threshold voltage of a selector tube when an electrical isolation solution is adopted.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] In a first aspect, a method for operating a memory is provided, wherein the memory includes a plurality of memory strings, the memory strings include a plurality of memory cells and a plurality of selection tubes, the memory cells are coupled to word lines, and the selection tubes are coupled to selection gate lines, and the method includes: in an erasing phase, applying an erasing voltage to the word lines, and applying an erasing voltage to the selection gate lines coupled to target selection tubes among the plurality of selection tubes; in a selection tube programming phase, applying a pass voltage to the word lines, and applying a programming voltage to the selection gate lines coupled to the target selection tubes.

[0007] The memory operation method provided by the present disclosure erases and programs the selection tube at the same time during the erasing process of the storage unit, so as to recalibrate the threshold voltage of the selection tube with failure risk, and the failure risk refers to the drift of the threshold voltage of the selection tube. By resetting the state of the selection tube, its potential failure problem is eliminated, and the threshold voltage is recalibrated to the expected range, thereby improving the reliability and stability of the selection tube, thereby ensuring the normal realization of the function of electrical isolation.

[0008] In some embodiments, after the erasing phase and before the selecting tube programming phase, an erasing verification phase is also included, and the method further includes: in the erasing verification phase, applying a first verification voltage to a selecting gate line coupled to the target selecting tube.

[0009] The memory operation method provided by the present disclosure can ensure that all bottom selection tubes are in the same state after erasing by verifying the erasing operation, thereby making it more convenient to subsequently recalibrate the threshold voltage of the selection tube to an expected range.

[0010] In some embodiments, the selection tube includes a top selection tube and a bottom selection tube, the target selection tube is the bottom selection tube, and the method further includes: in the selection tube programming stage, applying a programming selection voltage to the top selection tube of the storage string where the target selection tube is located, and applying a programming prohibition voltage to the top selection tubes of other storage strings.

[0011] The memory operation method provided by the present disclosure applies different voltages to different top selection tubes, so that different bottom selection tubes can be programmed to their respective corresponding target threshold voltages.

[0012] In some embodiments, after the selection tube programming stage, a selection tube programming verification stage is also included, and the method also includes: in the selection tube programming verification stage, applying a second verification voltage to the selection gate line coupled to the target selection tube; when the threshold voltage of the target selection tube does not reach the target threshold voltage, increasing the programming voltage.

[0013] In some embodiments, the method further comprises:

[0014] In the selection tube programming verification stage, a programming selection voltage is applied to the top selection tube of the storage string where the target selection tube is located, and a pass voltage is applied to the top selection tubes of other storage strings.

[0015] The memory operation method provided by the present disclosure performs different voltage operations on the top selection tubes of different memory strings, thereby ensuring that only the memory string where the target bottom selection tube is located will be programmed and verified, thereby avoiding other memory strings from being misoperated.

[0016] In some embodiments, the method further comprises: applying a pass voltage to the word line during the selection tube programming verification stage. In some embodiments, the method further comprises: applying a hold voltage to the top selection tube during the erase stage. In some embodiments, before the erase stage, a pre-programming stage is included, and the method further comprises: applying a pre-programming voltage or a pass voltage to the word line, and applying a pre-programming voltage to the selection gate line coupled to the target selection tube during the pre-programming stage.

[0017] The memory operation method provided by the present disclosure performs a pre-programming operation on the selection tubes to ensure that the selection tubes have the same threshold voltage after being erased, that is, the selection tubes have better consistency.

[0018] In a second aspect, a memory is provided, comprising: a memory cell array and a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit is configured to: in an erase phase, apply an erase voltage to a word line, and apply an erase voltage to a selection gate line coupled to a target selection tube; in a selection tube programming phase, apply a pass voltage to the word line, and apply a programming voltage to the selection gate line coupled to the target selection tube.

[0019] In some embodiments, after the erase phase and before the select tube programming phase, an erase verification phase is also included, and the peripheral circuit is further configured to: in the erase verification phase, apply a first verification voltage to the select gate line coupled to the target select tube.

[0020] In some embodiments, the selection tube includes a top selection tube and a bottom selection tube, the target selection tube is the bottom selection tube, and the peripheral circuit is further configured to: in the selection tube programming stage, apply a programming selection voltage to the top selection tube of the storage string where the target selection tube is located, and apply a programming prohibition voltage to the top selection tubes of other storage strings.

[0021] In some embodiments, after the selection tube programming stage, a selection tube programming verification stage is also included, and the peripheral circuit is further configured to: in the selection tube programming verification stage, apply a second verification voltage to the selection gate line coupled to the target selection tube; when the threshold voltage of the target selection tube does not reach the target threshold voltage, increase the programming voltage.

[0022] In some embodiments, the selection tube also includes a top selection tube, and the peripheral circuit is further configured to: in the selection tube programming verification stage, apply a programming selection voltage to the top selection tube of the storage string where the target selection tube is located, and apply a pass voltage to the top selection tubes of other storage strings.

[0023] In some embodiments, the peripheral circuit is further configured to: apply a pass voltage to the word line during a selection tube programming verification phase.

[0024] In some embodiments, the peripheral circuit is further configured to: apply a holding voltage to the top selection transistor during the erase phase.

[0025] In some embodiments, before the erase phase, a pre-programming phase is also included, and the peripheral circuit is further configured to: in the pre-programming phase, apply a pre-programming voltage to the word line or pass voltage to apply a pre-programming voltage to the selection gate line coupled to the target selection tube.

[0026] According to a third aspect, a memory system is provided. The memory system comprises a memory controller and the memory according to the first aspect, wherein the memory controller is configured to control the memory.

[0027] In a fourth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer-executable instructions; after the computer-executable instructions are executed, any one of the methods in the second aspect above can be implemented.

[0028] In a fifth aspect, a computer device is provided, comprising a processor and a readable storage medium coupled to the processor, wherein the readable storage medium stores executable instructions, and when the executable instructions are executed by the processor, any one of the methods in the second aspect can be implemented.

[0029] It can be understood that the technical effects of the second to fifth aspects refer to the technical effects of the first aspect and any embodiment thereof, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a block diagram of an electronic device according to some embodiments of the present disclosure;

[0031] Figure 2 is a block diagram of a storage system according to some embodiments of the present disclosure;

[0032] Figure 3 is a block diagram of another storage system according to some embodiments of the present disclosure;

[0033] Figure 4 is a schematic diagram of a floating gate field effect transistor according to some embodiments of the present disclosure;

[0034] Figure 5 A schematic diagram of storing data of a floating gate field effect transistor according to some embodiments of the present disclosure;

[0035] Figure 6 A schematic diagram of the connection structure of a storage cell array provided in an embodiment of the present disclosure;

[0036] Figure 7 A schematic diagram of a planar structure of a memory provided in an embodiment of the present disclosure;

[0037] Figure 8 Another schematic diagram of a memory provided by an embodiment of the present disclosure;

[0038] Fig. 9 A schematic diagram of a process of selectively shutting down a bottom selection tube provided in an embodiment of the present disclosure;

[0039] Fig.10 A schematic diagram of a possible voltage waveform for erasing a memory provided in an embodiment of the present disclosure;

[0040] Fig.11 A schematic diagram of another process of selectively shutting down the bottom selection tube provided in an embodiment of the present disclosure;

[0041] Fig.12 A schematic diagram of the structure of a memory and peripheral circuits provided in an embodiment of the present disclosure;

[0042] Fig.13 A schematic diagram of a flow chart of a method for operating a memory provided by an embodiment of the present disclosure;

[0043] Fig.14 A schematic diagram of another possible voltage waveform for erasing a memory provided by an embodiment of the present disclosure;

[0044] Fig.15 A flowchart of another method for operating a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0046] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0047] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0048] When describing some embodiments, the term "coupled" and its derivative expressions may be used. For example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. In this case, "coupled" may also be described as "connected". In addition, the term "coupled" may also refer to two or more components that are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0049] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0050] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B. The use of "suitable for" or "configured to" herein is meant to be open and inclusive language, which does not exclude devices that are suitable for or configured to perform additional tasks or steps. In addition, the use of "based on" is meant to be open and inclusive, because a process, step, calculation or other action "based on" one or more conditions or values ​​can be based on additional conditions or beyond values ​​in practice.

[0051] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0052] The embodiments of the present disclosure provide an electronic device, which may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc. Figure 1 , Figure 1 A schematic diagram of an electronic device 10 provided by an embodiment of the present disclosure is shown, including a host 100 and a storage system 110. The host 100 is coupled to the storage system 110 to write data to the storage system 110 or read data stored in the storage system 110. The host is also called a master device, and the storage system is also called a slave device. In an electronic device, a slave device can be accessed by different master devices. For example, taking the electronic device as a mobile phone as an example, the central processing unit (CPU) and digital signal processor (DSP) of the mobile phone can all access the storage system as a host.

[0053] For example, see Figure 2 , Figure 2A schematic diagram of a storage system 110 provided in an embodiment of the present disclosure is shown, the storage system 110 includes a storage controller 111 and a memory 112, the storage controller 111 is coupled to the memory 112 to control the memory 112 to store data. The memory 112 may be a two-dimensional (2-dimension, 2D) memory or a three-dimensional (3-dimension, 3D) memory.

[0054] The storage system 110 may be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an embedded multimedia card (eMMC) package). That is, the storage system 110 may be applied to and packaged into different types of electronic products, for example, mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0055] In some embodiments, the storage system 110 includes a storage controller 111 and a memory 112, and the storage system 110 can be integrated into a memory card. The memory card includes any one of a personal computer memory card international association (PCMCIA) card (abbreviated as PC card), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC), a secure digital memory card (SD) card, and a UFS.

[0056] In other embodiments, see Figure 3 The storage system 110 includes a storage controller 111 and a plurality of memories 112 , and the storage system 110 is integrated into solid state drives (SSDs).

[0057] In the storage system 110, in some embodiments, the storage controller 111 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0058] In other embodiments, the storage controller 111 is configured to operate in a high duty cycle environment SSD or eMMC, which is used for data storage in mobile devices such as smartphones, tablets, laptops, and enterprise storage arrays.

[0059] In some embodiments, the storage controller 111 may be configured to manage data stored in the memory 112 and communicate with an external device (e.g., the host 100). In some embodiments, the storage controller 111 may also be configured to control operations of the memory 112, such as read, erase, and program operations. In some embodiments, the storage controller 111 may also be configured to manage various functions regarding data stored or to be stored in the memory 112, including at least one of bad block management, garbage collection (GC), logical to physical address conversion, and wear leveling. In some embodiments, the storage controller 111 is also configured to process error correction codes regarding data read from or written to the memory 112.

[0060] In addition, the storage controller 111 can communicate with an external device (e.g., the host 100) through at least one of various interface protocols. It should be noted that the interface protocol includes at least one of a universal serial bus (USB) protocol, a Microsoft Management Console (MMC) protocol, a peripheral component interconnect (Peripheral Component Interconnect), a PCI protocol, a PCI Express (Peripheral Component Interconnect Express, PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, and a FireWire protocol.

[0061] Exemplarily, taking the storage medium of the memory 112 as a flash memory, the basic storage unit of the flash memory includes a floating gate field effect transistor or a charge trapping transistor, etc. The embodiment of the present disclosure takes the charge trapping transistor as an example for introduction.

[0062] See also Figure 4 , Figure 4 The schematic diagram of the structure of the charge trapping transistor is shown, including a control gate 211, a charge trapping layer 212, a source 213, a drain 214, a substrate 215, an oxide layer 216 and a tunnel oxide layer 217. The source 213 and the drain 214 are arranged on the substrate 215. The embodiment of the present disclosure takes an N-channel charge trapping layer field effect transistor as an example, the substrate 215 is a P-type semiconductor material, and the source 213 and the drain 214 are N-type semiconductor materials. The substrate material between the source 213 and the drain 214 can form a conductive channel 218, the charge capture layer 212 covers the conductive channel 218, the tunnel oxide layer 217 is located between the charge capture layer 212 and the conductive channel 218, and the charge capture layer 212 is separated from the source 213, the drain 214 and the conductive channel 218. The control gate 211 is arranged on the charge capture layer 212, and an oxide layer 216 is arranged between the control gate 211 and the charge capture layer 212 to separate the control gate 211 from the charge capture layer 212. The oxide layer 216 and the tunnel oxide layer 217 are both made of insulating materials, such as silicon dioxide (SiO2).

[0063] The charge capture layer 212 is made of an insulating material with a high charge capture density. When writing data, the charge capture layer 212 captures electrons, and the threshold voltage of the field effect transistor changes. Data is stored with such characteristics. When erasing data, holes in the channel are injected into the charge capture layer 212 and neutralized with the electrons in the charge capture layer 212 to achieve erasure.

[0064] When the charge trapping layer captures electrons, a higher threshold voltage is required to open the conductive channel due to the shielding effect of the electrons. If the threshold voltage when there are no electrons captured in the charge trapping layer is recorded as V th1 , the threshold voltage when electrons are captured in the charge trapping layer is recorded as V th2 , then assuming that a larger than V th1 And less than V th2A voltage is applied to try to turn on the charge capture transistor. If the charge capture field effect transistor is turned on, it can be determined that no electrons are captured in the charge capture layer. If the charge capture transistor is not turned on, it can be determined that electrons are captured in the charge capture layer. Based on this logic, when no electrons are captured on the charge capture layer, the charge capture transistor is in the on state, indicating 1. When electrons are captured on the charge capture layer, the charge capture transistor is in the off state, indicating 0. Therefore, such different states can be used to store data, and the storage function is achieved by injecting or capturing electrons in the charge capture layer to change the threshold voltage of the charge capture transistor.

[0065] When a voltage is applied to the control gate, a tunneling effect occurs based on the potential difference between the control gate and the channel, and electrons can be injected into the charge trapping layer or captured by the charge trapping layer. When storing data, the data is stored in the charge trapping layer, and the presence or absence of charge in the charge trapping layer can be used to indicate the data currently stored in the storage unit. For example, see Figure 5 ,like Figure 5 As shown in a, the state of the charge trapping layer with charge is 0, such as Figure 5 As shown in b, the state where the charge trapping layer has no charge is 1.

[0066] In order to continuously improve the density and capacity of memory, many memory designers and manufacturers have changed the traditional 2D integration mode and adopted three-dimensional stacking technology to improve the storage density of NAND flash memory. In this context, manufacturers hope to achieve shorter programming time during programming, because this brings many advantages. First of all, shorter programming time can significantly speed up the reading and writing of data. Programming is the process of writing to a single storage unit in the memory, and using a shorter programming time can quickly complete these operations, improve the response speed of the memory and the efficiency of data transmission, thereby improving the overall performance of the system.

[0067] Secondly, shorter programming time is crucial to improving the performance of memory devices. In 3D NAND memory, memory cells are stacked on multiple levels, which greatly improves the storage density. However, the long programming process may cause mutual interference and cross-interference between memory cells, thus affecting the stability of the memory and data reliability. By shortening the programming time, the possibility of such interference can be reduced, the stability of the memory can be improved, and problems such as data loss and miswrite can be avoided, thereby enhancing the performance and reliability of the memory device.

[0068] Finally, shorter programming time helps reduce the chance of electron migration, thereby extending the life of the memory. In the memory, long programming operations may cause electron migration in small structures, causing data loss and bit flipping, which in turn reduces the life of the flash memory chip. By shortening the programming time, the loss caused by electron migration can be reduced, the life of the memory can be extended, and thus the durability and reliability of the memory can be improved.

[0069] Therefore, how to reduce programming time under the condition of increasing storage density is a key concern of the industry. One possible way to achieve this is to improve programming time by reducing the impact of the parasitic RC (Resistor-Capacitor) effect of the non-programmed storage string on the programmed storage string. The RC effect is a non-ideal effect that is prevalent in integrated circuits and refers to the effect of mutual coupling between resistors and capacitors. This effect can cause delays in circuit signal transmission and response, thereby affecting the performance of the entire circuit.

[0070] For example, during programming, the parasitic RC effect of the non-programmed memory string will affect the programmed memory string, thereby affecting the programming time of the programmed memory string. Therefore, by reducing the RC effect, the signal transmission delay can be reduced, thereby improving the programming time.

[0071] In some embodiments, by programming the bottom selection tubes to different threshold voltages and applying different voltages to multiple bottom selection gate lines to achieve selective conduction of the bottom selection tubes, the effect of electrical isolation is achieved, thereby achieving the effect of improving programming time. That is, the parasitic RC effect of the non-programmed storage string will not affect the programmed storage string.

[0072] See also Figure 6 , shows a schematic diagram of the structure of the memory cell array provided by the present disclosure, the memory cell array 300 includes a plurality of memory cell strings 310. Each memory cell string is coupled to the peripheral circuit through a top select gate line (String select line, SSL), a word line (word line, WL), a bit line (bit line, BL), a bottom select gate line (ground select line, GSL), a source line (Source line, SL), etc. The memory cell string 310 includes a top select gate (top select gate, TSG), a plurality of memory cells and a bottom select gate (bottom select gate, BSG). For the bottom select gates located in different memory strings, the same bottom select gate line is connected.

[0073] As an example, the first bottom selection tubes of the plurality of memory strings are all connected to the first bottom selection gate line GSL1 , and the second bottom selection tubes of the plurality of memory strings are all connected to the second bottom selection gate line GSL2 .

[0074] For example, see Figure 7 The memory includes a top selection tube layer 301, a word line 302 connected to the memory cell and a bottom selection tube layer 303, a first bottom selection gate line GSL1 is connected to the driving circuit CMOS Driver 1, and a second bottom selection gate line GSL2 is connected to the driving circuit CMOS Driver 2.

[0075] See also Figure 8 , the principle of realizing electrical isolation of the embodiments of the present disclosure will be described, taking the storage string Str1 as the first storage string and the storage string Str2 as the second storage string as an example, the storage string Str1 and the storage string Str2 both include a first bottom selection tube and a second bottom selection tube.

[0076] As an example, the first bottom selection tube is close to one side of the storage unit, then the first bottom selection tubes on the storage string Str1 and the storage string Str2 are both connected to the first bottom selection gate line GSL1, the second bottom selection tubes on the storage string Str1 and the storage string Str2 are both connected to the second bottom selection gate line GSL2, the first bottom selection tube layer a1 includes all the first bottom selection tubes connected by the first bottom selection gate line GSL1, and the second bottom selection tube layer b1 includes all the second bottom selection tubes connected by the second bottom selection gate line GSL2.

[0077] In a possible embodiment, the threshold voltage of the corresponding bottom selection tube is shown in FIG. Fig. 9 As shown, the threshold voltage of the first bottom selection transistor close to the storage unit on the storage string Str1 is the first threshold voltage V a , the threshold voltage of the second bottom selection transistor close to the source terminal ACS on the storage string Str1 is the second threshold voltage V b , the threshold voltage of the first bottom selection tube close to the storage unit on the storage string Str2 is the second threshold voltage V b , the threshold voltage of the second bottom selection transistor close to the source terminal ACS on the storage string Str2 is the first threshold voltage V a .

[0078] It should be noted that the first threshold voltage V a Greater than the second threshold voltage V bThe threshold voltage of the bottom selection tube close to the storage cell on the storage string Str1 can be within the same threshold voltage range as the threshold voltage of the bottom selection tube close to the source terminal ACS on the storage string Str2. The threshold voltage of the bottom selection tube close to the source terminal ACS on the storage string Str1 can be within the same threshold voltage range as the threshold voltage of the bottom selection tube close to the source terminal ACS on the storage string Str2. It should be noted that it is difficult to achieve the same threshold voltage for any two bottom selection tubes. Therefore, if any two bottom selection tubes are within the same threshold voltage range, it can be considered that the two bottom selection tubes have the same threshold voltage.

[0079] The following will further combine Fig. 9 The content shown illustrates the case where the storage string Str1 and the storage string Str2 are selectively shut down.

[0080] For the convenience of subsequent description, the naming method of the bottom selection tube is explained, and the bottom selection tube is named according to the bottom selection gate line position and the storage string position where the bottom selection tube is located. If the bottom selection tube is located on Str1 and the first bottom selection gate line GSL1, the bottom selection tube is marked as G1Str1, and similarly, if the bottom selection tube is located on Str2 and the first bottom selection gate line GSL2, the bottom selection tube is marked as G2Str2.

[0081] As an example, the threshold voltages of the first bottom selection tube G1Str1 on the storage string Str1 and the second bottom selection tube G2Str2 on the storage string Str2 are both V a The threshold voltages of the second bottom selection tube G2Str1 on the storage string Str1 and the first bottom selection tube G1Str2 on the storage string Str2 are both V b In the process of programming and verifying the memory cells on the memory string Str1, when the memory string Str2 is selectively turned off, a first voltage V is applied to the first bottom selection gate line GSL1. A , applying a second voltage V to the second bottom selection gate line GSL2 B , the first voltage V A Greater than the second voltage V B , the first voltage V A Greater than the threshold voltage V a , the second voltage V B Greater than the threshold voltage V b , and the second voltage V B Less than the threshold voltage V a .

[0082] When the memory string Str1 is turned on and the memory string Str2 is selected to be turned off, a first voltage V is applied to the first bottom selection gate line. AWhen the first voltage V A Greater than the threshold voltage V of the first bottom selection tube G1Str1 on the storage string Str1 a and the threshold voltage V of the first bottom selection tube G1Str2 on the storage string Str2 b , so the first bottom selection tubes on the storage string Str1 and the storage string Str2 are both turned on.

[0083] When the second voltage V is applied to the second bottom selection gate line GSL2 B When the second voltage V B Greater than the threshold voltage V of the second bottom selection tube G2Str1 on the storage string Str1 b , so the second bottom selection tube G2Str1 on the storage string Str1 is turned on, and due to the second voltage V B Less than the threshold voltage V of the second bottom selection tube G2Str2 on the storage string Str2 a , so the second bottom selection tube G2Str2 on the storage string Str2 is turned off.

[0084] Based on the above operation process, the first bottom selection tube G1Str1 and the second bottom selection tube G2Str1 on the storage string Str1 are both turned on, so the storage string Str1 is turned on, and the first bottom selection tube G1Str2 on the storage string Str2 is turned on, and the second bottom selection tube G2Str2 is turned off, so the storage string Str2 is selected to be turned off.

[0085] When the memory string Str2 is turned on and the memory string Str1 is selected to be turned off, a second voltage V is applied to the first bottom selection gate line GSL1. B , since the second voltage V B Less than the threshold voltage V of the first bottom selection tube G1Str1 on the storage string Str1 a , so the first bottom selection tube G1Str1 on the storage string Str1 is turned off, and due to the second voltage V B Greater than the threshold voltage V of the first bottom selection tube G1Str2 on the storage string Str2 b , so the first bottom selection tube G1Str2 on the storage string Str2 is turned on.

[0086] When the first voltage V is applied to the second bottom selection gate line GSL2 A When the first voltage V A Greater than the threshold voltage V of the second bottom selection tube G2Str1 on the storage string Str1 b and the threshold voltage V of the second bottom selection tube G2Str2 on the storage string Str2 a, so the second bottom selection tubes on the storage string Str1 and the storage string Str2 are turned on, that is, G2Str1 and G2Str2 are turned on.

[0087] Based on the above operation process, the first bottom selection tube G2Str1 and the second bottom selection tube G2Str2 on the storage string Str2 are both turned on, so the bottom selection tube on the storage string Str2 is turned on, while the first bottom selection tube G1Str1 on the storage string Str1 is turned off, and the second bottom selection tube G1Str2 is turned on, so the bottom selection tube of the storage string Str1 is selected to be turned off.

[0088] The solution provided by the embodiments of the present disclosure sets different threshold voltages for different bottom selection tubes in different bottom selection tube layers, thereby achieving selective shutoff of the selection tubes during programming verification of the storage cells. After the selection tubes are selectively shut off, the programming storage string will be turned on and the non-programming storage string will be turned off, thereby achieving the influence of the parasitic RC effect of the non-programming storage string on the programming storage string, thereby achieving the effect of reducing the programming time.

[0089] However, during the process of cyclically executing the above-mentioned erase-program operation, the threshold voltage of the bottom selection tube will drift, and in the stages of erasing, verifying or programming the storage unit, for example, in combination with Fig.10 , usually a voltage is applied (hold / release) or passed through the selection tube, that is, during these processes, the bottom selection tube is not programmed, and the threshold voltage drift of the bottom selection tube may cause the electrical isolation function to fail.

[0090] For example, see Fig.11 For the first bottom selection tube G1Str1, its target threshold voltage is V a , and after completing an erase-program operation, its threshold voltage may drift, for example, in one possible implementation, the threshold voltage drifts to V n , and V n >V A >V a .

[0091] When the storage string Str1 needs to be turned on and the storage string Str2 is selected to be turned off, a first voltage V is applied to the first bottom selection gate line. A When the first voltage V A Less than the threshold voltage V of the first bottom selection tube G1Str1 on the storage string Str1 n， Therefore, the first bottom selection tube on the storage string Str1 is turned off, because the first voltage V A Greater than the threshold voltage V of the first bottom selection tube G1Str2 on the storage string Str2 b, so the first bottom selection tube on the storage string Str2 is turned on.

[0092] When the second voltage V is applied to the second bottom selection gate line GSL2 B When the second voltage V B Greater than the threshold voltage V of the second bottom selection tube G2Str1 on the storage string Str1 b , so the second bottom selection tube G2Str1 on the storage string Str1 is turned on, and due to the second voltage V B Less than the threshold voltage V of the second bottom selection tube G2Str2 on the storage string Str2 a , so the second bottom selection tube G2Str2 on the storage string Str2 is turned off.

[0093] Based on the above operation process, the first bottom selection tube G1Str1 on the storage string Str1 is turned off, and the second bottom selection tube G2Str1 is turned on, so the storage string Str1 is selected to be turned off, and the first bottom selection tube G1Str2 on the storage string Str2 is turned on, and the second bottom selection tube G2Str2 is turned off, so the storage string Str2 is selected to be turned off. Therefore, both the storage string Str1 and the storage string Str2 are turned off, and the function of electrical isolation fails.

[0094] It can be seen that in a solution that uses electrical isolation but does not reprogram the bottom selection tube, the threshold voltage drift of the bottom selection tube may cause the electrical isolation to fail, affecting the read and write performance of the memory.

[0095] Based on this, an embodiment of the present disclosure provides a solution: erasing the bottom selection tube while erasing the storage cell, and after completing the erasing of the bottom selection tube, reprogramming the bottom selection tube to adjust its threshold voltage to the target threshold voltage to avoid electrical isolation failure.

[0096] Fig.12 A schematic diagram of the structure of a memory array and peripheral circuits is shown. Fig.12 In the embodiment, the peripheral circuit 400 includes an I / O interface 410, a control logic circuit 420, a row decoder 430, a voltage generator 440, a column decoder 450, a page buffer 460, a data bus 470, and a register 480. It should be understood that in some examples, the peripheral circuit 400 may also include Fig.12 Additional circuitry not shown.

[0097] I / O interface 410 may be coupled to control logic circuit 420 and act as a control buffer to buffer data from a storage controller (eg, Figure 2The I / O interface 410 may receive control commands received from the memory controller 111 in the memory cell array 300 and relay them to the control logic circuit 420, and buffer status information received from the control logic circuit 420 and relay them to the host. The I / O interface 410 may also be coupled to the page buffer 460 via the data bus 470, and act as a data I / O interface 410 and a data buffer to buffer data and relay them to or from the memory cell array 300.

[0098] The control logic circuit 420 may be coupled to the voltage generator 440, the page buffer 460, the column decoder 450, the row decoder 430, the I / O interface 410, etc., and is configured to control the operation of each peripheral circuit. The control logic circuit 420 may generate an operation signal to control the operation of the row decoder 430, the column decoder 450, the page buffer 460, and the voltage generator 440 in response to a command (CMD) or a control signal from the memory controller 111; wherein the command may be a program command, a read command, etc.

[0099] The row decoder 430 may supply the word line voltage generated from the voltage generator 440 to the selected word lines and the unselected word lines of the memory cell array 300 in response to the control of the control logic circuit 420. As described in detail below, the row decoder 430 is configured to perform a program operation on the memory cells coupled to one or more selected word lines in the memory cell array 300.

[0100] The voltage generator 440 may generate various voltages for performing operations such as erasing, programming, reading, and verifying on the memory cell array 300 using an external power supply voltage or an internal power supply voltage.

[0101] The column decoder 450 may be controlled in response to the control logic circuit 420 , and select one or more memory cell strings 310 in the memory cell array 300 by applying a bit line voltage generated from the voltage generator 440 .

[0102] The page buffer 460 can read data from the memory cell array 300 and program (write) data to the memory cell array 300 according to the control signal from the control logic circuit 420. In one example, the page buffer 460 can store the programming data (write data) to be programmed into the memory cell array 300. In another example, the page buffer 460 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, the page buffer 460 can also detect a low-power signal from a bit line representing a data bit stored in the memory cell, and amplify a small voltage swing to a recognizable logic level in a read operation.

[0103] The register 480 may be coupled to the control logic circuit 420 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit.

[0104] It should be understood by those skilled in the art that the operations performed by the row decoder 430, the page buffer 460, the control logic circuit 420, and the voltage generator 440 described in the present disclosure may be performed by a processing circuit, wherein the processing circuit may include but is not limited to hardware of a logic circuit or a hardware / software combination of a processor that executes software.

[0105] Specifically, when the peripheral circuit 400 works, the following steps are performed: Fig.13 The operation method shown includes steps S10-S20, and the peripheral circuit 400 can execute at least one of steps S10 or S20.

[0106] See also Fig.13 , the memory operation method provided by the embodiment of the present disclosure includes:

[0107] S10: In the erasing phase, an erasing voltage is applied to the word line, and an erasing voltage is applied to the selection gate line coupled to the target selection tube.

[0108] Since electrical isolation is not used to shorten programming time, the threshold voltage of the selector tube will not be adjusted. Fig.10 , since an erase cycle only includes the erase phase and the erase verification phase of the memory cell, the memory cell erase operation is performed in the time period corresponding to T1, and the memory cell erase verification operation is performed in the time period corresponding to T2, and the holding voltage (Hold & Release) is applied to both the top selection tube and the bottom selection tube. Therefore, it is necessary for both the top selection tube and the bottom selection tube to be in the holding state first, and then in the floating state. When the top selection tube and the bottom selection tube are in the floating state, the potential of the top selection tube and the bottom selection tube are the same as the channel potential, so that the top selection tube and the bottom selection tube can be ensured not to be erased when the memory cell is erased.

[0109] In the scheme disclosed in the present invention, refer to Fig.14 Since the threshold voltage of the selection tube needs to be adjusted, an erase cycle includes not only the erase phase and the erase verification phase of the storage unit, but also at least the selection tube programming phase, the selection tube programming verification phase and the pre-programming phase. Therefore, compared with the solution without electrical separation, the erase cycle included in the solution disclosed in the present invention increases a certain amount of time. Therefore, in order to shorten the duration of the erase cycle, the erase process of the storage unit and the selection tube can be integrated.

[0110] That is, in the solution of the present disclosure, in the process of erasing the storage unit, the target selection tube needs to be erased at the same time. Since the electrical isolation effect is achieved by the bottom selection tube in the present disclosure, the threshold voltage of the bottom selection tube may drift, that is, the threshold voltage of the bottom selection tube needs to be readjusted. It should be noted that the target selection tube refers to the bottom selection tube selected to perform the erase and program operations.

[0111] For example, see Fig.14 In the erasing phase of an erasing cycle, i.e., in the T2 time period, the control logic circuit 420 controls the row decoder 430 to apply the erasing voltage Vss generated by the voltage generator 440 to the word line, and also controls the row decoder 430 to apply the erasing voltage Vss generated by the voltage generator 440 to the bottom selection gate line GSL coupled to the target bottom selection tube, and the control logic circuit 420 controls the row decoder 430 to apply the erasing voltage Vers generated by the voltage generator 440 to the bit line. That is, in the programming phase of a programming cycle, the row decoder 430 applies the same first erasing voltage Vss to the word line and the bottom selection gate line GSL, and provides the second erasing voltage Vers to the bit line. In the present disclosure, the erasing voltage applied to the word line and the bottom selection gate line is referred to as the first erasing voltage, and the erasing voltage applied to the bit line is referred to as the second erasing voltage. While erasing the memory cell, the bottom selection tube is erased. It should be noted that the second erasing voltage Vers is a high potential, and the first erasing voltage Vss is a low potential (0V), which can form a larger potential difference between the channel potential and the gate potential of the storage page to be erased and the bottom selection tube, so as to realize the erasing of the storage unit and the bottom selection tube.

[0112] S20: In the selection tube programming stage, a pass voltage is applied to the word line, and a programming voltage is applied to the selection gate line coupled to the target selection tube.

[0113] After the erasing operation on the storage unit and the bottom selection tube is completed, in order to ensure the normal use of the electrical isolation function, the threshold voltage of the bottom selection tube needs to be programmed to its corresponding target threshold voltage.

[0114] For example, continue as Fig.14As shown, in the selection tube programming phase of an erase cycle, i.e., in the T4 time period, the control logic circuit 420 controls the row decoder 430 to apply the pass voltage Vpass generated by the voltage generator 440 to the word line, and also controls the row decoder 430 to apply the programming voltage Vpgm3 generated by the voltage generator 440 to the bottom selection gate line GSL coupled to the target bottom selection tube. That is, in the selection tube programming phase of a programming cycle, the row decoder 430 applies the erase voltage Vpass and the programming voltage Vpgm3 to the word line and the bottom selection gate line GSL, respectively, that is, the bottom selection tube is programmed to program the threshold voltage of the bottom selection tube to its corresponding target threshold voltage.

[0115] The solution provided by the embodiment of the present disclosure is to erase and program the selection tube at the same time during the erasing process of the storage unit, so as to recalibrate the threshold voltage of the selection tube with failure risk. By resetting the state of the threshold voltage of the selection tube, its potential failure problem is eliminated, and the threshold voltage is recalibrated to the expected range, thereby improving the reliability and stability of the selection tube, thereby ensuring the normal realization of the electrical isolation function.

[0116] When performing an erase operation on the bottom selection tubes, if the threshold voltages of the bottom selection tubes themselves are different, the bottom selection tubes will not be consistent after erasing. Therefore, in order to ensure that the selection tubes have the same threshold voltage after erasing, that is, to make the selection tubes have better consistency, it is necessary to perform a pre-programming operation on the selection tubes before performing an erase operation on the selection tubes, so that all the selection tubes have the same threshold voltage when performing an erase operation.

[0117] The solution provided by the embodiments of the present disclosure is shown in Fig.15 , before the erasing phase, a pre-programming phase is also included, and the method further includes:

[0118] S100: In the pre-programming stage, a pre-programming voltage is applied to the word line or a pass voltage is applied to the selection gate line coupled to the target selection tube.

[0119] Through the pre-programming operation, the potential of the channel can be raised by extracting electrons in the channel. As an example, in the programming phase of an erase cycle, that is, in the T1 time period, the row decoder 430 applies the pre-programming voltage Vpgm1 and the pre-programming voltage Vpgm2 to the selection gate line coupled to the target selection tube. It should be noted that the bottom selection tube on the same selection gate line includes two threshold voltages of Va and Vb, so the pre-programming voltage includes Vpgm1 and Vpgm2, so that the bottom selection tubes with different threshold voltages D can be programmed to the same threshold voltage to facilitate the subsequent erase operation.

[0120] After the execution of erasure, the storage unit will be verified, but the selection tube will not be verified. In the solution disclosed in the present invention, since the selection tube is also erased when the storage unit is erased, it is necessary to verify the selection tube while verifying the storage unit. In a possible implementation, refer to Fig.15 , the method provided by the embodiment of the present disclosure also includes:

[0121] S110: During the erase phase, a holding voltage is applied to the top selection tube.

[0122] In the erasing stage, since only the bottom selection tube is erased and programmed, the top selection tube does not need to be erased. Therefore, the voltage of the top selection tube needs to be in a holding state first, and then in a floating state, so that the potential of the top selection tube is the same as the channel potential, thereby ensuring that the top selection tube will not be erased when the bottom selection tube and the storage unit are erased.

[0123] As an example, during the erase phase of an erase cycle, ie, time period T2, the control logic circuit 420 controls the row decoder 430 to apply the hold voltage (Hold & Release) generated by the voltage generator 440 to the top selection tube so that the top selection tube will not be erased.

[0124] The solution provided by the embodiment of the present disclosure includes an erase verification phase after the erase phase and before the select tube programming phase. The erase verification phase requires not only the storage unit to be erased and verified, but also the target select tube to be erased and verified. In a possible implementation, refer to Fig.15 , the method provided in the embodiment of the present application also includes:

[0125] S120: In the erase verification phase, a first verification voltage is applied to the selection gate line coupled to the target selection transistor.

[0126] For storage cells, by verifying the erase operation, on the one hand, it can ensure that the data in the erased storage cells are completely cleared and no longer interfere with subsequent reading or programming. On the other hand, it can ensure that the data in the storage cells are completely cleared, thereby avoiding potential data residue problems. For the bottom selection tube, by verifying the erase operation, it can be ensured that all the bottom selection tubes are in the same state after erasing, making it easier to recalibrate the threshold voltage of the selection tube to the expected range later.

[0127] As an example, in the erasure verification phase, i.e., in the T5 time period, when the row decoder 430 applies the erasure voltage Vpass to the word line, the first verification voltage Vpv1 is also applied to the bottom selection gate line GSL. That is, in the programming phase of a programming cycle, the row decoder 430 applies the erasure voltage Vpass and the first verification voltage Vpv1 to the word line and the bottom selection gate line GSL, respectively, that is, while verifying the erased state of the memory cell, the erased state of the bottom selection tube is also verified.

[0128] In the process of reprogramming the bottom selection tubes, in order to program different bottom selection tubes to their respective corresponding target threshold voltages, it is necessary to apply different voltages to different top selection tubes.

[0129] In one possible implementation, see Fig.15 , the method provided by the embodiment of the present disclosure also includes:

[0130] S210: In the selection tube programming stage, a programming selection voltage is applied to the top selection tube of the storage string where the target selection tube is located, and a programming inhibition voltage is applied to the top selection tubes of other storage strings.

[0131] As an example, in the selection tube programming stage of an erase cycle, i.e., in the T4 time period, the process of programming the bottom selection tube G1Str1 is described, and the bottom selection tube G1Str1 is the target selection tube. When the row decoder 430 applies the programming selection voltage Vcc to the top selection tube on the storage string Str1, the programming inhibition voltage Vss is also applied to the top selection tube on the storage string Str2. Similarly, when programming the bottom selection tube G1Str2, the bottom selection tube G1Str2 is the target selection tube. When the row decoder 430 applies the programming selection voltage Vcc to the top selection tube on the storage string Str2, the programming inhibition voltage Vss is also applied to the top selection tube on the storage string Str1.

[0132] After completing the programming operation on all bottom selection tubes, in order to ensure that the threshold voltages of all bottom selection tubes reach the target threshold voltage, it is necessary to perform programming verification on all bottom selection tubes, and execute corresponding processing strategies according to the verification results.

[0133] In one possible implementation, see Fig.15 After the tube selection programming stage, a tube selection programming verification stage is also included. The method provided by the embodiment of the present disclosure also includes:

[0134] S2201: In the selection tube programming verification stage, a second verification voltage is applied to the selection gate line coupled to the target selection tube, and when the threshold voltage of the target selection tube does not reach the target threshold voltage, the programming voltage is increased.

[0135] In the embodiments of the present disclosure, refer to Fig.13 First, verify whether the threshold voltage of the target bottom selection tube reaches the predetermined value under the current programming voltage. If it has reached the predetermined value, the threshold voltage distribution of the bottom selection tube meets the requirements, and the programming of the bottom selection tube is completed. If the threshold voltage of the bottom selection tube does not reach the predetermined value, the next programming voltage is used for programming, and the above steps are repeated until the threshold voltage of the target bottom selection tube reaches the target threshold voltage.

[0136] As an example, in the selection tube programming verification stage of an erase cycle, that is, in the T5 time period, the control logic circuit 420 controls the row decoder 430 to apply the second verification voltage Vpv2 generated by the voltage generator 440 to the bottom selection gate line coupled to the bottom selection tube, and then determines whether the threshold voltage of the target bottom selection tube reaches a predetermined value. If the threshold voltage of the target bottom selection tube reaches the predetermined value, the process ends. If the threshold voltage of the target bottom selection tube does not reach the predetermined value, the control logic circuit 420 controls the row decoder 430 to apply the programming voltage Vpgm4 generated by the voltage generator 440 to the bottom selection gate line coupled to the bottom selection tube, and then the control logic circuit 420 controls the row decoder 430 to apply the second verification voltage Vpv2 generated by the voltage generator 440 to the bottom selection gate line coupled to the bottom selection tube, and continues to perform the above-mentioned judgment steps until the threshold voltage of the bottom selection tube reaches the target threshold voltage. It should be noted that the programming voltage Vpgm4 has a certain increment based on the programming voltage Vpgm3.

[0137] During programming of the selection tubes, in order to ensure that only the storage string where the target bottom selection tube is located will be programmed and verified, thereby avoiding misoperation of other storage strings, different voltage operations need to be performed on the top selection tubes of different storage strings.

[0138] In one possible implementation, see Fig.15 , the method provided by the embodiment of the present disclosure also includes:

[0139] S2202: In the selection tube programming verification stage, a programming selection voltage is applied to the top selection tube of the storage string where the target selection tube is located, and a pass voltage is applied to the top selection tubes of other storage strings.

[0140] Applying a programming selection voltage to the top selection tube of the storage string where the target selection tube is located is to turn on the top selection tube of the target storage string, thereby selecting the target selection tube to perform a programming verification operation. Passing a voltage to the top selection tubes of other storage strings where the non-target selection tubes are located is to not turn on the top selection tube of the target storage string, thereby preventing the non-target selection tubes from being selected to perform a programming verification operation.

[0141] As an example, in the selection tube programming verification stage of an erase cycle, i.e., in the T5 time period, the process of programming verification of the bottom selection tube G1Str1 is described, and the bottom selection tube G1Str1 is the target selection tube. When the row decoder 430 applies the programming selection voltage Vpass to the top selection tube (the first top selection tube) on the storage string Str1, the programming inhibition voltage Vss is also applied to the top selection tube (the second top selection tube) on the storage string Str2. Similarly, when programming the bottom selection tube G1Str2, the bottom selection tube G1Str2 is the target selection tube. When the row decoder 430 applies the programming selection voltage Vpass to the top selection tube on the storage string Str2, the programming inhibition voltage Vss is also applied to the top selection tube on the storage string Str1.

[0142] In one possible implementation, see Fig.15 , the method provided by the embodiment of the present disclosure also includes:

[0143] S2203: During the selection tube programming verification phase, a pass voltage is applied to the word line.

[0144] In the selection tube programming verification stage, since no corresponding operation will be performed on the memory cell, a pass voltage is applied to the word line to turn on the memory cell that is not selected for programming.

[0145] As an example, during the select tube programming verification phase of an erase cycle, ie, time period T5, the control logic circuit 420 controls the row decoder 430 to apply the pass voltage Vpass generated by the voltage generator 440 to the word line so that no further operation is performed on the memory cell.

[0146] The memory operation method provided by the present disclosure erases and programs the selection tube at the same time during the erasing process of the storage unit, thereby recalibrating the threshold voltage of the selection tube with failure risk, and the failure risk refers to the drift of the threshold voltage of the selection tube. By resetting the state of the selection tube, its potential failure problem is eliminated, and the threshold voltage is recalibrated to the expected range, thereby improving the reliability and stability of the selection tube, thereby ensuring the normal realization of the electrical separation function.

[0147] The embodiment of the present disclosure further provides a memory, for example, the memory may be the aforementioned Fig. 9 The memory shown includes a peripheral circuit, and the peripheral circuit is configured as follows:

[0148] In the erasing phase, an erase voltage is applied to the word line, and an erase voltage is applied to the selection gate line coupled to the target selection tube; in the selection tube programming phase, a pass voltage is applied to the word line, and a programming voltage is applied to the selection gate line coupled to the target selection tube.

[0149] In some embodiments, after the erase phase and before the select tube programming phase, an erase verification phase is also included, and the peripheral circuit is further configured to: in the erase verification phase, apply a first verification voltage to the select gate line coupled to the target select tube.

[0150] In some embodiments, the selection tube includes a top selection tube and a bottom selection tube, the target selection tube is the bottom selection tube, and the peripheral circuit is further configured to: in the selection tube programming stage, apply a programming selection voltage to the top selection tube of the storage string where the target selection tube is located, and apply a programming prohibition voltage to the top selection tubes of other storage strings.

[0151] In some embodiments, after the selection tube programming stage, a selection tube programming verification stage is also included, and the peripheral circuit is further configured to: in the selection tube programming verification stage, apply a second verification voltage to the selection gate line coupled to the target selection tube; when the threshold voltage of the target selection tube does not reach the target threshold voltage, increase the programming voltage.

[0152] In some embodiments, the selection tube also includes a top selection tube, and the peripheral circuit is further configured to: in the selection tube programming verification stage, apply a programming selection voltage to the top selection tube of the storage string where the target selection tube is located, and apply a pass voltage to the top selection tubes of other storage strings.

[0153] In some embodiments, the peripheral circuit is further configured to: apply a pass voltage to the word line during a selection tube programming verification phase.

[0154] In some embodiments, the peripheral circuit is further configured to: apply a holding voltage to the top selection transistor during the erase phase.

[0155] In some embodiments, before the erase phase, a pre-programming phase is also included, and the peripheral circuit is further configured to: in the pre-programming phase, apply a pre-programming voltage to the word line or pass voltage to apply a pre-programming voltage to the selection gate line coupled to the target selection tube.

[0156] The present disclosure also provides a memory system. For example, the memory system includes the memory and the memory controller as described in the above embodiment, and the memory is coupled to the memory controller. Figure 2 or Figure 3 The memory system shown.

[0157] The present disclosure also provides an electronic device, which includes a host and the aforementioned memory system, wherein the host is connected to the memory system and is used to store data in the memory system or read data read by the memory system. Figure 1 The electronic device shown.

[0158] Those skilled in the art can clearly understand that, for the convenience and brevity of description, in the above embodiments, the description of each embodiment has different emphases, and the parts that are not described in detail in a certain embodiment can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0159] In the several embodiments provided in the present disclosure, it should be understood that the provided programming method and memory can be implemented in other ways. For example, the division of a module is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0160] Those of ordinary skill in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this disclosure.

[0161] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for operating a memory, characterized in that: The memory includes a plurality of memory strings, the memory strings include a plurality of memory cells and a plurality of selection tubes, the memory cells are coupled to word lines, the selection tubes are coupled to selection gate lines, and the method includes: In the erasing phase, an erasing voltage is applied to the word line, and an erasing voltage is applied to the selection gate line coupled to a target selection tube among the plurality of selection tubes; In the selection tube programming stage, a pass voltage is applied to the word line, and a programming voltage is applied to the selection gate line coupled to the target selection tube.

2. The memory operation method according to claim 1, characterized in that: After the erasing stage and before the selecting tube programming stage, an erasing verification stage is also included, and the method further includes: In the erase verification phase, a first verification voltage is applied to the selection gate line coupled to the target selection transistor.

3. The memory operation method according to claim 2, characterized in that: The selection tube comprises a top selection tube and a bottom selection tube, the target selection tube is the bottom selection tube, and the method further comprises: In the selection tube programming stage, a programming selection voltage is applied to the top selection tube of the storage string where the target selection tube is located, and a programming prohibition voltage is applied to the top selection tubes of other storage strings.

4. The memory operation method according to claim 3, characterized in that: After the selection tube programming stage, a selection tube programming verification stage is further included, and the method further includes: In the selection tube programming verification stage, applying a second verification voltage to the selection gate line coupled to the target selection tube; When the threshold voltage of the target selection tube does not reach the target threshold voltage, the programming voltage is increased.

5. The memory operation method according to claim 4, characterized in that: The method further comprises: In the selection tube programming verification stage, a programming selection voltage is applied to the top selection tube of the storage string where the target selection tube is located, and a pass voltage is applied to the top selection tubes of other storage strings.

6. The memory operation method according to claim 4, characterized in that: The method further comprises: During the selection tube programming verification stage, a pass voltage is applied to the word line.

7. The memory operation method according to claim 4, characterized in that: The method further comprises: In the erasing phase, a holding voltage is applied to the top selection transistor.

8. The memory operation method according to any one of claims 1 to 7, characterized in that: Before the erasing stage, a pre-programming stage is also included, and the method further includes: In the pre-programming stage, a pre-programming voltage or a pass voltage is applied to the word line, and a pre-programming voltage is applied to the selection gate line coupled to the target selection tube.

9. A memory, characterized in that: include: A memory cell array and a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit is configured as follows: In the erasing phase, an erasing voltage is applied to the word line, and an erasing voltage is applied to the selection gate line coupled to a target selection tube among the plurality of selection tubes; In the selection tube programming stage, a pass voltage is applied to the word line, and a programming voltage is applied to the selection gate line coupled to the target selection tube.

10. The memory according to claim 9, characterized in that: After the erasing stage and before the selecting tube programming stage, an erasing verification stage is also included, and the peripheral circuit is further configured as follows: In the erase verification phase, a first verification voltage is applied to the selection gate line coupled to the target selection transistor.

11. The memory according to claim 10, characterized in that: The selection tube includes a top selection tube and a bottom selection tube, the target selection tube is a bottom selection tube, and the peripheral circuit is further configured as: In the selection tube programming stage, a programming selection voltage is applied to the top selection tube of the storage string where the target selection tube is located, and a programming prohibition voltage is applied to the top selection tubes of other storage strings.

12. The memory according to claim 11, characterized in that: After the selection tube programming stage, a selection tube programming verification stage is also included, and the peripheral circuit is further configured as follows: In the selection tube programming verification stage, applying a second verification voltage to the selection gate line coupled to the target selection tube; When the threshold voltage of the target selection tube does not reach the target threshold voltage, the programming voltage is increased.

13. The memory according to claim 12, characterized in that: The selection tube further includes a top selection tube, and the peripheral circuit is further configured as: In the selection tube programming verification stage, a programming selection voltage is applied to the top selection tube of the storage string where the target selection tube is located, and a pass voltage is applied to the top selection tubes of other storage strings.

14. The memory according to claim 12, characterized in that: The peripheral circuit is further configured as: During the selection tube programming verification stage, a pass voltage is applied to the word line.

15. The memory according to claim 12, characterized in that: The peripheral circuit is further configured as: In the erasing phase, a holding voltage is applied to the top selection transistor.

16. The memory according to any one of claims 9 to 15, characterized in that: Before the erasing phase, a pre-programming phase is also included, and the peripheral circuit is further configured as follows: In the pre-programming stage, a pre-programming voltage or a pass voltage is applied to the word line, and a pre-programming voltage is applied to the selection gate line coupled to the target selection tube.

17. A memory system, characterized in that: The invention comprises a storage controller and the memory according to any one of claims 9 to 16, wherein the storage controller is configured to control the memory to write data or read data stored in the memory.

18. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions; after the computer-executable instructions are executed, the method provided in any one of claims 1 to 8 can be implemented.

Images