Branch coverage rate calculation method and device based on BOOL logic

Abstract

The invention discloses a branch coverage rate calculation method and device based on BOOL logic, and relates to the technical field of software testing. The method is suitable for the test case taking the BOOL logic expression as basic test data, the branch path diagram is generated according to the BOOL logic expression, the coverage rate condition of the test case set on the BOOL logic branches is calculated according to the covered path condition in the case execution process, covered and uncovered BOOL branch reports are output according to the test execution condition, and the test efficiency is improved. The test case executed by the black box is transparent, and meanwhile, a test case set can be completed according to uncovered branch guidance in an output report.

Description

Technical Field

[0001] The present invention relates to the field of software testing technology, in particular to the field of automatic testing technology of computer interlocking systems, and more specifically to a branch coverage calculation method and device based on BOOL logic. Background Art

[0002] The rapid development of high-speed railways and urban rail transit has brought convenience to people's travel, all thanks to the safety guarantee of the railway signal system. The interlocking system, as the core control system of the signal system, is an embedded real-time system based on a computer, which realizes the interlocking control of station equipment and ensures driving safety. Computer interlocking system software is a typical safety-related software with very complex interlocking control logic and safety requirements centered on failure. The realization of its safety requirements is a very arduous task.

[0003] The interlocking test guidelines currently designed by various signal manufacturers and railway bureaus are mainly based on the TB.T3537-2018 Railway Station Computer Interlocking Test Specification. The scenarios covered by the test cases are limited. Because the inputs such as the system acquisition device status and the issuance of human-machine interface commands are randomly changing, within a given state space, it is difficult for manually designed test cases to achieve 100% coverage of BOOL logic branches.

[0004] Most automatic test execution processes are black-box. When the basic logic of the test object is based on a set of BOOL logical expressions, since the branches of the BOOL logical expressions are not unique and different branches correspond to different test scenarios, when a test case checks that a BOOL variable is true, even if the test result is passed, it is difficult to define which BOOL branch this test case scenario corresponds to, so there may be situations where scenarios are missed.

[0005] For BOOL interlocking rules, after given the rules and test cases, it is particularly important to determine the coverage of these test cases on the BOOL logic, whether key scenarios are missed, and how to effectively increase test cases to improve branch coverage. Summary of the invention

[0006] In order to overcome the defects and shortcomings existing in the above-mentioned prior art, the present invention provides a branch coverage calculation method and device based on BOOL logic. The present invention aims to provide a method suitable for test cases based on BOOL logic expressions as test data, generate a branch path graph according to the BOOL logic expression, calculate the coverage of the BOOL logic branches by the test case set according to the paths covered during the execution of the case, and output the coverage and uncovered BOOL branch reports according to the test execution situation, so as to make the test cases executed by the black box transparent, and at the same time, guide the improvement of the test case set according to the uncovered branches in the output report.

[0007] In order to solve the above problems existing in the prior art, the present invention is implemented through the following technical solutions.

[0008] A first aspect of the present invention provides a branch coverage calculation method based on BOOL logic, the method comprising the following steps: S1, convert the input BOOL logic data into a T-type graph structure; S2, process and split the original BOOL expression, and store each branch of the BOOL expression in the form of a branch path diagram; S3, outputting path identifiers for key nodes on branch paths in the branch path graph; S4, executing the test case set by simulating the test module with the help of the test tool, marking the accessed BOOL variables during the execution process; S5. Obtain the accessed path according to the access tag, calculate the test path branch coverage, and generate a branch coverage report.

[0009] Further preferably, in step S1, the input BOOL logical data is converted into a T-type graph structure, specifically, the variable on the left side of the equal sign of the BOOL expression corresponds to the variable VAR on the main road in the T-type graph, the logical relationship on the right side of the equal sign of the BOOL expression is constructed through the branches in the T-type graph, the "logical and" between the variables corresponds to series connection, the "logical or" corresponds to parallel connection, and the "logical not" corresponds to drop connection.

[0010] More preferably, as long as all variables on any branch meet the condition of forming a connected VAR, VAR=1 holds; if all branches do not form a connected VAR, VAR=0; the condition of forming a connected VAR means that the result of the branch logic operation is 1; not forming a connected VAR means that the result of the branch logic operation is 0.

[0011] Further preferably, in step S2, each branch of the BOOL expression is stored in the form of a branch path graph, specifically, the stored path name records the key node path.

[0012] More preferably, the stored path name records the key node path, specifically, the path naming adopts the "ROOT_VAR~COV:Count:route" format, wherein ROOT_VAR is the root node variable name, that is, the variable name on the left side of the equal sign of the BOOL expression; Count is a counter, counting sequentially starting from 1; route is the path from the top node to the current child node in the path graph, the edge path passed by the left branch is represented by the number 0, and the edge path passed by the right branch is represented by the number 1, and the edges are connected by "-"; the rest are fixed formats.

[0013] More preferably, the top node in the branch path graph is used to store the BOOL variable on the left side of the BOOL expression, while ensuring that each minimum branch in the T-type graph falls on the last node in the path graph, and the minimum branch refers to a branch that does not contain a "logical or" in the branch.

[0014] Further preferably, in step S2, the code processing logic for storing each branch of the BOOL expression in the form of a branch path graph is as follows: if the parent node expression contains both "logical AND" and "logical OR", and the child node expression has only "logical OR" or "logical OR" and "logical NOT", the parent node path is named in the "ROOT_VAR~COV:Count:route" format; if the child node is a transition node, the expression corresponding to this child node is further iterated and split, and the child node path is not generated; when the child node expression does not contain "logical OR", the child node path is named in the "ROOT_VAR~COV:Count:route" format.

[0015] Further preferably, in step S3, the path identifier is generated only at the end node with a BOOL variable and the main branch node of the T-type graph.

[0016] Further preferably, in step S4, the test case set is a collection of a series of test cases, and according to the case description, BOOL assignments are performed on input variables with the help of an automatic testing tool, and then the testing tool performs logical operations based on the input variables according to a given BOOL logic to check whether the key variables after calculation are consistent with the expected values.

[0017] Further preferably, in step S5, the branch coverage report includes at least branch coverage and a set of covered and uncovered branch paths after the use case is executed.

[0018] Further preferably, the method further comprises step S6, analyzing or supplementing the test case set according to the branch paths not covered in the branch coverage report.

[0019] The second aspect of the present invention provides a branch coverage calculation device based on BOOL logic, which includes an input module, a test tool and an output module, wherein the input module is used to input a BOOL logic file and a test case set, and the output module is used to output a test result and a branch coverage report; the test tool includes a T-type graph conversion module, a simulation test module and a branch coverage module; wherein the T-type graph conversion module is used to read the BOOL logic file input in the input module, and convert the BOOL expression into a T-type graph according to the T-type graph conversion rule; the branch coverage module is used to split the BOOL expression in the input file Processing, storing each BOOL logic branch according to the branch path diagram; judging the node storing the variable set in the branch path diagram, and generating a node path for the node according to the set rules when it is judged to be a key node; the simulation test module is used to execute the test case set, and the variables that have changed during the execution of the case are tracked and marked, mapped to the node path of the branch path diagram according to the set rules, and the test results are output through the output module; the branch coverage module also calculates the branch coverage based on the branches visited and the branches not visited in the branch path diagram, and generates a branch coverage report, and the output module outputs the branch coverage report.

[0020] The third aspect of the present invention provides a computer device, comprising a processor, an input device, an output device and a memory, wherein the processor, the input device, the output device and the memory are interconnected, wherein the memory is used to store a computer program, the computer program comprises program instructions, and the processor is configured to call the program instructions to execute some or all of the steps described in the first aspect of the present invention.

[0021] A fourth aspect of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program for electronic data exchange, wherein the computer program enables a computer to execute some or all of the steps described in the first aspect of the present invention.

[0022] Compared with the prior art, the beneficial technical effects brought by the present invention are as follows: 1. Most automatic test execution processes are black-box. When the branch paths of BOOL expressions are not unique, it is difficult to define which branch a test case scenario is implemented through. Different branches correspond to different test scenarios, so there may be cases where scenarios are missed. The present invention generates branch coverage paths based on BOOL logic to make the test case process executed by black boxes transparent.

[0023] 2. The method and device of the present invention can output the BOOL branches covered and uncovered during the execution of the test case, and can guide the improvement of the test case set according to the uncovered branches in the output report.

[0024] 3. In the present invention, each branch path of the BOOL expression is stored in the form of a branch path graph, which is convenient for searching and finding variable paths, and path identifiers are output only at key nodes, which can improve search efficiency.

[0025] 4. The present invention converts BOOL logic into a T-type diagram, which is convenient for testing process debugging and BOOL path visualization. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a flow chart of the branch coverage calculation method based on BOOL logic of the present invention; Figure 2 It is a schematic diagram of the structure of the branch coverage calculation device based on BOOL logic of the present invention; Figure 3 It is a schematic diagram of the structure of a T-type graph in an embodiment of the present invention; Figure 4 For Figure 3 The branching path diagram corresponding to the T-graph shown. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the specification of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] Example 1 As a preferred embodiment of the present invention, refer to the attached specification Figure 1 As shown, this embodiment provides a branch coverage calculation method based on BOOL logic, and the method includes the following steps: S1, convert the input BOOL logic data into a T-type graph structure; S2, process and split the original BOOL expression, and store each branch of the BOOL expression in the form of a branch path diagram; S3, outputting path identifiers for key nodes on branch paths in the branch path graph; S4, executing the test case set by simulating the test module with the help of the test tool, marking the accessed BOOL variables during the execution process; S5. Obtain the accessed path according to the access tag, calculate the test path branch coverage, and generate a branch coverage report.

[0029] The BOOL logic data conversion T-type graph structure is to facilitate test case debugging and realize BOOL path visualization. The T-type graph is a graph structure similar to a series-parallel circuit, such as Figure 3 Shown is a simplified T-graph example.

[0030] As an implementation method of this embodiment, the input BOOL logical data is converted into a T-type graph structure, specifically, for example, the BOOL expression is: BOOL VAR=(branch ①+branch ②); when performing the T-type graph conversion, the variable on the left side of the equal sign of the BOOL expression corresponds to the variable VAR on the main road of the T-type graph, and the logical relationship on the right side of the equal sign of the BOOL expression is connected through each branch in the T-type graph. The "logical and" between the variables corresponds to series connection, the "logical or" corresponds to parallel connection, and the "logical not" corresponds to drop connection. As long as all variables on any branch meet the condition of connecting VAR, VAR=1 is established. If all branches do not connect VAR, VAR=0; the condition of connecting VAR means that the branch logic operation result is 1, and not connecting VAR means that the branch logic operation result is 0. For example, "logical or" means parallel connection, which is the parallel connection between different branches. "+" is used to divide the parallel branches, "+" means "logical or", "*" means "logical and", and ".N." means "logical negation". Then the expression VAR=A*.N.B+C is divided into two branches, branch ① is A*.NB; branch ② is C; then the condition for VAR to be connected is that the result of the logical calculation of any branch is 1, that is, A*.NB=1 or C=1, where A*.NB=1, that is, A=1 and B=0. If all branches are blocked, the results of the logical operation of all branches are 0. For example, VAR=A*.N.B+C, the results of the logical operation of the two branches are both 0, and for branch ①, A*.NB=0, that is, A=0 or B=1; for branch ②, C=0.

[0031] As another implementation of this embodiment, in step S2, the key technology for generating the branch path graph is: 1. The path name should be able to record the key node path.

[0032] As an example, the path naming adopts the format of "ROOT_VAR~COV:Count:route", where ROOT_VAR is the root node variable name, that is, the variable name on the left side of the BOOL expression equal sign; Count is a counter, which counts sequentially from 1; route is the path from the top node to the current child node in the path graph, the edge path passed by the left branch is represented by the number 0, the edge path passed by the right branch is represented by the number 1, and the edges are connected by "-"; the rest are fixed formats. Other naming methods can also be used to accurately record the key node path.

[0033] 2. The top node in the path diagram is used to store the BOOL variable on the left side of the BOOL expression. When using it, it should be ensured that each minimum branch in the T-type diagram falls on the last node in the path diagram. The minimum branch means that the branch does not contain "logical or".

[0034] 3. To improve search efficiency, path identifiers are only generated at the end nodes with BOOL variables and the main branch nodes of the T-type graph. The code processing logic for storing each branch of the BOOL expression in the form of a branch path graph is as follows: if the parent node expression contains both "logical AND" and "logical OR", and the child node expression only has "logical OR" or "logical OR" and "logical NOT", the parent node path is named in the "ROOT_VAR~COV:Count:route" format; if the child node is a transition node, the expression corresponding to this child node is further iterated and split, and the child node path is not generated; if the child node expression does not contain "logical OR", the child node path is named in the "ROOT_VAR~COV:Count:route" format.

[0035] Split the BOOL expression branch according to "logical OR", and each "logical OR" branch occupies one node for storage; if the "logical OR" branch after splitting is a combination of A*(B+C) (where A, B, and C are the smallest branch units that do not contain "logical OR"), then the node where the combined branch is located needs to generate a node path. At the same time, because the combined branch contains "logical OR", the branch needs to be further split until the branch after splitting does not contain "logical OR", that is, B and C each occupy one child node, and the child node path needs to be generated at the same time.

[0036] During the splitting process, the node that stores only the branch that contains the "logical OR" combination is called a transition node. Such a node does not generate a path. For example, when the node stores the branch B+C, it is a transition node. The node path is named in the format of "ROOT_VAR~COV:Count:route".

[0037] As another implementation of this embodiment, the test case set is a collection of a series of test cases. According to the use case description, BOOL assignment is performed on the input variables with the help of an automatic testing tool. Then, the testing tool performs logical operations based on the input variables according to a given BOOL logic to check whether the key variables after calculation are consistent with the expected values.

[0038] As another implementation of this embodiment, the branch coverage report includes at least branch coverage and a set of covered and uncovered branch paths after the test case is executed. According to the uncovered branch paths in the branch coverage report, the test case set is analyzed or supplemented.

[0039] Example 2 As another preferred embodiment of the present invention, this embodiment is based on the above embodiment 1, and further elaborates and supplements the technical solution of the present invention. This embodiment provides an example of T-type graph conversion and branch path graph generation. Figure 3 and attached Figure 4 As shown: A BOOL logical expression can be simplified to VAR=(A*(B+C)+D), where A, B, C, and D represent a set of variables or a single variable that only has "logical AND". According to the T-type diagram conversion principle, logical AND is represented by series connection and logical OR is represented by parallel connection. This BOOL expression can be converted to Figure 3 The T-type graph shown. This T-type graph contains 2 main branches, which are split according to the OR branch. There is no logical OR condition in the variable set D on the second branch, so it can be directly stored on the right child node of the top node. A*(B+C) in the first branch is placed on the left child node under the top node, but the set contains logical OR, so it needs to be further split and finally split to the terminal node without logical OR. According to the edge passed by the terminal node, the path of each node is recorded. Because the terminal node on the first branch only retains the variable sets B and C on the minimum branch, and omits the variable set A, the node A*(B+C) may output the path identifier according to the key node. The output branch path graph is as follows Figure 4 shown.

[0040] Example 3 As another preferred embodiment of the present invention, refer to the attached specification Figure 2 As shown, this embodiment provides a branch coverage calculation device based on BOOL logic, which includes an input module, a test tool and an output module, wherein the input module is used to input a BOOL logic file and a test case set, and the output module is used to output a test result and a branch coverage report; the test tool includes a T-type graph conversion module, a simulation test module and a branch coverage module; wherein the T-type graph conversion module is used to read the BOOL logic file input in the input module, and convert the BOOL expression into a T-type graph according to the T-type graph conversion rule; the branch coverage module is used to split the BOOL expression in the input file Processing, storing each BOOL logic branch according to the branch path diagram; judging the node storing the variable set in the branch path diagram, and generating a node path for the node according to the set rules when it is judged to be a key node; the simulation test module is used to execute the test case set, and the variables that have changed during the execution of the case are tracked and marked, mapped to the node path of the branch path diagram according to the set rules, and the test results are output through the output module; the branch coverage module also calculates the branch coverage based on the branches visited and the branches not visited in the branch path diagram, and generates a branch coverage report, and the output module outputs the branch coverage report.

[0041] As an implementation method of this embodiment, the above-mentioned T-type diagram conversion rule is that the variable on the left side of the equal sign of the BOOL expression corresponds to the variable VAR on the main road of the T-type diagram, and the logical relationship on the right side of the equal sign of the BOOL expression is connected through each branch in the T-type diagram. The "logical and" between the variables corresponds to series connection, the "logical or" corresponds to parallel connection, and the "logical negation" corresponds to drop connection. As long as all variables on any branch meet the conditions for connecting VAR, VAR=1 is established, otherwise if all branches do not connect VAR, VAR=0; the condition for connecting VAR means that the branch logic operation result is 1, and not connecting VAR means that the branch logic operation result is 0.

[0042] The path name stored in the branch path graph records the key node path. The path naming adopts the format of "ROOT_VAR~COV:Count:route", where ROOT_VAR is the root node variable name, that is, the variable name on the left side of the BOOL expression equal sign; Count is a counter, which counts sequentially from 1; route is the path from the top node to the current child node in the path graph, the edge path passed by the left branch is represented by the number 0, and the edge path passed by the right branch is represented by the number 1, and the edges are connected by "-"; the rest are fixed formats. The top node in the branch path graph is used to store the BOOL variable on the left side of the BOOL expression, and at the same time ensure that each minimum branch in the T-type graph falls on the last node in the path graph. The minimum branch refers to the branch that does not contain "logical or" in the branch.

[0043] The code processing logic is that if there is "logical or" in the parent node expression and there is no "logical or" in the child node expression, the path naming adopts the "ROOT_VAR~COV:Count:route" format; if the parent node expression contains both "logical and" and "logical or", and the child node expression only has "logical or" or "logical or" and "logical negation", the parent node path naming adopts the "ROOT_VAR~COV:Count:route" format; if the child node is a transition node, the expression corresponding to this child node is further iterated and split, and the child node path is not generated; when the child node expression does not contain "logical or", the child node path naming adopts the "ROOT_VAR~COV:Count:route" format.

[0044] The test case set is a collection of a series of test cases. According to the case description, BOOL values ​​are assigned to input variables with the help of automatic testing tools. Then the testing tool performs logical operations based on the input variables according to the given BOOL logic to check whether the key variables after calculation are consistent with the expected values.

[0045] The branch coverage report includes at least branch coverage and a set of covered and uncovered branch paths after the test case is executed. According to the uncovered branch paths in the branch coverage report, the test case set is analyzed or supplemented.

[0046] Example 4 As another preferred embodiment of the present invention, in order to achieve the above-mentioned purpose, according to another aspect of the present application, a computer device is also provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps of the above-mentioned branch coverage calculation method based on BOOL logic when executing the computer program.

[0047] In this embodiment, the processor may be a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or a combination of the above chips.

[0048] The memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer executable programs and units, such as the corresponding program module units in the above method embodiments of the present invention. The processor executes various functional applications of the processor and works data processing by running the non-transitory software programs, instructions and modules stored in the memory, that is, implementing the method in the above method embodiments.

[0049] The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created by the processor, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0050] The one or more units are stored in the memory, and when executed by the processor, perform the steps of the above-mentioned embodiment 1 or embodiment 2.

[0051] Example 5 As another preferred embodiment of the present invention, this embodiment discloses a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned embodiment 1 or embodiment 2 are implemented.

Claims

1. A branch coverage calculation method based on BOOL logic, characterized in that: The method comprises the following steps: S1, convert the input BOOL logic data into a T-type graph structure; S2, process and split the original BOOL expression, and store each branch of the BOOL expression in the form of a branch path diagram; S3, outputting path identifiers for key nodes on branch paths in the branch path graph; S4, executing the test case set by simulating the test module with the help of the test tool, marking the accessed BOOL variables during the execution process; S5. Obtain the accessed path according to the access tag, calculate the test path branch coverage, and generate a branch coverage report.

2. The branch coverage calculation method based on BOOL logic as claimed in claim 1, characterized in that: In step S1, the input BOOL logical data is converted into a T-type diagram structure. Specifically, the variable on the left side of the equal sign of the BOOL expression corresponds to the variable VAR on the main road of the T-type diagram, and the logical relationship on the right side of the equal sign of the BOOL expression is connected through each branch in the T-type diagram. The "logical and" between the variables corresponds to series connection, the "logical or" corresponds to parallel connection, and the "logical not" corresponds to drop connection.

3. A branch coverage calculation method based on BOOL logic as claimed in claim 2, characterized in that: As long as all variables on any branch meet the condition of forming a VAR, VAR=1 holds. If all branches do not form a VAR, VAR=0. The condition of forming a VAR means that the result of the branch logic operation is 1, and not forming a VAR means that the result of the branch logic operation is 0.

4. A method for calculating branch coverage based on BOOL logic as claimed in any one of claims 1 to 3, characterized in that: In step S2, each branch of the BOOL expression is stored in the form of a branch path graph, specifically, the stored path name records the key node path.

5. A method for calculating branch coverage based on BOOL logic as claimed in claim 4, characterized in that: The stored path name records the key node path. Specifically, the path naming adopts the "ROOT_VAR~COV:Count:route" format, where ROOT_VAR is the root node variable name, that is, the variable name on the left side of the BOOL expression equal sign; Count is a counter, which counts sequentially starting from 1; route is the path from the top node to the current child node in the path graph, the edge path passed by the left branch is represented by the number 0, and the edge path passed by the right branch is represented by the number 1, and the edges are connected by "-"; the rest are fixed formats.

6. A branch coverage calculation method based on BOOL logic as claimed in claim 5, characterized in that: The top node in the branch path diagram is used to store the BOOL variable on the left side of the BOOL expression, and ensure that each minimum branch in the T-type diagram falls on the last node in the path diagram. The minimum branch refers to the branch that does not contain "logical or" in the branch.

7. The method for calculating branch coverage based on BOOL logic as claimed in claim 5, characterized in that: In step S2, the code processing logic for storing each branch of the BOOL expression in the form of a branch path graph is as follows: if the parent node expression contains both "logical AND" and "logical OR", and the child node expression only has "logical OR" or "logical OR" and "logical NOT", the parent node path is named in the "ROOT_VAR~COV:Count:route" format; if the child node is a transition node, the expression corresponding to this child node is further iterated and split, and the child node path is not generated; when the child node expression does not contain "logical OR", the child node path is named in the "ROOT_VAR~COV:Count:route" format.

8. A method for calculating branch coverage based on BOOL logic according to any one of claims 1 to 3, characterized in that: In step S3, path identifiers are generated only at the end nodes with BOOL variables and the main branch nodes of the T-type graph.

9. A method for calculating branch coverage based on BOOL logic according to any one of claims 1 to 3, characterized in that: In step S4, the test case set is a collection of a series of test cases. According to the case description, the input variables are assigned BOOL values ​​with the help of an automatic testing tool. Then the testing tool performs logical operations based on the input variables according to the given BOOL logic to check whether the key variables after calculation are consistent with the expected values.

10. A method for calculating branch coverage based on BOOL logic according to any one of claims 1 to 3, characterized in that: In step S5, the branch coverage report includes at least branch coverage and a set of covered and uncovered branch paths after the use case is executed.

11. A method for calculating branch coverage based on BOOL logic according to any one of claims 1 to 3, characterized in that: The method also includes step S6, analyzing or supplementing the test case set according to the branch paths not covered in the branch coverage report.

12. A branch coverage calculation device based on BOOL logic, characterized in that: The device comprises an input module, a test tool and an output module, wherein the input module is used to input a BOOL logic file and a test case set, and the output module is used to output a test result and a branch coverage report; the test tool comprises a T-graph conversion module, a simulation test module and a branch coverage module; wherein the T-graph conversion module is used to read the BOOL logic file input in the input module, and convert the BOOL expression into a T-graph according to the T-graph conversion rule; the branch coverage module is used to split the BOOL expression in the input file, and store each BOOL logic branch according to a branch path graph; the node storing the variable set in the branch path graph is judged, and when it is judged to be a key node, a node path is generated for the node according to a set rule; the simulation test module is used to execute the test case set, and during the execution of the test case, the variables that have changed are tracked and marked, mapped to the node path of the branch path graph according to the set rule, and the test result is output through the output module; the branch coverage module also calculates the branch coverage according to the branches visited and the branches not visited in the branch path graph, and generates a branch coverage report, and the branch coverage report is output by the output module.

13. A computer device, comprising a processor, an input device, an output device and a memory, wherein the processor, the input device, the output device and the memory are interconnected, the memory is used to store a computer program, the computer program comprises program instructions, and is characterized in that: The processor is configured to call the program instructions to execute part or all of the steps described in the branch coverage calculation method based on BOOL logic as described in any one of claims 1 to 11.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program for electronic data exchange, wherein the computer program enables a computer to execute part or all of the steps described in a branch coverage calculation method based on BOOL logic as described in any one of claims 1 to 11.

Images