Test method and device for detecting quality of power supply of solid state disk

Abstract

The invention discloses a test method and device for detecting the quality of a power supply of a solid state disk. The device comprises a first type programmable power supply chip, a main control chip correspondingly connected with the solid state disk, and n voltage sensors and n current sensors arranged on the first type programmable power supply chip; and n second type programmable power supply chips, and each second type programmable power supply chip and the n NAND are arranged in a one-to-one correspondence manner. And n voltage sensors and n current sensors are arranged on one second type programmable power supply chip corresponding to each NAND. Each power supply chip is set to obtain different fluctuation thresholds of normal working voltage according to a set load; and judging the condition that the voltage input value fluctuates in different threshold values, and taking corresponding measures. The defects that problems cannot be found in time and measures cannot be taken in time due to the fact that input and output fluctuation and power change of a power supply cannot be accurately monitored in a traditional method are overcome.

Description

Technical Field

[0001] The present application relates to the field of semiconductor storage technology, and in particular to a power supply detection technology for a solid state drive. Background Art

[0002] With the widespread use of SSDs in computers and embedded systems, power quality detection for SSDs has become critical. Power quality is critical to the matching of SSD circuits or power-consuming devices, and poor power quality may cause device failure or even damage. Therefore, real-time monitoring of power input and output and providing complete real-time safety protection are essential to ensure stable system operation.

[0003] At present, the power quality detection of solid-state drives often relies on traditional detection methods, which lack real-time and accuracy. Traditional methods may not be able to accurately monitor the fluctuations and power changes of power input and output, resulting in the inability to detect problems in time and take measures to solve them.

[0004] In addition, due to the task-based working characteristics of the NAND of the solid-state drive, the transmission method cannot accurately monitor the changes in the NAND, resulting in low NAND working efficiency or affecting the service life. Summary of the invention

[0005] The technical problem to be solved by the present application is to provide a testing method and device for detecting the power quality of solid-state hard drives, so as to improve the technical defects that traditional methods may not be able to accurately monitor the fluctuations and power changes of power input and output, resulting in the inability to timely discover problems and take measures to solve the problems.

[0006] Furthermore, the present invention can accurately monitor the fluctuation of power input and output and power variation of NAND according to the task-based working characteristics of NAND, thereby avoiding the impact on the quality of NAND.

[0007] This application adopts the following technical solutions to solve the above technical problems: A test device for detecting the power quality of a solid-state hard disk, characterized by comprising: a first type of programmable power chip corresponding to a main control chip connected to the solid-state hard disk, and n voltage sensors and n current sensors are arranged on the first type of programmable power chip; Also, n second-type programmable power chips are provided, each of which corresponds to n NANDs; and n voltage sensors and n current sensors are provided on a second-type programmable power chip corresponding to each NAND.

[0008] In the above technical solution, a backup power supply chip is provided, and n voltage sensors and n current sensors are provided on the backup power supply chip.

[0009] In the above technical solution, the test device for detecting the power quality of the solid-state hard disk is connected to the solid-state hard disk power management module as an external plug-in unit in an insertable manner. Naturally, a first-class programmable power chip and a plurality of second-class programmable power chips are arranged in the external plug-in unit to form an FPGA control module. The solid-state hard disk power management module is connected to the main control chip and each NAND in a voltage pin manner.

[0010] In the above technical solution, the test device for detecting the power quality of the solid-state hard disk is connected to the solid-state hard disk in an insertion manner via an FPGA protocol interface to a USB interface.

[0011] In the above technical solution, the voltage sensor is connected to each programmable power chip through a voltage pin.

[0012] In the above technical solution, the current sensor is connected to each programmable power chip through a current pin.

[0013] A test method for detecting the power quality of a solid state hard disk, characterized by: Install n voltage sensors and n current sensors on the main control chip and the programmable power chips corresponding to the n NANDs respectively; According to the load of each power chip, the rated working voltage of the power chip and the first fluctuation amplitude based on the rated working voltage are set, and the normal fluctuation limit range is obtained, that is, the upper and lower limit values ​​of the normal fluctuation are determined; the second fluctuation amplitude is set on the basis of the normal fluctuation limit, and the safe fluctuation limit range of the power chip is determined respectively; that is, the safe fluctuation limit is determined by the highest fluctuation limit value and the lowest fluctuation limit value; the normal fluctuation limit range is within the safe fluctuation limit range; For each power chip, take the voltage values ​​collected by n voltage sensors, calculate the weighted arithmetic mean as the voltage input value; take the current values ​​collected by n current sensors, calculate the weighted arithmetic mean as the current input value; Calculate the real-time power based on the voltage input value and the current input value to make power judgment; when the real-time power is greater than or less than the rated power, it will display the power abnormality; Determine whether the voltage input value of each voltage chip fluctuates within the normal fluctuation upper and lower limit range and the safe fluctuation limit range, and when it exceeds the safe fluctuation limit range, shut down the power supply, or issue a warning and switch to the backup power supply chip; When the power is between the upper and lower limits of normal fluctuations and the safe fluctuation limit, cyclic detection, multiple restarts and real-time power judgment are performed. If the power judgment is abnormal, the power is turned off, or a warning is issued and the power is switched to the backup power chip.

[0014] In the above technical solution, if the voltage input value fluctuates within the normal fluctuation limit range, it indicates that the power quality is normal.

[0015] In the above technical solution, when calculating the voltage input value and the current input value, the weighted values ​​of different types of power chips are set differently or the same, thereby adapting to different working modes and read and write tasks of different types of chips (corresponding to NAND and master control).

[0016] In the above technical solution, when calculating the voltage input value and the current input value, the weighted values ​​of the sensors corresponding to the power chip of the same NAND are set differently or the same, thereby adapting to different types of working modes and read-write tasks to meet the diverse and frequent access and read-write operation requirements of NAND.

[0017] Of course, we prefer that in the same NAND, the weighted value of one or several sensors connected to the areas with busier work or more frequent tasks is larger than that of relatively idle areas, thereby ensuring the quality test effect under the condition of efficient NAND reading and writing.

[0018] In the above technical solution, the same fluctuation amplitude of different types of power chips is the same or different, thereby adapting to different partition read-write test conditions.

[0019] In the above technical solution, the two fluctuation amplitudes of the same power chip are set to be the same or different, thereby adapting to different judgment efficiencies. For example, the fluctuation amplitude ratio can be increased to quickly perform voltage management control and protect power safety.

[0020] In the above technical solution, the second fluctuation amplitude and the first fluctuation amplitude are set to 3%-8% based on the normal fluctuation limit, preferably 5%.

[0021] After the testing device for detecting the power quality of the solid state hard disk is connected to the solid state hard disk, the test state is entered.

[0022] In the above technical solution, after the power is turned on, the programmable power chip sets the normal working value of the solid state hard disk, and the sensor starts working. At this time, the power supply has no output.

[0023] In the above technical solution, first determine whether the voltage input value fluctuation is within the upper limit of the normal fluctuation upper and lower limit range. If not, the circuit issues a warning and sends an instruction to the sensor to delay the cycle detection until the power output is within the upper and lower limits and the warning is automatically lifted. If yes, the sensor continues to monitor the voltage and current; then determine whether it is within the safe fluctuation limit range. If not, the circuit issues a warning and sends an instruction to the sensor to delay the cycle detection until the power output is within the upper and lower limits and the warning is automatically lifted. If yes, the sensor continues to monitor the voltage and current. For situations between the two ranges, power judgment is added. When the real-time power is greater than or less than the rated power, the power abnormality is displayed.

[0024] In summary, the present invention discloses a test method and device for detecting the power quality of a solid-state hard disk. n voltage sensors and n current sensors are installed on the main control chip of the solid-state hard disk and each programmable power chip corresponding to n NANDs respectively; the test device for detecting the power quality of the solid-state hard disk is connected to the solid-state hard disk and enters a test state. In the test state, the power chip is set to calculate different thresholds of normal working voltage according to a set load; the voltage sensor and the current sensor respectively collect the weighted arithmetic mean of the voltage and the current; it is judged that the voltage input value fluctuates at different thresholds, and corresponding measures are taken.

[0025] The present invention can thus improve the technical defect that the traditional method cannot accurately monitor the fluctuation and power change of the power input and output, resulting in the inability to timely discover the problem and take measures to solve the problem.

[0026] Compared with the existing technology, the beneficial effects of this application are as follows: Improve the accuracy of power quality detection: Install voltage sensors and current sensors at the main control and NAND respectively, perform separate calculations, and calculate the weighted arithmetic mean of n sensors to more accurately determine the actual value of the power supply, thereby improving the accurate monitoring and evaluation of power quality.

[0027] Introducing a real-time monitoring mechanism: The FPGA power chip microcontroller calculates and monitors voltage and current data in real time, promptly discovers power quality problems, and enhances the system's ability to monitor and control power stability. Real-time monitoring of power input and output accurately determines power conditions, ensures stable system operation, and reduces the risk of equipment failure and damage.

[0028] Automatic fault handling function: When the power supply fluctuates or the back-end current (judged by power consumption) exceeds the threshold, the system automatically issues a warning and takes corresponding measures, such as automatically removing the warning or prompting a back-end circuit failure or switching to a backup power chip, effectively protecting the back-end circuit and electrical equipment, and improving the system's automation and fault handling efficiency. Improve the system's safety and stability. Reduce maintenance costs: Automatic processing functions and fault prompt mechanisms quickly identify and solve power problems, reducing manual intervention and maintenance costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 This is a structural diagram of a testing device for detecting the power quality of a solid-state hard disk according to an embodiment of the present application.

[0031] Figure 2 A structural block diagram of a test device for detecting the power quality of a solid-state hard disk connected to a solid-state hard disk according to an embodiment of the present application.

[0032] Figure 3 This is a structural block diagram of an implementation of a test device for detecting the power quality of a solid-state hard disk in an embodiment of the present application, which is connected to a solid-state hard disk via a USB port through an FPGA protocol interface.

[0033] Figure 4 This is a flow chart of a testing method for detecting the power quality of a solid state drive according to an embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0035] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0036] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0037] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the product of the application is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0038] In addition, the terms "horizontal", "vertical", "overhanging" and the like do not mean that the components are required to be absolutely horizontal or overhanging, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0039] The features and performance of the present application are further described in detail below in conjunction with the embodiments.

[0040] Example 1 In order to solve the problems existing in the prior art, a device and method based on solid state hard disk power quality detection are proposed.

[0041] like Figure 1 As shown, the test device for detecting the power quality of a solid-state hard disk in this embodiment is provided with n voltage sensors and n current sensors on a programmable power chip (FPGA) corresponding to a main control chip of a solid-state hard disk (SSD), and each programmable power chip provided in a one-to-one correspondence with each NAND of the solid-state hard disk is also equipped with n voltage sensors and n current sensors.

[0042] Each programmable power chip is connected to a plurality of voltage sensors and current sensors via a voltage pin and a current pin respectively.

[0043] Specifically, the programmable power chip corresponding to the main control chip is connected to n voltage sensors through voltage pins, and is connected to n current sensors through current pins.

[0044] In the same way, on the solid state drive SSD, each NAND is correspondingly provided with a programmable power chip, and each programmable power chip is also respectively equipped with n voltage sensors and n current sensors.

[0045] Therefore, the voltage and current values ​​of each master control and each NAND chip can be recorded in real time in this way to monitor power supply fluctuations.

[0046] like Figure 1 As shown, the number of voltage sensors and current sensors of the programmable power chips corresponding to each NAND is the same, and the number of voltage sensors and current sensors of the programmable power chips corresponding to different NAND and main control chips are also the same.

[0047] That is, n NANDs are provided, and the number of voltage sensors and current sensors corresponding to the main control chip and the programmable power supply chips corresponding to the NANDs are also n respectively.

[0048] In order to maintain the flexibility of the test method and redundancy, the backup power chip and the corresponding backup voltage sensor and current sensor can also be set in the same way. Each sensor and the power chip are set in the solid state drive using the same connection method.

[0049] In a solid state drive, as is known, the master control (main controller) and multiple NAND connections, such as through a series of high-speed serial interfaces, are not described in detail.

[0050] Example 2 like Figure 1-3 As shown, as an improved design of the present invention, in a solid state drive (SSD), n voltage sensors and n current sensors are set on the programmable power chip of the main control chip of the solid state drive, and n voltage sensors and n current sensors are installed on the programmable power chip at each NAND of the solid state drive.

[0051] The SSD power management module is connected to the main control (main controller) and n NAND flash memory chips through voltage pins to supply a stable voltage. The SSD power management module is connected to multiple voltage sensors through voltage pins and multiple current sensors through current pins.

[0052] In addition, an FPGA control module containing multiple programmable power chips (FPGA) is set up. The FPGA control module identifies the interface form of the SSD and connects to the USB interface (FPGA protocol interface to USB interface) through the FPGA protocol conversion chip, so that the solid-state drive can be connected via USB insertion, and the power quality of the solid-state drive can be conveniently detected by plug-and-play.

[0053] like Figure 3 As shown, at least one of the SATA, M.2, and U.2 interfaces can be used to convert to USB interfaces, forming a SATA interface to USB interface; an M.2 interface to USB interface; and a U.2 interface to USB interface, so as to facilitate connecting the SSD through different protocols.

[0054] Similarly, n FPGA power chips in the FPGA control module are configured to correspond to n NAND flash memory chips, and then an additional power chip is configured to correspond to the main control chip for transmitting voltage and current values ​​to the FPGA power chip.

[0055] The FPGA control module also controls the detection frequency of each sensor and monitors the count of the SSD power management module.

[0056] Example 3 Based on Examples 1 and 2, Figure 3 As shown, the test method for detecting the power quality of a solid state hard disk in this embodiment is performed based on the above-mentioned test device and includes the following steps: S1. When the power is turned on, all voltage sensors and current sensors start working, and the power supply has no output at this time; S2. Simulated load setting: Each programmable power chip (FPGA) sets the normal working value of the solid-state drive according to the solid-state drive load, including setting the load current and load voltage of each power chip; Each FPGA calculates its own normal operating voltage threshold according to its own individually set load voltage and current; That is, a certain percentage of overvoltage or undervoltage limit ratio is set on the nominal voltage or normal voltage range, and the percentage is increased or decreased in sequence. First, determine whether the first limit ratio on the normal voltage range is exceeded, and then continue to exceed the first limit ratio on the basis of the first limit ratio (higher voltage limit or lower voltage limit) to reach the second limit (highest voltage limit or lowest voltage limit).

[0057] For example, the normal operating voltage threshold is the ±5% fluctuation limit value of the nominal voltage value of 5V (simulating the solid-state hard disk load), where the upper fluctuation limit value of the nominal voltage value is the first threshold value (higher voltage limit), and the lower fluctuation limit value of the nominal voltage value is the third threshold value (lower voltage limit); That is, as a preference of the present invention, in the embodiment of the present invention, the first threshold value (higher voltage limit) can be set to 105% of the nominal voltage value of 5V or 5.25V.

[0058] As a preference of the present invention, in the embodiment of the present invention, the second threshold value or the maximum voltage limit can be set to 105% of the first threshold value or 5.5125V.

[0059] As a preference of the present invention, in the embodiment of the present invention, the third threshold (lower voltage limit) can be set to 95% of the nominal voltage value, such as 95% of 5V or 4.75V.

[0060] As a preference of the present invention, in the embodiment of the present invention, the fourth threshold or the lowest voltage limit may be set at 95% of the third threshold, such as 95% of 4.75V or 4.5125V.

[0061] S3, collecting voltage and current: collecting the actual voltage and current of each sensor, FPGA takes the weighted arithmetic mean of the aforementioned n current sensors as the current input value of the power supply, and takes the weighted arithmetic mean of the n voltage sensors as the voltage input value of the power supply; In this step, the voltage value passed to the FPGA is processed as follows: There are n voltage sensors at the power supply, and the voltage values ​​are V1, V2, V3, ..., Vn. The number of times each voltage value appears is M1, M2, M3, ..., Mn. The weighted arithmetic average is used for calculation, so the voltage value is: V= (V1×M1+V2×M2+V3×M3+…+VnMn) / (M1+M2+M3+…+Mn).

[0062] How the current value passed to the FPGA is processed: There are n current sensors at the power supply, and the current values ​​are I1, I2, I3, ..., In. The number of times each voltage value appears is M1, M2, M3, ..., Mn. The weighted arithmetic average is used for calculation, so the current value is: I= (I1×M1+I2×M2+I3×M3+…+InMn) / (M1+M2+M3+…+Mn).

[0063] S4. Voltage fluctuation judgment: If the voltage fluctuation is normal, that is, the voltage input value fluctuates within the first threshold, the sensor continues to monitor the voltage and current values ​​input to the SSD; If the voltage input value exceeds the first threshold, the circuit alarms and continues to judge the upper limit voltage fluctuation until the voltage input value is within the first threshold and the alarm is lifted; If the voltage input value exceeds the first threshold value, the circuit will issue a blue light flashing warning, and the FPGA will send a command to the sensor to delay the detection by 500uS until the voltage input value is within the first threshold value and the warning is automatically lifted; If the voltage input value fluctuates outside the first threshold and exceeds the second threshold or the upper limit of the first threshold by 5%, the FPGA sends a command to the power module, flashes a white light and emits a buzzer, indicating that the SSD circuit (electrical equipment) is faulty, and shuts off the power supply and switches to the backup power chip; If the voltage input value fluctuates outside the third threshold and exceeds the fourth threshold or the lower limit of the third threshold by 5%, if the output voltage of the power module still exceeds the fourth threshold, the FPGA sends a command to the power module, flashing a red light and beeping, indicating that the solid-state hard disk circuit (electrical equipment) is faulty, and turns off the power and switches to the backup power chip.

[0064] S5, power judgment: If the voltage fluctuates between the first threshold and the second threshold (high voltage fluctuation range), or fluctuates between the third threshold and the fourth threshold (low voltage fluctuation range), the power judgment is performed after continuous restart, and the real-time power is calculated by the current input value and the voltage input value of the power supply to determine whether the real-time power is normal; if the real-time power is within the nominal power value, it shows that the solid-state power supply is normal, and the sensor continues to monitor the voltage and current values ​​input to the solid-state hard disk; If the real-time power is greater than the power value or the nominal power value when the solid-state hard disk is working normally, it indicates that the solid-state power supply is abnormal. If the output voltage still exceeds the second threshold or the fourth threshold limit, it switches to the backup power chip.

[0065] The FPGA can be set to send instructions to the power module to restart once every 1S, three times in a row, or a set number of times.

[0066] In particular, when the real-time power is abnormal and exceeds the second threshold (high voltage limit), an alarm is required to shut down the power supply and switch to the backup power chip.

[0067] At this time, you can set the purple light to flash and emit a buzzer to indicate that the SSD circuit (electrical device) is faulty, and shut down the power supply and switch to the backup power chip to protect the power supply from burning out.

[0068] When the real-time power is abnormal and exceeds the fourth threshold (low voltage limit), it will directly switch to the backup power chip. Since it will not cause damage to the power supply, no alarm prompt is required.

[0069] Therefore, the present invention has the following advantages: 1. Improve system stability: monitor power input and output in real time, accurately determine power conditions, ensure stable system operation, and reduce the risk of equipment failure and damage.

[0070] 2. Strengthen system security: timely detect power quality abnormalities and take measures to effectively protect back-end circuits and electrical equipment, and improve system security and stability.

[0071] 3. Reduce maintenance costs: Automatic processing function and fault prompt mechanism can quickly identify and solve power problems, reducing manual intervention and maintenance costs.

[0072] 4. Reduce maintenance costs: Automatic processing function and fault prompt mechanism can quickly identify and solve power problems, reducing manual intervention and maintenance costs.

[0073] Example 4 Based on Examples 1 and 2, when the device of the present invention is used for power quality detection, the following test preparation procedures are required: Test environment: Ensure that the necessary test tools and equipment are available, including power monitoring equipment and load simulators. Initialization test: Connect the solid state drive to the test device of the present invention and ensure that the power supply is turned off. Power-on detection: Start the power supply, observe the power output, and record the situation where the power supply has no output. Simulated load setting: Use a programmable chip (FPGA) to set load current parameters to simulate the solid-state drive load.

[0074] Voltage and current acquisition: FPGA acquires the voltage of the power input and the current data of the simulated load. Power calculation: Based on the collected voltage and current data, FPGA calculates the power value of the current system. Power comparison: Compare the calculated power value with the power value when the SSD is working normally to determine whether it is within the normal range.

[0075] Output control: Based on the power comparison results, the FPGA controls the electrical sensor, indicator light, and buzzer to monitor the voltage and current values ​​of the SSD.

[0076] Abnormal handling: If the power is abnormal or the voltage fluctuation exceeds the threshold, the system will issue a warning and take corresponding measures, such as delaying detection or shutting down the power or switching to a backup power chip. Fault prompt: If the system continuously detects that the SSD current exceeds the threshold, the system will continuously flash the red light to indicate that there may be a fault in the SSD circuit.

[0077] The embodiments described above are part of the embodiments of the present application, rather than all of the embodiments. The detailed description of the embodiments of the present application is not intended to limit the scope of the present application for protection, but merely represents the selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present application.

Claims

1. A test device for detecting the power quality of a solid state hard disk, characterized in that include: The first type of programmable power chip corresponds to the main control chip connected to the solid state drive, and n voltage sensors and n current sensors are arranged on the first type of programmable power chip; Also, n second-type programmable power chips are provided, each of which corresponds to n NANDs; and n voltage sensors and n current sensors are provided on a second-type programmable power chip corresponding to each NAND.

2. The testing device for detecting the power quality of a solid state hard disk according to claim 1, characterized in that The testing device for detecting the power quality of the solid state hard disk is connected to the solid state hard disk power management module in an insertable manner as an external plug-in unit.

3. The testing device for detecting the power quality of a solid state hard disk according to claim 1, characterized in that The test device for detecting the power quality of the solid state hard disk is connected to the solid state hard disk in an insertion manner via an FPGA protocol interface to a USB interface.

4. The testing device for detecting the power quality of a solid state hard disk according to claim 1, characterized in that The voltage sensor is connected to each programmable power chip through a voltage pin; the current sensor is connected to each programmable power chip through a current pin.

5. A test method for detecting the power quality of a solid state drive, characterized in that: Install n voltage sensors and n current sensors on the main control chip and the programmable power chips corresponding to the n NANDs respectively; For each power chip, the rated working voltage, the first fluctuation range and the second fluctuation range of each power chip are set according to the load of each power chip; A normal fluctuation limit range is obtained based on the rated working voltage and the first fluctuation range; a safe fluctuation limit range is determined based on the normal fluctuation limit range and the second fluctuation range; and the normal fluctuation limit range is within the safe fluctuation limit range; For the same power chip, the weighted arithmetic mean of the voltage values ​​of n voltage sensors is taken as the voltage input value, and the weighted arithmetic mean of the current values ​​of n current sensors is taken as the current input value; Determine whether the voltage input value of each voltage chip fluctuates within the normal fluctuation limit range and the safe fluctuation limit range, and shut down the power supply, or issue a warning and switch to the backup power supply chip when the safe fluctuation limit range is exceeded; When the power is between the normal fluctuation limit range and the safe fluctuation limit range, the system will perform cyclic detection, restart multiple times and make real-time power judgment. If the power is abnormal, the system will shut down the power supply, issue a warning or switch to the backup power chip. The real-time power is calculated based on the voltage input value and the current input value. When the real-time power is greater than or less than the rated power, the power judgment result is abnormal power.

6. The method for testing the power quality of a solid state drive according to claim 5, characterized in that: When taking the weighted arithmetic mean, the weighted values ​​of different types of power chips can be set differently or the same.

7. The method for testing the power quality of a solid state drive according to claim 5, wherein: When taking the weighted arithmetic mean, the weighted values ​​of the sensors corresponding to the same NAND power chip are set differently or identically.

8. The method for testing the power quality of a solid state drive according to claim 5, wherein: When taking the weighted arithmetic mean, in the same NAND, the weight of one or several sensors connected to the busier area or the area with more frequent tasks is greater than that of the sensors in the relatively idle area.

9. The method for testing the power quality of a solid state drive according to claim 1, wherein: The same fluctuation amplitude of different types of power chips may be the same or different.

10. The method for testing the power quality of a solid state drive according to claim 1, wherein: The first fluctuation amplitude and the second fluctuation amplitude of the same power chip are set to be the same or different.

Images