Gate drive stage and method for operating gate drive stage
By adopting a gate driving stage driven by multiple voltage horizontally in SiC-Mosfet, the instability problem of SiC-Mosfet when switching gates is solved, and stable switching of power transistors and long-term stable threshold voltage are achieved.
Patent Information
- Application Number
- CN202411233550.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-04
- Filing Date
- 2024-09-04
- Publication Date
- 2025-03-04
AI Technical Summary
SiC-Mosfet has instability when switching gates, resulting in problems such as increased threshold voltage and parasitic on.
A gate driving stage is adopted, including a first power transistor and a second power transistor, and the third gate of the normally closed-type operation is controlled by a node, and the third gate connection terminal is driven by three voltage levels (first voltage value, second voltage value and third voltage value) to ensure stable switching of the power transistor.
The long-term stable threshold voltage of the driven power transistor is achieved, and parasitic turn-on of the power transistor is prevented, reducing gate voltage instability.
Smart Images
Figure CN119561539A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a gate driver stage and a method for operating a gate driver stage. Background Art
[0002] Field effect transistors may have instabilities when switching the gate. This instability occurs because the component switches back and forth between a voltage far above the threshold voltage and a voltage below the flatband voltage in the operating mode. This negatively affects the circuit paths of the component.
[0003] In vehicle inverters, normally closed SiC MOSFETs are often used as switches. When a negative voltage is applied, these normally closed SiC MOSFETs are turned off. When the SiC MOSFET is in operation, it switches back and forth between a positive gate voltage and a negative gate voltage.
[0004] A disadvantage here is that an increase in the threshold voltage can occur over the course of time.
[0005] This can be prevented by switching off the SiC MOSFET at 0V.
[0006] However, a disadvantage here is that an unintentional switching on of the SiC MOSFET can occur, a so-called parasitic switching on.
[0007] The object of the present invention is to overcome these disadvantages. Summary of the invention
[0008] The gate driver stage includes a first power transistor and a second power transistor. The first power transistor has a first drain connection terminal and a first source connection terminal. The second power transistor has a second drain connection terminal and a second source connection terminal. The first source connection terminal is conductively connected to the second drain connection terminal. The first drain connection terminal is conductively connected to the first voltage connection terminal, and the second source connection terminal is conductively connected to the second voltage connection terminal. The first voltage connection terminal has a first voltage value, and the second voltage connection terminal has a second voltage value, wherein the second voltage value is less than the first voltage value. A node is arranged between the first power transistor and the second power transistor, and the node is conductively connected to the third gate connection terminal of the normally closed power transistor, wherein the third gate connection terminal can be controlled by the node. According to the present invention, the node is conductively connected to the third voltage connection terminal, wherein the third voltage connection terminal has a third voltage value, and the third voltage value is between the first voltage value and the second voltage value.
[0009] It is advantageous here that the threshold voltage of the driven power transistor is stable over the long term and parasitic switching on of the power transistor is prevented.
[0010] In one embodiment, the third voltage value is dependent on a drain-source leakage current of the normally-off-operated power transistor.
[0011] It is advantageous here that the third voltage value only needs to be applied briefly in order to avoid or significantly reduce gate voltage instabilities, since an optimum voltage can be used.
[0012] In a further embodiment, the third voltage value is dependent on the temperature of the power transistor in normally closed operation.
[0013] In one embodiment, the voltage value is a fixed value in the range between 0 V and the threshold voltage of the normally OFF-operated power transistor.
[0014] It is advantageous here that the switching process of the activated power transistor is low-loss.
[0015] In one embodiment, a parallel circuit having a first resistor, a second resistor, a first diode and a second diode is arranged between the node and the third gate connection, wherein the first resistor and the first diode are connected in parallel with the second resistor and with the second diode, and the second diode has a current flow direction opposite to that of the first diode.
[0016] The advantage here is that the switching processes in the actuated power transistor can be controlled, in other words, oscillations of the actuated power transistor can be prevented.
[0017] In another embodiment, the normally off-operated power transistor is a SiC MOSFET.
[0018] The method according to the invention for operating a gate driver stage having a first power transistor and a second power transistor comprises switching on the second power transistor at a first time, the first power transistor comprising a first drain connection and a first source connection, the second power transistor comprising a second drain connection and a second source connection, wherein the first source connection is electrically conductively connected to the second drain connection and the first drain connection is electrically conductively connected to a first voltage connection, wherein the second source connection is electrically conductively connected to the second voltage connection, wherein the first voltage connection has a first voltage value and the second voltage connection has a second voltage value, wherein the second voltage value is less than the first voltage value, wherein a node is arranged between the first power transistor and the second power transistor, the node being electrically conductively connected to a third gate connection of a normally closed power transistor, wherein the third gate connection can be controlled via the node, wherein the node is electrically conductively connected to the third voltage connection, wherein the third voltage connection has a third voltage value and the third voltage value is between the first voltage value and the second voltage value, wherein the first power transistor, the second power transistor and the normally closed power transistor are turned off. Furthermore, the method comprises switching off the second power transistor at a second point in time and switching on the first power transistor at a third point in time.
[0019] It is advantageous here that the voltage at the third gate terminal can be adjusted.
[0020] In one embodiment, a drain-source leakage current of the normally OFF-operated power transistor is detected by means of the current sense connection, and the third voltage value is set as a function of the drain-source leakage current of the normally OFF-operated power transistor.
[0021] An advantage here is that the third voltage value can be set optimally.
[0022] In a further embodiment, the temperature of the normally closed-operated power transistor is detected by means of a temperature sensor, and the third voltage value is set as a function of the temperature of the normally closed-operated power transistor.
[0023] Further advantages result from the following description of exemplary embodiments or from further developments. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The present invention is described below based on preferred embodiments and the accompanying drawings. The drawings show:
[0025] Figure 1 The gate drive stage according to the present invention is shown,
[0026] Figure 2 A method for operating a gate driver stage according to the invention is shown,
[0027] Figure 3The voltage curve according to the invention at the gate of a power transistor in normally closed operation is shown. DETAILED DESCRIPTION
[0028] Figure 1 A gate driver stage 100 is described, which has a first power transistor 101 and a second power transistor 102. The first power transistor 101 has a first drain connection and a first source connection. The second power transistor 102 has a second drain connection and a second source connection. The first source connection and the second drain connection are connected in a conductive manner, that is, the first power transistor 101 and the second power transistor 102 are connected in series. The first drain connection is connected to a first voltage connection 103, which has a first voltage value. The second source connection is connected to a second voltage connection 104, which has a second voltage value. Here, the second voltage value is less than the first voltage value. A node 105 is arranged between the first power transistor 101 and the second power transistor 102. The node 105 is conductively connected to a third gate connection of a normally closed power transistor 109, which is, for example, a SiC-MOSFET. This means that the third gate connection can be controlled via the node 105. The node 105 is also electrically conductively connected to a third voltage connection terminal 110, wherein the third voltage connection terminal 110 has a third voltage value, and the third voltage value is between the first voltage value and the second voltage value. In other words, the third gate connection terminal is driven by means of three voltage levels. Directly before opening or connecting the normally closed power transistor 109, an intermediate voltage or a third voltage value is used to load the interface state with electrons so that the positive interface charge is reduced. As a result, the electric field at the interface after opening is reduced, thereby reducing the threshold voltage drift, the so-called gate switching instability (GSI).
[0029] In an embodiment not shown, the node 105 and the third gate connection are directly connected to the line. In another embodiment not shown, a resistor is arranged between the node 105 and the third gate connection. This arrangement ensures a slow switching on of the power transistor 109 so that no oscillation occurs during the switching process. In another embodiment, as in Figure 1 As shown in FIG. 1 , a parallel circuit 106 having a first resistor 111, a second resistor 113, a first diode 112 and a second diode 114 is arranged between the node 105 and the third gate connection terminal, wherein the first resistor 111 and the first diode 112 are connected in parallel with the second resistor 113 and with the second diode 114, and the second diode 114 has a flow direction opposite to that of the first diode 112. This means that the first diode 112 is connected in antiparallel with the second diode 114.
[0030] Both the resistor and the parallel circuit 106 can be implemented within the driver ASIC or as discrete components between the driver ASIC and the power transistor to be driven or in the form of an integration in a power MOSFET.
[0031] The gate driver stage according to the invention is used in the electric drive train of an electrically or hybrid-operated vehicle, ie in a DC / DC converter and an inverter. In addition, the gate driver stage is used in a vehicle charger.
[0032] Figure 2 A method 200 for operating a gate driver stage is shown. In the initial state of the gate driver stage, the first power transistor, the second power transistor, and the normally closed power transistor are turned off. The method 200 starts from step 210, in which the second power transistor is turned on at a first time point. Therefore, the second voltage connection terminal is conductively connected to the third gate connection terminal so that a second voltage value is applied to the third gate connection terminal for a first duration. Preferably, the second voltage value is negative. In a subsequent step 220, the second power transistor is turned off at a second time point. Therefore, the third voltage connection terminal is conductively connected to the third gate connection terminal so that a third voltage value is applied to the third gate connection terminal for a second duration. For example, the third voltage value has a fixed value in a range between 0V and a threshold voltage. This value is determined by measuring on a normally closed power transistor during the manufacturing process or measuring on a module and fixedly set in a module or a gate driver stage, which is part of the module. Alternatively, the third voltage value has a low positive value, which is related to the drain-source leakage current of the normally closed power transistor or the temperature of the normally closed power transistor. In the subsequent step 230, the first power transistor is turned on at a third time point. Therefore, the first voltage connection terminal is conductively connected to the third gate connection terminal. The first voltage value is positive and higher than the threshold voltage, so that the first voltage value is applied to the third gate connection terminal for a third duration, so that the normally closed power transistor is switched or turned on. Next, the method is terminated or restarted from step 210. In other words, the gate voltage of the normally closed power transistor can be set step by step.
[0033] Figure 3 A voltage profile 300 is shown, which is obtained by Figure 2Method 200 in is generated on the third gate connection terminal. Time is shown on the x-axis, and the voltage value applied to the third gate connection terminal is shown on the y-axis. In the starting state of the method for operating the gate driver stage, the first power transistor, the second power transistor and the normally closed power transistor are turned off. This means that in the normally closed power transistor, no drain-source current flows. Alternatively, a low drain-source leakage current flows, and the drain-source leakage current is lower than a determined limit value. The determined limit value is determined by the power loss or premature opening of the normally closed power transistor. The first voltage value is, for example, 18V, the second voltage value is, for example, -5V, and the third voltage value is, for example, 0V. After the second power transistor is turned on, the second voltage value is applied to the third gate connection terminal. This means that the normally closed power transistor is turned off. After the first duration, the second power switch is turned off at a second time point, for example, by a control signal of a controller. Therefore, the third voltage value is applied to the third gate connection terminal and is used to prepare for the opening of the normally closed power transistor. In the normally closed power transistor, there is still no significant drain-source current flowing, but the interface states are loaded with electrons. This directly affects the electric field at the interface directly after opening. After the second duration, the first power transistor is switched on at a third time point, for example, by another control signal of the controller. As a result, the normally closed power transistor is switched on and the drain-source current flows through the normally closed power transistor. In other words, the interface states are loaded with electrons by means of the intermediate voltage value used directly before the normally closed power transistor is turned on, thereby reducing the electric field at the interface directly after opening and generating less threshold voltage drift.
Claims
1. A gate driver stage (100), the gate driver stage comprising a first power transistor (101) and a second power transistor (102), the first power transistor comprising a first drain connection terminal and a first source connection terminal, the second power transistor comprising a second drain connection terminal and a second source connection terminal, wherein: The first source connection terminal is conductively connected to the second drain connection terminal, and the first drain connection terminal is conductively connected to a first voltage connection terminal (103), wherein the second source connection terminal is conductively connected to a second voltage connection terminal (104), wherein the first voltage connection terminal (103) has a first voltage value, and the second voltage connection terminal (104) has a second voltage value, wherein the second voltage value is smaller than the first voltage value, wherein a node (105) is arranged between the first power transistor (101) and the second power transistor (102), wherein the node is conductively connected to a third gate connection terminal of a normally closed power transistor (109), wherein the third gate connection terminal can be controlled via the node (105), characterized in that the node (105) is conductively connected to a third voltage connection terminal (110), wherein the third voltage connection terminal (110) has a third voltage value, and the third voltage value is between the first voltage value and the second voltage value.
2. The gate driver stage (100) according to claim 1, characterized in that: The third voltage value is related to the drain-source leakage current of the normally closed power transistor (109).
3. The gate driver stage (100) according to any one of claims 1 or 2, characterized in that: The third voltage value is related to the temperature of the normally closed power transistor (109).
4. The gate driver stage (100) according to any one of the preceding claims, characterized in that The third voltage value is a fixed value in the range between 0V and a threshold voltage of the normally-off-operated power transistor (109).
5. The gate driver stage (100) according to any one of the preceding claims, characterized in that A parallel circuit (106) having a first resistor (111), a second resistor (113), a first diode (112) and a second diode (114) is arranged between the node (105) and the third gate connection terminal, wherein the first resistor and the first diode are connected in parallel with the second resistor and the second diode, and the second diode has a flow direction opposite to that of the first diode.
6. The gate driver stage (100) according to any one of the preceding claims, characterized in that The normally closed power transistor (109) is a SiC-MOSFET.
7. A method (200) for operating a gate driver stage, the gate driver stage comprising a first power transistor and a second power transistor, the first power transistor comprising a first drain connection and a first source connection, the second power transistor comprising a second drain connection and a second source connection, wherein: The first source connection is conductively connected to the second drain connection, and the first drain connection is conductively connected to a first voltage connection, wherein the second source connection is conductively connected to a second voltage connection, wherein the first voltage connection has a first voltage value, and the second voltage connection has a second voltage value, wherein the second voltage value is less than the first voltage value, wherein a node is arranged between the first power transistor and the second power transistor, the node is conductively connected to a third gate connection of a normally closed power transistor, wherein the third gate connection can be controlled via the node, wherein the node is conductively connected to a third voltage connection, wherein the third voltage connection has a third voltage value, and the third voltage value is between the first voltage value and the second voltage value, wherein the first power transistor, the second power transistor and the normally closed power transistor are turned off, and the method comprises the following steps: switching on (210) the second power transistor at a first time point, turning off (220) the second power transistor at a second point in time, and At a third point in time, the first power transistor is turned on (230).
8. The method (200) for operating a gate driver stage according to claim 7, characterized in that The drain-source leakage current of the normally closed power transistor is detected by means of a current sensing connection, and the third voltage value is set as a function of the drain-source leakage current of the normally closed power transistor.
9. The method (200) for operating a gate driver stage according to any one of claims 7 or 8, characterized in that: The temperature of the normally closed-operated power transistor is detected by means of a temperature sensor, and the third voltage value is set as a function of the temperature of the normally closed-operated power transistor.