Preparation method of rewiring structure and rewiring structure

Abstract

The invention relates to the technical field of rewiring structures, and discloses a preparation method of a rewiring structure and the rewiring structure, and the method comprises the steps: providing a semiconductor substrate; forming a barrier layer, a seed layer and a photoresist layer on the surface of one side of the semiconductor substrate; exposing and developing the photoresist layer to form a via hole window and a wiring window on the photoresist layer, and exposing the seed layer from the via hole window; forming a first metal layer on the seed layer exposed by the via hole window; removing part of photoresist reserved in the wiring window; forming a second metal layer on the first metal layer and the seed layer exposed by the wiring window; removing the photoresist layer, removing the seed layer and the barrier layer which are not covered by the first metal layer, and removing the seed layer and the barrier layer which are not covered by the second metal layer to form a via hole and a wiring layer; and forming a plastic package layer on the surface of one side of the semiconductor substrate to form a rewiring structure. The alignment deviation of the wiring layer and the via hole can be eliminated, so that the I / O density is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of redistribution structures, and in particular to a preparation method of a redistribution structure and a redistribution structure. Background Art

[0002] The Redistribution Layer (RDL) is a layer of metal wiring built between the chip and the packaging substrate. It is used to rearrange and connect the input / output (I / O) ports of the chip so that the chip can be suitable for different packaging forms and meet the requirements of packaging and system-level interconnection.

[0003] At present, two exposures are usually performed in the RDL manufacturing process. The first exposure forms the metal line (Trace) of the RDL, and the second exposure forms the via (VIA) used for vertical interconnection between the upper and lower layers of the RDL. Due to the alignment deviation caused by multiple exposures, a sufficiently large pad (Pad) needs to be reserved under the VIA to ensure that the VIA is aligned with the Pad, resulting in a waste of wiring space at the vertical interconnection, limiting the improvement of I / O density, and making it difficult for the packaging structure to meet the needs of future high-performance computing. Summary of the invention

[0004] In view of this, the present invention provides a preparation method and a rewiring structure to solve the problem that the I / O density is difficult to improve due to the alignment deviation caused by multiple exposures and the need to reserve a sufficiently large pad under the via.

[0005] In a first aspect, the present invention provides a method for preparing a rewiring structure, the method comprising: providing a semiconductor substrate; forming a barrier layer, a seed layer and a photoresist layer on a surface of one side of the semiconductor substrate, wherein the barrier layer, the seed layer and the photoresist layer are stacked from bottom to top; performing an exposure process and a development process on the photoresist layer to form a via window and a wiring window in the photoresist layer, wherein the via window exposes the seed layer and the wiring window retains a portion of the photoresist; forming a first metal layer on the seed layer exposed by the via window; removing the wiring window; A portion of the photoresist is retained to expose the seed layer through the wiring window; a second metal layer is formed on the first metal layer and the seed layer exposed by the wiring window; the photoresist layer, the seed layer and the barrier layer not covered by the first metal layer, and the seed layer and the barrier layer not covered by the second metal layer are removed to form a via and a wiring layer; a plastic encapsulation layer is formed on one side surface of the semiconductor substrate to form a rewiring structure, the plastic encapsulation layer encapsulates the wiring layer and the via, and the plastic encapsulation layer exposes the via away from the side surface of the semiconductor substrate.

[0006] In an optional embodiment, the photoresist layer is exposed and developed to form via windows and wiring windows in the photoresist layer, including: based on a target mask template, the photoresist layer is exposed, wherein the light transmittance of the area on the target mask template corresponding to the via window is greater than the light transmittance of the area on the target mask template corresponding to the wiring window; and the exposed photoresist layer is developed to form the via window and the wiring window.

[0007] In an optional embodiment, forming a first metal layer on the seed layer exposed by the via window includes: forming the first metal layer on the seed layer exposed by the via window by an electroplating process.

[0008] In an optional implementation, removing the portion of the photoresist retained in the wiring window includes: removing the portion of the photoresist retained in the wiring window by a dry etching process or a developer.

[0009] In an optional embodiment, a plastic encapsulation layer is formed on one side surface of the semiconductor substrate, including: coating polyimide on one side surface of the semiconductor substrate, the polyimide encapsulating the wiring layer and the via; curing the polyimide; chemically polishing or dry etching the cured polyimide, so that the cured polyimide exposes the via away from the side surface of the semiconductor substrate.

[0010] In an optional embodiment, removing the photoresist layer, removing the seed layer and the barrier layer not covered by the first metal layer, and removing the seed layer and the barrier layer not covered by the second metal layer, includes: removing the photoresist layer, removing the seed layer and the barrier layer not covered by the first metal layer, and removing the seed layer and the barrier layer not covered by the second metal layer by a corrosive solution.

[0011] In an optional embodiment, a barrier layer, a seed layer and a photoresist layer are formed on one side surface of the semiconductor substrate, including: sequentially forming the barrier layer and the seed layer on one side surface of the semiconductor substrate by a deposition process; and coating a photoresist on a side surface of the seed layer away from the barrier layer to form a photoresist layer.

[0012] In an optional embodiment, the material of the barrier layer includes at least one of titanium, titanium nitride, tantalum, tantalum nitride, titanium tungsten alloy and chromium, the material of the seed layer includes copper, and the materials of the first metal layer and the second metal layer each include at least one of copper, aluminum, silver, chromium, titanium, tantalum, molybdenum and neodymium.

[0013] In an optional implementation, the semiconductor substrate is a temporary bonding material or a package structure encapsulating a chip.

[0014] In a second aspect, the present invention provides a redistribution structure, which is prepared by the method provided by the first aspect or any corresponding embodiment thereof.

[0015] The present invention provides a method for preparing a redistribution structure and a redistribution structure which have at least the following beneficial effects:

[0016] (1) The preparation method of the rewiring structure provided by the present invention completes the manufacture of the wiring layer and the via through a single exposure, which can ensure that the wiring layer and the via have no alignment deviation, and there is no need to manufacture large-size pads, which effectively saves the wiring space at the vertical interconnection and significantly improves the I / O density. It can meet the future demand for high-density I / O interfaces for high-performance computing, promote the development of semiconductor packaging technology towards higher density and higher performance, and at the same time improve the overall manufacturing accuracy and product reliability.

[0017] (2) The rewiring structure obtained by the preparation method of the rewiring structure provided by the present invention can have a tighter wiring layer, and the RDL that originally required 2 or 3 layers to be laid out is optimized to 1 layer, thereby effectively reducing warping, simplifying the process, reducing process risks, and being able to effectively control production costs and improve production efficiency.

[0018] (3) The RDL preparation method provided by the present invention is not mutually exclusive with the existing RDL preparation method and can be used in combination, which greatly increases the scope of application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the related technologies, the drawings required for use in the specific embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 is a schematic diagram of a rewiring structure according to an embodiment of the present invention;

[0021] Figure 2 is a schematic diagram of a semiconductor structure in which a barrier layer, a seed layer and a photoresist layer are formed on a semiconductor substrate according to an embodiment of the present invention;

[0022] Figure 3 According to an embodiment of the present invention Figure 2 A schematic diagram of an exposure process for a semiconductor structure shown;

[0023] Figure 4 is a schematic diagram of a semiconductor structure in which a via window and a wiring window are formed in a photoresist layer according to an embodiment of the present invention;

[0024] Figure 5 is a schematic diagram of a semiconductor structure in which a first metal layer is formed on a seed layer exposed by a via window according to an embodiment of the present invention;

[0025] Figure 6 According to an embodiment of the present invention Figure 5 A schematic diagram of a semiconductor structure in which a portion of the photoresist retained in the wiring window is removed based on the structure;

[0026] Figure 7 is a schematic diagram of a semiconductor structure in which a second metal layer is formed on a first metal layer and a seed layer exposed by a wiring window according to an embodiment of the present invention;

[0027] Figure 8 According to an embodiment of the present invention Figure 7 Schematic diagram of semiconductor structure with vias and wiring layers formed on the basis;

[0028] Fig. 9 According to an embodiment of the present invention Figure 8 Schematic diagram of semiconductor structure on which a plastic encapsulation layer is formed;

[0029] Fig.10 is a schematic diagram of another rewiring structure according to an embodiment of the present invention;

[0030] Fig.11 is a schematic diagram of another rewiring structure according to an embodiment of the present invention.

[0031] Figure numerals: 110, pad; 200, semiconductor substrate; 210, barrier layer; 220, seed layer; 230, photoresist layer; 231, via window; 232, wiring window; 240, first metal layer; 250, second metal layer; 260, via; 270, wiring layer; 280, plastic layer; 300, target mask; 310, via area; 320, wiring area. DETAILED DESCRIPTION

[0032] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0033] In the following description, the description of known structures and technologies is omitted to avoid unnecessary confusion of the concept of the present invention. Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified for the purpose of clear expression, and some details may be omitted. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships between them are only exemplary, and may be deviated due to manufacturing tolerances or technical limitations in practice, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs. In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be a middle layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element.

[0034] RDL is an advanced semiconductor packaging technology that improves I / O density and electrical performance by rearranging and optimizing the I / O ports of the chip. RDL technology has the advantages of improving packaging efficiency, improving signal integrity, supporting multiple packaging technologies including flip chip and wafer-level packaging, and promoting the development of heterogeneous integration. It can be applied to integrated circuit packaging and advanced packaging, such as wafer-level chip scale packaging (WLSCP), 2.5D packaging and 3D packaging.

[0035] With the rapid development of artificial intelligence technology, the data processing capabilities of chips are increasing, and the demand for the number of I / Os is also increasing. It is necessary to further increase the I / O density of RDL to meet the needs of future high-performance computing. Figure 1 As shown, the conventional RDL technology is prone to misalignment due to multiple exposures, and a sufficiently large pad 110 needs to be reserved under the via 260, resulting in a waste of wiring space and limiting the improvement of I / O density.

[0036] In view of this, the present invention provides a method for preparing a rewiring structure. By preparing the rewiring structure through a single exposure, the alignment deviation of the wiring layer and the via can be eliminated, thereby improving the I / O density, while enhancing the manufacturing accuracy and product reliability to meet the future high-performance computing needs for high-density I / O.

[0037] like Figures 2 to 9 As shown, this embodiment provides a method for preparing a redistribution structure, and the preparation method includes but is not limited to steps S10 to S17.

[0038] Step S10, providing a semiconductor substrate.

[0039] Specifically, the semiconductor substrate may be a package structure encapsulating a chip, or may be a temporary bonding material or a silicon substrate.

[0040] Exemplarily, the chip in the package structure can be a computing or storage chip such as a central processing unit (CPU), a graphics processing unit (GPU), an application specific integrated circuit (ASIC), a memory, a field programmable gate array (FPGA), etc.

[0041] Step S11, forming a barrier layer, a seed layer and a photoresist layer on one side surface of the semiconductor substrate.

[0042] Among them, Figure 2 As shown, the barrier layer 210, the seed layer 220 and the photoresist layer 230 are stacked from bottom to top on the upper surface of the semiconductor substrate 200. When the semiconductor substrate 200 is a package structure encapsulating a chip, the upper surface of the semiconductor substrate 200 is the surface where the chip pad is located.

[0043] Specifically, the seed layer 220 is used to provide a nucleation site for subsequent metal deposition, which helps to ensure the uniformity and continuity of metal deposition. The material of the seed layer 220 can be copper or a copper alloy, etc. The barrier layer 210 is used to prevent the diffusion of metal atoms. The material of the barrier layer 210 can include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium tungsten alloy (TiW) and chromium (Cr).

[0044] In some embodiments, a barrier layer 210 and a seed layer 220 may be sequentially formed on one surface of a semiconductor substrate by a deposition process, and then a photoresist may be coated on a surface of the seed layer 220 away from the barrier layer 210 to form a photoresist layer 230 .

[0045] The deposition process involved in the present invention may be physical vapor deposition (PVD) or chemical vapor deposition (CVD).

[0046] Specifically, physical vapor deposition is a technology that evaporates or sputters source materials at high temperatures and then deposits them onto the surface of a substrate to form a thin film. The physical vapor deposition process is mainly a physical process, without the involvement of chemical reactions (or the chemical reactions are extremely weak and can be ignored). Chemical vapor deposition is a technology that generates a solid thin film on the surface of a substrate by chemically reacting a gaseous precursor under conditions such as high temperature, plasma or catalysts. The chemical vapor deposition process is mainly a chemical process.

[0047] Exemplarily, photoresist is coated on the surface of the seed layer 220 away from the barrier layer 210 to form the photoresist layer 230. Specifically, the semiconductor substrate 200 including the barrier layer 210 and the seed layer 220 is placed in the center of the tray of a coating machine, and photoresist is dropped in the center of the seed layer 220 for coating; after coating, the seed layer 220 is placed on a hot plate for soft baking to form the photoresist layer 230.

[0048] Step S12, performing exposure and development processing on the photoresist layer to form via windows and wiring windows in the photoresist layer.

[0049] Among them, Figure 4 As shown, the via window 231 exposes the seed layer 220, and the wiring window 232 retains part of the photoresist. The position and shape of the via window 231 correspond to the via position and shape required by the RDL, and the position and shape of the wiring window 232 correspond to the conductive line position and shape required by the RDL.

[0050] Specifically, during the exposure process, the exposure dose can be used to under-expose the area corresponding to the metal wiring and normally expose the area corresponding to the via, so that during the development process, the photoresist in the area corresponding to the via is completely removed to expose the seed layer 220, thereby forming a via window 231, and some photoresist remains in the area corresponding to the metal wiring, thereby forming a wiring window 232.

[0051] The underexposure of the area corresponding to the metal wiring specifically refers to that the exposure dose of the area corresponding to the metal wiring is less than the normal exposure dose, and the normal exposure dose refers to the exposure dose required for completely removing the photoresist in the area corresponding to the metal wiring.

[0052] Exposure dose is a key parameter in the photolithography process, which refers to the amount of light energy received per unit area. During the photolithography process, the size of the exposure dose determines the degree of photochemical reaction inside the photoresist.

[0053] For positive photoresist, when the exposure dose reaches a certain threshold, the photosensitive components in the photoresist (such as photoacid generators) absorb photon energy to decompose and produce acidic substances. These acidic substances will further catalyze the decomposition reaction of the photoresist polymer chain, increasing the solubility of the photoresist in the exposed area in the developer.

[0054] For negative photoresist, the exposure dose causes the polymer in the photoresist to undergo a cross-linking reaction. Under appropriate exposure doses, the photoresist in the unexposed area is soluble in the developer, while the photoresist in the exposed area becomes insoluble due to the cross-linking reaction, thereby forming a desired pattern.

[0055] The exposure process in the present invention is similar to the conventional exposure process in the art, except that the exposure dose of the metal wiring corresponding area is less than the normal exposure dose, and the development process in the present invention is the same as the conventional development process in the art.

[0056] In some embodiments, step S12 includes but is not limited to step S121 and step S122:

[0057] Step S121 , performing exposure processing on the photoresist layer based on the target mask.

[0058] Among them, Figure 3 As shown, the light transmittance of the area on the target mask plate 300 corresponding to the via window is greater than the light transmittance of the area on the target mask plate 300 corresponding to the wiring window.

[0059] For the convenience of description, the area corresponding to the via window on the target mask 300 is recorded as the via area 310, and the area corresponding to the wiring window on the target mask 300 is recorded as the wiring area 320. The light transmittance of the via area 310 is greater than that of the wiring area 320, so that the via corresponding area and the metal wiring corresponding area can receive different exposure doses, so that the metal wiring corresponding area is under-exposed and the via corresponding area is normally exposed.

[0060] Exemplarily, the materials of the via region 310 and the wiring region 320 in the target mask plate 300 can both be chromium, and the light transmittance of the via region 310 and the wiring region 320 can be adjusted by adjusting the thickness of the chromium metal layer. The via region 310 in the target mask plate 300 can also be a through hole, and the wiring region 320 is composed of chromium of a preset thickness.

[0061] Step S122, developing the exposed photoresist layer to form via windows and wiring windows.

[0062] Specifically, after the photoresist layer 230 is exposed, the photoresist layer 230 may be placed in a developer to transfer the wiring pattern and the via pattern corresponding to the redistribution structure to the photoresist layer 230, forming a Figure 4 The via window 231 and the wiring window 232 are shown.

[0063] The developer is a chemical solvent, which can be determined based on the type of photoresist (positive or negative).

[0064] Step S13, forming a first metal layer on the seed layer exposed by the via window.

[0065] For example, a layer such as the following may be formed on the seed layer 220 exposed by the via window 231 by an electroplating process. Figure 5 The first metal layer 240 is shown. It should be understood that during the electroplating process, metal will not be plated inside the wiring window 232 due to the blocking of the photoresist.

[0066] The material of the first metal layer 240 may include at least one of copper, aluminum, silver, chromium, titanium, tantalum, molybdenum and neodymium.

[0067] Specifically, the thickness of the first metal layer 240 is determined based on the thickness of the metal line and the thickness of the via required for RDL. For example, the thickness of the first metal layer 240 is the difference between the thickness of the via and the thickness of the metal line. The electroplating time and current density are determined based on the thickness of the first metal layer 240.

[0068] In other embodiments, the first metal layer may also be formed on the seed layer exposed by the via window by a deposition process.

[0069] Step S14, removing a portion of the photoresist retained in the wiring window to expose the seed layer in the wiring window.

[0070] Specifically, in the formation Figure 5 After the semiconductor structure shown in FIG. 1 is formed, the photoresist remaining in the wiring window 232 can be removed by dry etching or developer to obtain the semiconductor structure shown in FIG. Figure 6 The semiconductor structure shown.

[0071] The dry etching process uses plasma to react chemically with the photoresist, and removes the reaction products through physical bombardment to achieve photoresist removal. Based on the change in the solubility of the photoresist before and after exposure, the photoresist can also be removed through the developer. After exposure, the molecular structure of the exposed part of the positive photoresist changes and becomes soluble in the developer; while the unexposed part of the negative photoresist is soluble in the developer.

[0072] Step S15, forming a second metal layer on the first metal layer and the seed layer exposed by the wiring window.

[0073] Specifically, in the formation Figure 6 After the semiconductor structure shown in FIG. 1 is formed, a metal material may be simultaneously grown on the first metal layer 240 and the seed layer 220 exposed by the wiring window 232 by an electroplating process to form a semiconductor structure as shown in FIG. Figure 7 A second metal layer 250 is shown.

[0074] The material of the second metal layer 250 may also include at least one of copper, aluminum, silver, chromium, titanium, tantalum, molybdenum and neodymium.

[0075] In other embodiments, the second metal layer 250 may also be formed on the first metal layer 240 and the seed layer 220 exposed by the wiring window 232 by a deposition process.

[0076] Step S16, removing the photoresist layer, removing the seed layer and the barrier layer not covered by the first metal layer, and removing the seed layer and the barrier layer not covered by the second metal layer, to form vias and wiring layers.

[0077] Specifically, in forming Figure 7 After the semiconductor structure shown in FIG. 1 is formed, the photoresist layer 230, the seed layer 220 and the barrier layer 210 not covered by the first metal layer 240, and the seed layer 220 and the barrier layer 210 not covered by the second metal layer 250 can be removed by using an etching solution to form a semiconductor structure shown in FIG. Figure 8 The via 260 and the wiring layer 270 are shown. The via 260 forms a vertical interconnection structure, and the wiring layer 270 forms a complete horizontal interconnection structure.

[0078] Exemplarily, the remaining photoresist in the photoresist layer 230 can be removed by a photoresist remover or a solution such as acetone, the seed layer 220 not covered by the first metal layer 240 and the second metal layer 250 can be removed by a sulfate solution, and the blocking layer 210 under the seed layer 220 not covered by the first metal layer 240 and the second metal layer 250 can be removed by a phosphoric acid solution.

[0079] Step S17, forming a plastic encapsulation layer on one side surface of the semiconductor substrate to form a redistribution structure.

[0080] Among them, Fig. 9 As shown, the plastic encapsulation layer 280 encapsulates the wiring layer 270 and the via 260, and the plastic encapsulation layer 280 exposes a surface of the via 260 away from the semiconductor substrate 200. The material of the plastic encapsulation layer 280 can be an insulating material such as polyimide (PI) or epoxy resin.

[0081] Specifically, the top view of the redistribution structure can be as follows: Fig.10 As shown, Fig.11 Compared with the traditional rewiring structure shown, the rewiring structure prepared by the present invention does not need to manufacture large-sized Pads, effectively saving wiring space at vertical interconnections, thereby significantly improving I / O density.

[0082] The preparation method of the rewiring structure provided by the present invention completes the manufacture of the wiring layer and the via through one exposure, can make the wiring layer and the via have no alignment deviation, does not need to manufacture large-size Pads, effectively saves the wiring space at the vertical interconnection, significantly improves the I / O density, can meet the future high-performance computing needs for high-density I / O interfaces, promotes the development of semiconductor packaging technology towards higher density and higher performance, and can improve the overall manufacturing accuracy and product reliability.

[0083] Moreover, the rewiring structure obtained by the preparation method of the rewiring structure provided by the present invention can have a tighter wiring layer, and the RDL that originally required 2 or 3 layers to be laid out is optimized to 1 layer, thereby effectively reducing warping, simplifying the process, reducing process risks, and being able to effectively control production costs and improve production efficiency. In addition, the preparation method of the RDL provided by the present invention is not mutually exclusive with the existing preparation method of the RDL, and can be used in combination, which greatly increases the scope of application.

[0084] In some optional embodiments, the photoresist coated on the seed layer 220 is a chemically amplified photoresist (Chemically Amplified Resist, CAR). At this time, the step of removing a portion of the photoresist retained in the wiring window to expose the seed layer in the wiring window (i.e., step S14) can be: removing a portion of the photoresist retained in the wiring window through post exposure baking (Post Exposure Bake, PEB) and a developer.

[0085] Specifically, the PEB process is to bake the photoresist layer 230 at a certain temperature after exposure, and the temperature range can be 100°C to 150°C. During the PEB process, the acid-catalyzed reaction inside the photoresist causes chemical changes in the photoresist molecules, such as breaking the polymer chain or changing its chemical structure, so that the solubility of the photoresist in the developer changes. For positive chemically amplified photoresist, after PEB, the solubility of the exposed part of the photoresist in the developer is greatly increased. After PEB, a development process is performed, and a suitable developer (such as an alkaline developer) is used to remove the part of the photoresist retained in the wiring window.

[0086] Optionally, the step of forming a plastic encapsulation layer on one side surface of the semiconductor substrate (i.e., step S17) may include: coating polyimide on one side surface of the semiconductor substrate, the polyimide encapsulating the wiring layer and the vias; curing the polyimide; chemically polishing (Chemical Mechanical Polishing, CMP) or dry etching the cured polyimide, so that the cured polyimide exposes the vias on one side surface away from the semiconductor substrate, forming a 1P1M structure.

[0087] Exemplarily, the cured polyimide may be subjected to underexposure, development and etching, so that the cured polyimide exposes a surface of a side of the via away from the semiconductor substrate.

[0088] The present invention further provides a redistribution structure, which is prepared by the method for preparing a redistribution structure provided by any of the above embodiments.

[0089] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0090] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0091] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0092] In the description of this specification, the description with reference to the terms "this embodiment", "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0093] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0094] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the present invention.

Claims

1. A method for preparing a redistribution structure, characterized in that: The method comprises: providing a semiconductor substrate; forming a barrier layer, a seed layer and a photoresist layer on a surface of one side of the semiconductor substrate, wherein the barrier layer, the seed layer and the photoresist layer are stacked from bottom to top; Performing exposure and development processing on the photoresist layer to form a via window and a wiring window in the photoresist layer, wherein the via window exposes the seed layer and the wiring window retains a portion of the photoresist; forming a first metal layer on the seed layer exposed by the via window; Removing a portion of the photoresist retained in the wiring window, so that the wiring window exposes the seed layer; forming a second metal layer on the first metal layer and the seed layer exposed by the wiring window; Removing the photoresist layer, removing the seed layer and the barrier layer not covered by the first metal layer, and removing the seed layer and the barrier layer not covered by the second metal layer to form vias and a wiring layer; A plastic encapsulation layer is formed on one side surface of the semiconductor substrate to form a redistribution structure, wherein the plastic encapsulation layer encapsulates the wiring layer and the via hole, and the plastic encapsulation layer exposes a side surface of the via hole away from the semiconductor substrate.

2. The method according to claim 1, characterized in that The photoresist layer is subjected to an exposure process and a development process to form a via window and a wiring window in the photoresist layer, comprising: Based on a target mask, the photoresist layer is exposed, wherein the light transmittance of the area on the target mask corresponding to the via window is greater than the light transmittance of the area on the target mask corresponding to the wiring window; The photoresist layer that has been subjected to the exposure process is developed to form the via window and the wiring window.

3. The method according to claim 1, characterized in that: Forming a first metal layer on the seed layer exposed by the via window, comprising: A first metal layer is formed on the seed layer exposed by the via window through an electroplating process.

4. The method according to claim 1, characterized in that: Removing a portion of the photoresist retained in the wiring window, comprising: The portion of the photoresist retained in the wiring window is removed by a dry etching process or a developer.

5. The method according to any one of claims 1 to 4, characterized in that Forming a plastic encapsulation layer on a surface of one side of the semiconductor substrate, comprising: Coating polyimide on one side surface of the semiconductor substrate, wherein the polyimide encapsulates the wiring layer and the via hole; Performing a curing treatment on the polyimide; The cured polyimide is subjected to chemical polishing or dry etching, so that the cured polyimide exposes a surface of a side of the via away from the semiconductor substrate.

6. The method according to any one of claims 1 to 4, characterized in that Removing the photoresist layer, removing the seed layer and the barrier layer not covered by the first metal layer, and removing the seed layer and the barrier layer not covered by the second metal layer, comprising: The photoresist layer, the seed layer and the barrier layer not covered by the first metal layer, and the seed layer and the barrier layer not covered by the second metal layer are removed by an etching solution.

7. The method according to any one of claims 1 to 4, characterized in that A barrier layer, a seed layer and a photoresist layer are formed on a surface of one side of the semiconductor substrate, comprising: forming the barrier layer and the seed layer in sequence on a surface of one side of the semiconductor substrate by a deposition process; A photoresist is coated on a surface of the seed layer away from the barrier layer to form a photoresist layer.

8. The method according to claim 7, characterized in that The material of the barrier layer includes at least one of titanium, titanium nitride, tantalum, tantalum nitride, titanium-tungsten alloy and chromium, the material of the seed layer includes copper, and the materials of the first metal layer and the second metal layer each include at least one of copper, aluminum, silver, chromium, titanium, tantalum, molybdenum and neodymium.

9. The method according to any one of claims 1 to 4, characterized in that The semiconductor substrate is a temporary bonding material or a package structure encapsulating a chip.

10. A rewiring structure, characterized in that: The rewiring structure is prepared by the method according to any one of claims 1 to 9.

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