LDMOS device and forming method thereof

Abstract

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a forming method thereof, a shallow trench is arranged in a drift region, a first shallow trench isolation structure first part and a first shallow trench isolation structure second part which are isolated from each other are arranged in the shallow trench, a first field plate is formed on the first shallow trench isolation structure first part, and a second field plate is formed on the second shallow trench isolation structure second part. A first field plate is formed on the first shallow trench isolation structure first part, a second field plate is formed on the first shallow trench isolation structure second part, a control gate is formed between the first shallow trench isolation structure first part and the first shallow trench isolation structure second part, the control gate is electrically connected with the first field plate, and the control gate is isolated from the second field plate. The LDMOS device has an unexpected technical effect, regulation and control of key parameter breakdown voltage and conduction impedance of the LDMOS device can be realized by adjusting the voltage applied to the control gate, the conduction impedance is obviously reduced on the premise of not changing the size of the LDMOS device, and meanwhile, the breakdown voltage is increased to a certain extent.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an LDMOS device and a method for forming the same. Background Art

[0002] LDMOS (Lateral Diffused Metal Oxide Semiconductor) is one of the core devices of the BCD (Bipolar-CMOS-DMOS) process platform products. It is compatible with BJT (bipolar junction transistor) and CMOS (Complementary Metal Oxide Semiconductor) processes, has high-voltage and high-current driving capabilities, and consumes very little power in switching mode. LDMOS devices are composed of hundreds or thousands of single-structure LDMOS units, and their area is determined by the driving capability required by the chip. Taking PMIC (power management integrated circuit) products as an example, LDMOS devices will occupy more than half of the chip area. Therefore, the performance of LDMOS devices directly determines the driving capability and area of ​​the entire chip.

[0003] The main technical indicators of LDMOS devices include on-resistance (Rdson), breakdown voltage (BVdss) and threshold voltage (Vth). The increase in the breakdown voltage of LDMOS devices requires a long drift region and low drift region doping, but it will introduce high on-resistance, which is inconsistent with the increase in the frequency and efficiency of LDMOS devices. In order to overcome this contradiction, it is necessary to reduce the drift region resistance while increasing the breakdown voltage of LDMOS devices to improve their frequency characteristics, output efficiency, linear region characteristics, etc. There are two conventional approaches: one is the channel region engineering, that is, shortening the length of the channel region, adopting the global SOI (Silicon-On-Insulator, silicon on insulating substrate) structure, using high mobility materials such as SiGe materials for the channel doping region, using new gate materials such as molybdenum materials and strained channel region technology, etc.; the other is the drift region engineering, that is, reducing the surface field (RESURF) technology, field plate technology, field limiting ring technology, lateral variable doping technology, junction terminal extension technology, SOI technology, covering the drift region with a high dielectric constant film technology and strained silicon technology, etc. Adding an STI (Shallow Trench Isolation) structure to the drift region of the LDMOS device can significantly increase the breakdown voltage without increasing the chip area. However, the electric field concentration problem is very likely to occur at the STI bottom corner (corner) in the drift region, which leads to unexpected leakage or a reduction in breakdown voltage. In addition, the STI structure also increases the drift path of carriers, resulting in a larger on-resistance. Summary of the invention

[0004] The object of the present invention is to provide an LDMOS device and a method for forming the same, so as to solve the problem of high on-resistance and low breakdown voltage in the LDMOS device.

[0005] In order to solve the above technical problems, the present invention provides an LDMOS device, including a substrate and a drift region located in the substrate, a shallow trench is formed in the drift region, a bottom corner of the shallow trench is formed with a first shallow trench isolation structure first part and a first shallow trench isolation structure second part isolated from each other, a first field plate is formed on the first part of the first shallow trench isolation structure, a second field plate is formed on the second part of the first shallow trench isolation structure, a control gate is formed between the first part of the first shallow trench isolation structure and the second part of the first shallow trench isolation structure, the control gate is electrically connected to the first field plate, and the control gate and the second field plate are isolated from each other.

[0006] Optionally, a gate oxide is formed in the shallow trench, the gate oxide covers the sidewalls and bottom wall of the shallow trench, and the gate oxide also covers the top and sidewalls of the first part of the first shallow trench isolation structure and the top and sidewalls of the second part of the first shallow trench isolation structure.

[0007] Optionally, the substrate further includes an active region and a first conductivity type well region located in the active region, the drift region is located in the active region, and the drift region is adjacent to the first conductivity type well region, and the conductivity type of the drift region is the second conductivity type.

[0008] Optionally, the LDMOS device further includes an LDMOS gate, and the LDMOS gate is located above a portion where the first conductive type well region and the drift region are adjacent.

[0009] Based on the same inventive concept, the present invention also provides a method for forming an LDMOS device, comprising: A substrate is provided, wherein a drift region is formed in the substrate, a shallow trench and a first shallow trench isolation structure located in the shallow trench are formed in the drift region; Etching part of the first shallow trench isolation structure to expose part of the sidewall and part of the bottom wall of the shallow trench, and retaining the first part of the first shallow trench isolation structure and the second part of the first shallow trench isolation structure which are isolated from each other at the bottom corner of the shallow trench, so as to form a downward convex opening; A control gate, a first field plate, and a second field plate are formed, wherein the first field plate is located on the first portion of the first shallow trench isolation structure, the second field plate is located on the second portion of the first shallow trench isolation structure, the control gate is located between the first portion of the first shallow trench isolation structure and the second portion of the first shallow trench isolation structure, the control gate is electrically connected to the first field plate, and the control gate and the second field plate are isolated from each other.

[0010] Optionally, an active region is formed in the substrate, the drift region is located in the active region, a first conductivity type well region is also formed in the active region, the first conductivity type well region is adjacent to the drift region, and the conductivity type of the drift region is the second conductivity type.

[0011] Optionally, the step of forming the control gate, the first field plate and the second field plate includes: Forming a polysilicon material layer, the polysilicon material layer covers the first conductive type well region, the drift region, and the sidewalls and bottom wall of the lower convex opening, and the polysilicon material layer also covers the sidewalls and bottom wall of the first part of the first shallow trench isolation structure and the sidewalls and bottom wall of the second part of the first shallow trench isolation structure; Part of the polysilicon material layer is etched to retain the polysilicon material layer above the first conductive type well region and the drift region adjacent to form an LDMOS gate, and part of the polysilicon material layer in the lower convex opening is retained to form a control gate, a first field plate and a second field plate.

[0012] Optionally, after the steps of forming the control gate, the first field plate and the second field plate, the method further includes: forming a source region and a drain region, wherein the source region is located in the first conductive type well region, and the drain region is located in the drift region at one end away from the first conductive type well region.

[0013] Optionally, before forming the control gate, the first field plate and the second field plate, it also includes: forming a gate oxide, wherein the gate oxide covers the first conductive type well region, the drift region, and the side walls and bottom walls of the lower convex opening, and the gate oxide also covers the side walls and bottom walls of the first part of the first shallow trench isolation structure and the side walls and bottom walls of the second part of the first shallow trench isolation structure.

[0014] Optionally, the step of forming the lower convex opening includes: forming a first patterned photoresist layer, wherein the first patterned photoresist layer covers the first conductive type well region and the drift region and exposes the first shallow trench isolation structure; Performing a first etching process, using the first patterned photoresist layer as a mask, etching a portion of the thickness of the first shallow trench isolation structure to form a first opening; forming a second patterned photoresist layer, wherein the second patterned photoresist layer covers the first conductive type well region, the drift region and a portion of the first opening and exposes a portion of the top surface of the remaining first shallow trench isolation structure; Perform a second etching process, using the second patterned photoresist layer as a mask, and etch the remaining portion of the first shallow trench isolation structure, retaining the first portion of the first shallow trench isolation structure and the second portion of the first shallow trench isolation structure at the bottom angle of the shallow trench to form a second opening, wherein the second opening exposes the bottom wall of the shallow trench, and the first opening and the second opening together constitute a downward convex opening in the shallow trench; wherein the width of the first opening is greater than the width of the second opening.

[0015] In the LDMOS device provided by the present invention, a shallow trench is provided in the drift region, and a first part of a first shallow trench isolation structure and a second part of a first shallow trench isolation structure are provided in the shallow trench, a first field plate is formed on the first part of the first shallow trench isolation structure, a second field plate is formed on the second part of the first shallow trench isolation structure, a control gate is formed between the first part of the first shallow trench isolation structure and the second part of the first shallow trench isolation structure, the control gate is electrically connected to the first field plate, and the control gate and the second field plate are isolated from each other, that is, a control gate is added in the shallow trench of the drift region, and the potential of the control gate is separately led out, independent of the potentials of the other terminals of the LDMOS device. The key parameters of the LDMOS device, the breakdown voltage and the on-resistance, can be regulated by adjusting the voltage applied to the control gate. The present invention has unexpected technical effects, the electrical parameters of the LDMOS device are more flexible to adjust, and the adjustable range is wider, and the on-resistance is significantly reduced without changing the size of the LDMOS device, while the breakdown voltage is increased to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Those skilled in the art will appreciate that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0017] Figure 1 It is a schematic diagram of the top structure of the LDMOS device according to an embodiment of the present invention.

[0018] Figure 2 The LDMOS device of the embodiment of the present invention is Figure 1 Schematic diagram of the transverse cross-sectional structure along line AA'.

[0019] Figure 3 The LDMOS device of the embodiment of the present invention is Figure 1 Schematic diagram of the longitudinal section structure along line BB'.

[0020] Figure 4 The LDMOS device of the embodiment of the present invention is Figure 1 Schematic diagram of the longitudinal cross-section structure along the CC' line.

[0021] Figure 5 It is a flow chart of a method for forming an LDMOS device according to an embodiment of the present invention.

[0022] Figure 6 It is a schematic diagram of the structure of an LDMOS device after forming a first shallow trench isolation structure according to an embodiment of the present invention.

[0023] Figure 7 It is a schematic diagram of the structure of the LDMOS device after forming a first patterned photoresist according to an embodiment of the present invention.

[0024] Figure 8It is a schematic diagram of the structure of the LDMOS device after the first opening is formed according to an embodiment of the present invention.

[0025] Fig. 9 It is a schematic diagram of the structure of the LDMOS device after forming the second patterned photoresist according to an embodiment of the present invention.

[0026] Fig.10 It is a schematic diagram of the structure of the LDMOS device after the second opening is formed according to an embodiment of the present invention.

[0027] Fig.11 It is a schematic diagram of the structure of the LDMOS device after the gate oxide is formed according to an embodiment of the present invention.

[0028] Fig.12 It is a schematic diagram of the structure of an LDMOS device after a polysilicon material layer is formed according to an embodiment of the present invention.

[0029] Fig.13 It is a schematic diagram of the structure of the LDMOS device after forming the third patterned photoresist according to an embodiment of the present invention.

[0030] Fig.14 It is a schematic diagram of the structure of the LDMOS device after forming the control gate according to an embodiment of the present invention.

[0031] In the accompanying drawings: 10-substrate; 11-high-voltage well region; 12-drift region; 13-first conductive type well region; 14-second shallow trench isolation structure; 15-first shallow trench isolation structure; 15a-shallow trench; 15b-first opening; 15c-second opening; 15d-first part of the first shallow trench isolation structure; 15e-second part of the first shallow trench isolation structure; 16-first patterned photoresist layer; 17-second patterned photoresist layer; 18-gate oxide; 19-polysilicon material layer; 20-third patterned photoresist layer; 21-LDMOS gate; 22-first field plate; 23-control gate; 24-second field plate; 25-source region; 26-drain region. DETAILED DESCRIPTION

[0032] The present invention provides an LDMOS device, wherein a shallow trench is arranged in a drift region, and a first part of a first shallow trench isolation structure and a second part of a first shallow trench isolation structure that are isolated from each other are arranged in the shallow trench, a first field plate is formed on the first part of the first shallow trench isolation structure, a second field plate is formed on the second part of the first shallow trench isolation structure, a control gate is formed between the first part of the first shallow trench isolation structure and the second part of the first shallow trench isolation structure, the control gate is electrically connected to the first field plate, and the control gate and the second field plate are isolated from each other, and the key parameters of the LDMOS device, breakdown voltage and on-resistance, can be regulated by adjusting the voltage applied to the control gate. For example, when the device is turned on, the LDMOS gate increases the potential, and the control gate also increases the potential, which will attract electrons in the drift region at the position where the shallow trench sidewalls in the drift region contact the control gate, the first field plate, and the second field plate, forming a low-resistance path on the drift path of the carriers, and the on-resistance generated when the carriers pass through is lower; since there is a strong electric field at the position of the first shallow trench isolation structure in the shallow trench of the drift region, the thick first part of the first shallow trench isolation structure and the second part of the first shallow trench isolation structure should be retained here to avoid serious hot carrier effects at the corners of the bottom corners of the shallow trench. The second field plate will generate a coupled electric field under the action of the drain voltage. When the device is turned off, the second field plate in the drift region can make the electric field distribution near the shallow trench smoother, and can keep the depletion region of the drift region away from the Si / SiO2 interface, thereby increasing the breakdown voltage of the LDMOS device.

[0033] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0034] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second" and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second" and "third" can explicitly or implicitly include one or at least two of the features. In addition, as used in the present invention, an element is arranged on another element, which usually only indicates that there is a connection, coupling, matching or transmission relationship between the two elements, and the connection, coupling, matching or transmission between the two elements can be direct or indirect through an intermediate element, and cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, an element can be in any orientation such as inside, outside, above, below or on one side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0035] Figure 1 It is a schematic diagram of the top structure of the LDMOS device according to an embodiment of the present invention. Figure 2 The LDMOS device of the embodiment of the present invention is Figure 1 Schematic diagram of the transverse cross-section structure of the AA' line. Figure 1 to Figure 2 As shown, this embodiment provides an LDMOS device, wherein a high voltage well region (High Voltage N Well, HVNW) 11 is formed in the substrate (SUB) 10. An active region and a second shallow trench isolation structure 14 for defining the active region are formed in the high voltage well region 11. Figure 1 It can be seen that the active area surrounded by the second shallow trench isolation structure 14 is used to form a single LDMOS unit. A first conductive type well region 13 and a drift region 12 are formed in the active area, and the first conductive type well region 13 is adjacent to the drift region 12, and the conductivity type of the drift region 12 is the second conductive type. In this embodiment, the first conductive type is, for example, P-type, and the second conductive type is, for example, N-type, that is, the first conductive type well region 13 is a P-type well region (P well, PW), and the drift region 12 is an N-type well region (Nwell, NW).

[0036] Please continue to refer to Figure 2A shallow trench 15a and a first shallow trench isolation structure first part 15d and a first shallow trench isolation structure second part 15e, which are mutually isolated and located at the bottom corner of the shallow trench 15a, are formed in the drift region 12. The thickness of the first shallow trench isolation structure first part 15d and the second shallow trench isolation structure second part 15e are at least greater than one third of the shallow trench 15a. Generally, severe hot carriers will be generated at the bottom corner of the shallow trench 15. In this embodiment, a sufficiently thick first shallow trench isolation structure first part 15d and a first shallow trench isolation structure second part 15e are provided at the bottom corner of the shallow trench 15 to avoid severe hot carrier effects at the bottom corner of the shallow trench 15. It is worth emphasizing that, since the role of the shallow trench isolation structure around the active region is different from that of the shallow trench isolation structure in the drift region 12, the shallow trench isolation structure in the drift region 12 is defined as the first shallow trench isolation structure 15, and the shallow trench isolation structure around the active region is defined as the second shallow trench isolation structure 14.

[0037] Please continue to refer to Figure 2 A gate oxide 18 is formed in the shallow trench 15a, and the gate oxide 18 covers part of the sidewalls and bottom wall of the shallow trench 15a. The gate oxide 18 also covers the top and sidewalls of the first part 15d of the first shallow trench isolation structure and the top and sidewalls of the second part 15e of the first shallow trench isolation structure.

[0038] Please continue to refer to Figure 1 and Figure 2 The LDMOS device further includes an LDMOS gate 21, which is located above the junction of the first conductive type well region 13 and the drift region 12. The LDMOS gate 21 extends to the second shallow trench isolation structure 14 on both sides, and the LDMOS gate 21 on the second shallow trench isolation structure 14 is used to connect with the subsequent contact plug.

[0039] Please continue to refer to Figure 2 A control gate 23 is formed between the first shallow trench isolation structure first portion 15d and the first shallow trench isolation structure second portion 15e, which are isolated from each other. A first field plate 22 is formed on the first shallow trench isolation structure first portion 15d, and a second field plate 24 is formed on the first shallow trench isolation structure second portion 15e. The control gate 23 is connected to the first field plate 22, and the control gate 23 and the second field plate 24 are isolated from each other.

[0040] Figure 3 The LDMOS device of the embodiment of the present invention is Figure 1 Schematic diagram of the longitudinal section structure along line BB'. Figure 4 The LDMOS device of the embodiment of the present invention is Figure 1 Schematic diagram of the longitudinal section structure of the CC' line. Figure 3 As shown, the first field plate 22 is located on the first portion 15d of the first shallow trench isolation structure in the shallow trench 15a and does not extend to the second shallow trench isolation structure 14 on both sides. Figure 4 As shown, the control gate 23 is located on the bottom wall of the shallow trench 15 a and extends to the second shallow trench isolation structure 14 . The control gate 23 portion on the second shallow trench isolation structure 14 is used to connect with a subsequent contact plug.

[0041] Please continue to refer to Figure 2 The LDMOS device further includes a source region 25 and a drain region 26. The drain region 26 is located in the drift region 12 at one end away from the first conductive type well region 13. The drain region 26 is of the second conductive type and is used to connect the drain. The source region 25 is located in the first conductive type well region 13, and the source region 25 includes an N+ region and a P+ region, and the P+ region is used to connect the source and reduce the contact resistance of the source.

[0042] In this embodiment, a control gate 23 is added in the shallow groove 15a of the drift region 12, and the potential of the control gate 23 is separately led out, independent of the potentials of the other terminals of the LDMOS device. By adjusting the voltage applied to the control gate 23, the key parameters of the LDMOS device, the breakdown voltage and the on-resistance, can be regulated. The electrical parameter adjustment of the LDMOS device in this embodiment is more flexible and has a wider adjustable range. While significantly reducing the on-resistance without changing the size of the LDMOS device, the breakdown voltage is increased to a certain extent. Specifically, when the device is turned on, the LDMOS gate 21 increases the potential, and the control gate 23 also increases the potential, which will attract electrons in the drift region 12 at the side wall of the shallow groove 15a of the drift region 12 and the position of the control gate 23, the first field plate 22, and the second field plate 24, forming a low-resistance path on the drift path of the carrier, and the on-resistance generated when the carrier passes is lower. Since there is a strong electric field at the bottom corner of the shallow trench 15a, the thick first shallow trench isolation structure first part 15d and the second part 15e of the first shallow trench isolation structure are retained here to avoid serious hot carrier effects at the corners of the bottom corners of the shallow trench. The second field plate 24 will generate a coupled electric field under the action of the drain voltage. When the device is turned off, the second field plate 24 in the drift region 12 can make the electric field distribution near the shallow trench 15a smoother, and can make the depletion region of the drift region 12 away from the Si / SiO2 interface, thereby effectively increasing the breakdown voltage of the LDMOS device. Similarly, the first field plate 22 will also generate a coupled electric field under the action of the control gate voltage. When the device is turned off, the first field plate 22 in the drift region 12 can also make the electric field distribution near the shallow trench 15a smoother, and can make the depletion region of the drift region 12 away from the Si / SiO2 interface, thereby effectively increasing the breakdown voltage of the LDMOS device. The Si / SiO2 interface is also the contact area between the drift region 12 and the first shallow trench isolation structure first portion 15d, the first shallow trench isolation structure second portion 15e, and the gate oxide.

[0043] Figure 5 FIG. 1 is a flow chart of a method for forming an LDMOS device according to an embodiment of the present invention. Figure 5 As shown, this embodiment also provides a method for forming an LDMOS device, including: Step S10, providing a substrate, wherein a drift region is formed in the substrate, a shallow trench and a first shallow trench isolation structure located in the shallow trench are formed in the drift region; Step S20, etching part of the first shallow trench isolation structure to expose part of the sidewall and part of the bottom wall of the shallow trench and retaining the first part of the first shallow trench isolation structure and the second part of the first shallow trench isolation structure isolated from each other at the bottom corner of the shallow trench, so as to form a downward convex opening; Step S30, forming a control gate, a first field plate and a second field plate, wherein the first field plate is located on the first part of the first shallow trench isolation structure, the second field plate is located on the second part of the first shallow trench isolation structure, the control gate is located between the first part of the first shallow trench isolation structure and the second part of the first shallow trench isolation structure, the control gate is electrically connected to the first field plate, and the control gate and the second field plate are isolated from each other.

[0044] Figure 6 It is a schematic diagram of the structure of an LDMOS device after forming a first shallow trench isolation structure according to an embodiment of the present invention. Figure 7 It is a schematic diagram of the structure of the LDMOS device after forming a first patterned photoresist according to an embodiment of the present invention. Figure 8 It is a schematic diagram of the structure of the LDMOS device after the first opening is formed according to an embodiment of the present invention. Fig. 9 It is a schematic diagram of the structure of the LDMOS device after forming the second patterned photoresist according to an embodiment of the present invention. Fig.10 It is a schematic diagram of the structure of the LDMOS device after the second opening is formed according to an embodiment of the present invention. Fig.11 It is a schematic diagram of the structure of the LDMOS device after the gate oxide is formed according to an embodiment of the present invention. Fig.12 It is a schematic diagram of the structure of an LDMOS device after a polysilicon material layer is formed according to an embodiment of the present invention. Fig.13 It is a schematic diagram of the structure of the LDMOS device after forming the third patterned photoresist according to an embodiment of the present invention. Fig.14 1 is a schematic diagram of the structure of the LDMOS device after forming the control gate according to an embodiment of the present invention. Figures 6 to 14 The specific embodiments of the present invention are described in detail.

[0045] like Figure 6 As shown, a substrate 10 is provided. The substrate (SUB) 10 can provide an operating platform for subsequent processes. It can be any substrate for carrying semiconductor integrated circuit components known to those skilled in the art, and can be a bare chip or a wafer processed by an epitaxial growth process. In detail, the substrate 10 is, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate. In this embodiment, the substrate 10 is a silicon substrate.

[0046] Please continue to refer to Figure 6A high voltage well region (High Voltage N Well, HVNW) 11 is formed in the substrate 10. An active region and a second shallow trench isolation structure 14 for defining the active region are formed in the high voltage well region 11. A first conductive type well region 13 and a drift region 12 are formed in the active region. The first conductive type well region 13 is adjacent to the drift region 12, and the conductivity type of the drift region 12 is the second conductive type. In this embodiment, the first conductive type is, for example, P-type, and the second conductive type is, for example, N-type, that is, the first conductive type well region 13 is a P-type well region (P well, PW), and the drift region 12 is an N-type well region (N well, NW). A shallow trench 15a and a first shallow trench isolation structure 15 located in the shallow trench 15a are formed in the drift region 12. It is worth emphasizing that since the function of the shallow trench isolation structure around the active area is different from that of the shallow trench isolation structure in the drift area 12, the shallow trench isolation structure in the drift area 12 is defined as a first shallow trench isolation structure 15, and the shallow trench isolation structure around the active area is defined as a second shallow trench isolation structure 14.

[0047] like Figure 7 As shown, a first patterned photoresist layer 16 is formed, which covers the first conductive type well region 13 and the drift region 12 and exposes the top surface of the first shallow trench isolation structure 15, that is, the opening width of the first patterned photoresist layer 16 is the same as the opening top width of the shallow trench 15a.

[0048] like Figure 8 As shown, a first etching process is performed, using the first patterned photoresist layer 16 as a mask, etching a portion of the thickness of the first shallow trench isolation structure 15, forming a first opening 15b and retaining a portion of the thickness of the first shallow trench isolation structure 15, wherein the thickness of the retained first shallow trench isolation structure 15 is at least greater than one-third of the shallow trench 15a. The first opening 15b extends from the top surface of the first shallow trench isolation structure 15 to the bottom corner of the first shallow trench isolation structure 15 near the shallow trench 15a. After the step of forming the first opening 15b, if the first patterned photoresist layer 16 has not been consumed, a photoresist removal process is required, and the remaining first patterned photoresist layer 16 is usually removed by an ashing process or stripping.

[0049] like Fig. 9 As shown, a second patterned photoresist layer 17 is formed, and the second patterned photoresist layer 17 covers the first conductive type well region 13 and the drift region 12 and exposes a portion of the remaining top surface of the first shallow trench isolation structure 15. The opening width of the second patterned photoresist layer 17 is smaller than the opening width of the first patterned photoresist layer 16.

[0050] like Fig.10 As shown, a second etching process is performed, using the second patterned photoresist layer 17 as a mask, etching the remaining first shallow trench isolation structure 15, forming a second opening 15c to expose the bottom wall of the shallow trench 15a, and retaining the first shallow trench isolation structure 15 of the thickness of the two sides of the second opening 15c to form a first shallow trench isolation structure first part 15d and a first shallow trench isolation structure second part 15e. The second opening 15c extends from the bottom surface of the first opening 15b to the bottom wall of the shallow trench 15a. The first opening 15b and the second opening 15c constitute a lower convex opening. After the step of forming the second opening 15c, if the second patterned photoresist layer 17 has not been consumed, a photoresist removal process is required, usually using an ashing process or a stripping method to remove the remaining second patterned photoresist layer 17.

[0051] like Fig.11 As shown, a gate oxide 18 is formed, and the gate oxide 18 covers the side walls and bottom walls of the first conductive type well region 13, the drift region 12, and the lower convex opening. The gate oxide 18 also covers the side walls and bottom walls of the first portion 15d of the first shallow trench isolation structure and the side walls and bottom walls of the second portion 15e of the first shallow trench isolation structure. The material of the gate oxide 18 is silicon oxide, and can be formed by an in-situ water vapor process, a thermal oxidation process, or a chemical vapor deposition process. In this embodiment, an in-situ water vapor process is used to form a gate oxide with a dense structure and few interface defects.

[0052] like Fig.12 As shown, a polysilicon material layer 19 is formed, and the polysilicon material layer 19 covers the gate oxide 18. The polysilicon material layer 19 can be formed by a chemical vapor deposition process.

[0053] like Fig.13 As shown, a third patterned photoresist layer 20 is formed, and the third patterned photoresist layer 20 covers the polysilicon material layer 19 above the junction of the first conductive type well region 13 and the drift region 12 and a portion of the polysilicon material layer 19 in the second opening 15c and on the first portion 15d of the first shallow trench isolation structure. The polysilicon material layer 19 formed on the sidewall of the shallow trench 15a is not covered by the patterned photoresist layer 20, and the polysilicon material layer 19 on the second portion 15e of the first shallow trench isolation structure is not covered by the patterned photoresist layer 20.

[0054] like Fig.14As shown, a third etching process is performed, using the third patterned photoresist layer 20 as a mask, etching part of the polysilicon material layer 19, retaining the polysilicon material layer 19 above the adjacent portion of the first conductive type well region 13 and the drift region 12 to form an LDMOS gate 21, and retaining part of the polysilicon material layer 19 on the first portion 15d of the first shallow trench isolation structure in the lower convex opening to form a control gate 23. The polysilicon material layer 19 on the sidewall of the shallow trench 15a is etched, and since the polysilicon material layer 19 on the sidewall of the shallow trench 15a is arc-shaped, the etching inherits the original shape of the polysilicon material layer 19 on the sidewall of the shallow trench 15a to form a first field plate 22 and a second field plate 24. The control gate 23 is located on the bottom wall of the lower convex opening, the first field plate 22 is located on the first portion 15d of the first shallow trench isolation structure, and the second field plate 24 is located on the second portion 15e of the first shallow trench isolation structure. The control gate 23 is connected to the first field plate 22 , and the control gate 23 is isolated from the second field plate 24 .

[0055] In this embodiment, a control gate 23 is added in the shallow groove 15a of the drift region 12, and the potential of the control gate 23 is separately led out, independent of the potentials of the other terminals of the LDMOS device. By adjusting the voltage applied to the control gate 23, the key parameters of the LDMOS device, the breakdown voltage and the on-resistance, can be regulated. The electrical parameter adjustment of the LDMOS device in this embodiment is more flexible and has a wider adjustable range. While significantly reducing the on-resistance without changing the size of the LDMOS device, the breakdown voltage is increased to a certain extent. Specifically, when the device is turned on, the LDMOS gate 21 increases the potential, and the control gate 23 also increases the potential, which will attract electrons in the drift region 12 at the position where the side wall of the shallow groove 15a contacts the control gate 23, the first field plate 22, and the second field plate 24, forming a low-resistance path on the drift path of the carrier, and the on-resistance generated when the carrier passes is lower. Since there is a strong electric field at the bottom corner position in the shallow trench 15a, the thick first shallow trench isolation structure first part 15d and the second part 15e of the first shallow trench isolation structure are retained here to avoid serious hot carrier effects at the corners of the bottom corners of the shallow trench. The second field plate 24 will generate a coupled electric field under the action of the drain voltage. When the device is turned off, the second field plate 24 in the drift region 12 can make the electric field distribution near the shallow trench 15a smoother, and can make the depletion region of the drift region 12 away from the Si / SiO2 interface, thereby effectively increasing the breakdown voltage of the LDMOS device. Similarly, the first field plate 22 will also generate a coupled electric field under the action of the control gate voltage. When the device is turned off, the first field plate 22 in the drift region 12 can also make the electric field distribution near the shallow trench 15a smoother, and can make the depletion region of the drift region 12 away from the Si / SiO2 interface, thereby effectively increasing the breakdown voltage of the LDMOS device. The Si / SiO2 interface is also the contact area between the drift region 12 and the first shallow trench isolation structure first portion 15d, the first shallow trench isolation structure second portion 15e, and the gate oxide.

[0056] Please refer to Figure 2 , after the steps of forming the control gate 23, the first field plate 22, and the second field plate 24, an ion implantation process is performed to form a source region 25 in the first conductive type well region 13 and a drain region 26 is formed in the drift region 12 at one end away from the first conductive type well region 13. The drain region 26 is of the second conductive type, and the doping concentration of the N-type ions in the drain region 26 is higher than that of the drift region 12, so the drain region 26 is an N+ region for connecting the drain. The source region 25 and the drain region 26 have the same ion doping type, so the source region 25 is called an N+ region for connecting the source. And the ion implantation process is continued to implant P-type ions in the source region 25 to reduce the contact resistance of the source. Since the doping concentration of the P-type ions in the source region 25 is higher than that of the first conductive type well region 13, the source region 25 includes a P+ region.

[0057] In summary, it can be seen that the embodiment of the present invention is to set a shallow trench in the drift region, and set a first part of the first shallow trench isolation structure and a second part of the first shallow trench isolation structure that are isolated from each other in the shallow trench, a first field plate is formed on the first part of the first shallow trench isolation structure, a second field plate is formed on the second part of the first shallow trench isolation structure, and a control gate is formed between the first part of the first shallow trench isolation structure and the second part of the first shallow trench isolation structure, the control gate is electrically connected to the first field plate, and the control gate and the second field plate are isolated from each other. By adjusting the voltage applied to the control gate, the key parameters of the LDMOS device, the breakdown voltage and the on-resistance, can be regulated. The present invention has unexpected technical effects, and the electrical parameters of the LDMOS device are more flexible to adjust, and the adjustable range is wider. While significantly reducing the on-resistance without changing the size of the LDMOS device, the breakdown voltage is increased to a certain extent.

[0058] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

Claims

1. An LDMOS device, characterized in that: It includes a substrate and a drift region located in the substrate, a shallow trench is formed in the drift region, a first shallow trench isolation structure first part and a first shallow trench isolation structure second part isolated from each other are formed at the bottom corner of the shallow trench, a first field plate is formed on the first part of the first shallow trench isolation structure, a second field plate is formed on the second part of the first shallow trench isolation structure, a control gate is formed between the first part of the first shallow trench isolation structure and the second part of the first shallow trench isolation structure, the control gate is electrically connected to the first field plate, and the control gate and the second field plate are isolated from each other.

2. The LDMOS device according to claim 1, characterized in that: A gate oxide is formed in the shallow trench, and the gate oxide covers the sidewalls and bottom wall of the shallow trench. The gate oxide also covers the top and sidewalls of the first part of the first shallow trench isolation structure and the top and sidewalls of the second part of the first shallow trench isolation structure.

3. The LDMOS device according to claim 1, characterized in that: The substrate also includes an active region and a first conductivity type well region located in the active region. The drift region is located in the active region and is adjacent to the first conductivity type well region. The conductivity type of the drift region is the second conductivity type.

4. The LDMOS device according to claim 3, characterized in that: The LDMOS device further includes an LDMOS gate, which is located above a portion where the first conductive type well region and the drift region are adjacent.

5. A method for forming an LDMOS device, characterized in that: include: A substrate is provided, wherein a drift region is formed in the substrate, a shallow trench and a first shallow trench isolation structure located in the shallow trench are formed in the drift region; Etching part of the first shallow trench isolation structure to expose part of the sidewall and part of the bottom wall of the shallow trench, and retaining the first part of the first shallow trench isolation structure and the second part of the first shallow trench isolation structure which are isolated from each other at the bottom corner of the shallow trench, so as to form a downward convex opening; A control gate, a first field plate, and a second field plate are formed, wherein the first field plate is located on the first portion of the first shallow trench isolation structure, the second field plate is located on the second portion of the first shallow trench isolation structure, the control gate is located between the first portion of the first shallow trench isolation structure and the second portion of the first shallow trench isolation structure, the control gate is electrically connected to the first field plate, and the control gate and the second field plate are isolated from each other.

6. The method for forming an LDMOS device according to claim 5, characterized in that: An active region is formed in the substrate, the drift region is located in the active region, a first conductivity type well region is also formed in the active region, the first conductivity type well region is adjacent to the drift region, and the conductivity type of the drift region is the second conductivity type.

7. The method for forming an LDMOS device according to claim 6, characterized in that: The steps of forming a control gate, a first field plate and a second field plate include: Forming a polysilicon material layer, the polysilicon material layer covers the first conductive type well region, the drift region, and the sidewalls and bottom wall of the lower convex opening, and the polysilicon material layer also covers the sidewalls and bottom wall of the first part of the first shallow trench isolation structure and the sidewalls and bottom wall of the second part of the first shallow trench isolation structure; Part of the polysilicon material layer is etched to retain the polysilicon material layer above the first conductive type well region and the drift region adjacent to form an LDMOS gate, and part of the polysilicon material layer in the lower convex opening is retained to form a control gate, a first field plate and a second field plate.

8. The method for forming an LDMOS device according to claim 6, wherein: After the step of forming the control gate, the first field plate and the second field plate, the method further comprises: A source region and a drain region are formed, wherein the source region is located in the first conductive type well region, and the drain region is located in the drift region at one end away from the first conductive type well region.

9. The method for forming an LDMOS device according to claim 6, characterized in that: Before forming the control gate, the first field plate and the second field plate, the method further includes: A gate oxide is formed, the gate oxide covers the first conductive type well region, the drift region, and the side walls and bottom walls of the lower convex opening, and the gate oxide also covers the side walls and bottom walls of the first part of the first shallow trench isolation structure and the side walls and bottom walls of the second part of the first shallow trench isolation structure.

10. The method for forming an LDMOS device according to claim 6, wherein: The steps of forming the lower convex opening include: Forming a first patterned photoresist layer, wherein the first patterned photoresist layer covers the first conductive type well region and the drift region and exposes the first shallow trench isolation structure; Performing a first etching process, using the first patterned photoresist layer as a mask, etching a portion of the thickness of the first shallow trench isolation structure to form a first opening; forming a second patterned photoresist layer, wherein the second patterned photoresist layer covers the first conductive type well region, the drift region and a portion of the first opening and exposes a portion of the top surface of the remaining first shallow trench isolation structure; Perform a second etching process, using the second patterned photoresist layer as a mask, and etch the remaining portion of the first shallow trench isolation structure, retaining the first portion of the first shallow trench isolation structure and the second portion of the first shallow trench isolation structure at the bottom angle of the shallow trench to form a second opening, wherein the second opening exposes the bottom wall of the shallow trench, and the first opening and the second opening together constitute a downward convex opening in the shallow trench; wherein the width of the first opening is greater than the width of the second opening.

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