Semiconductor structural element and method for producing semiconductor structural element

Abstract

According to the invention, a semiconductor structure element having a semiconductor substrate is provided, the semiconductor structure element having at least one source element, at least one drain element and at least one field plate. The semiconductor structure element according to the invention is characterized in that the at least one field plate surrounds an edge of the semiconductor structure element and is in electrical contact with the drain element. According to another aspect of the invention, a method is proposed for producing a semiconductor structural element constructed according to the invention.

Description

Technical Field

[0001] The invention relates to a semiconductor component, preferably a power MOSFET component, and a method for producing a semiconductor component. Background Art

[0002] An important part of semiconductor structural elements, such as power transistors, is the edge of the component. In this area, high field strength may be formed due to symmetry breaking. For this reason, so-called edge structures or edge shielding are generally provided. Various possibilities of shielding are known from the prior art, such as B. Baliga.'s "Basics of Power Semiconductor Devices", Springer US2008, doi: 10.1007 / 978-0-387-47314-7 describes various variations. However, the edge of the component still retains a susceptible area. Electrical breakdown that usually damages the component may occur. On the contrary, if the edge is sufficiently protected, the breakdown occurs in the battery area, and ideally occurs there through the so-called avalanche breakdown in the drift region. As long as the component is avalanche-capable (such as gallium nitride trench MOSFET), the avalanche breakdown will not cause damage. Another solution for reducing the field peak is to set a field plate. This usually metal overhang is conducive to the distribution of the potential drop over a larger area and thus reduces the field strength.

[0003] Field plates and their use in semiconductor components are generally known from the prior art. These are components which are electrically insulated from active semiconductor regions, are usually short-circuited to a source electrode, and are made of an electrically conductive material, such as metal or polysilicon.

[0004] The field plates are usually arranged spatially directly adjacent to the drift region. The field plates serve to reduce the electric field peaks at the edges of the component and at the transition between the n-doped drift region and other p-doped regions, such as edge structures or channel regions. For charge compensation in the drift region and by influencing the charge carrier density in the drift region through their doping, the field plates enable a higher doping degree in the drift region, which reduces the resistance of the component in the switched-on state, but at the same time maintains a high breakdown voltage, which is necessary for safe operation of the semiconductor component. Summary of the invention

[0005] According to the present invention, a semiconductor component having a semiconductor substrate is provided, wherein the semiconductor component has at least one source component, at least one drain component and at least one field plate. The semiconductor component according to the present invention is characterized in that the at least one field plate surrounds an edge of the semiconductor component and is in electrical contact with the drain component.

[0006] The present invention therefore relates to a new way of forming a field plate which, in particular at the edges or edges of a component, leads to a more favorable field distribution with respect to avoiding electrical breakdown. This makes it possible to better utilize favorable material parameters, such as a high critical field strength, especially in the case of so-called wide bandgap semiconductors.

[0007] Unlike conventional solutions, the field plate is not at source potential, but at drain potential. This allows the field distribution in the semiconductor and in particular at the edges of the component to be better influenced. This reduces the probability of breakdown in this area and reduces the load on the passivation layer, which in turn has a positive effect on the service life of the component.

[0008] The semiconductor component may be, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The semiconductor substrate may be, for example, silicon, another semiconductor substrate or a silicon-on-insulator (SOI) substrate.

[0009] In a preferred embodiment, the semiconductor structure element may have a vertical structure. Here, the source element is constructed on the first surface of the semiconductor structure element, and the drain element is constructed on the second surface, wherein the second surface is opposite to the first surface. Here, the field plate has a first section and a second section connected to the first section, wherein the first area is formed on the first surface of the semiconductor structure element, and the second area extends along the edge area of ​​the semiconductor structure element and contacts the drain element. In other words, the field plate has a substantially L-shaped cross section. The angle between the first section and the second section can be, for example, about 90° or greater than 90°.

[0010] The field plate may be in contact with the drain element via a highly doped layer of the semiconductor substrate and / or via a metallization of the drain element.

[0011] In a preferred embodiment of the invention, the passivation layer is formed on the surface of the semiconductor component associated with the source component and on the edges of the semiconductor component, so that the passivation layer surrounds the edges of the semiconductor component. The field plate is formed on the passivation layer.

[0012] Particularly preferably, at least one doped edge structure is formed in the region of the first surface, wherein the doping of this region is different from the doping of the semiconductor substrate in particular, and wherein the first region of the field plate extends on the surface to the edge of the doped region. The field distribution can be additionally influenced by the doped edge structure. The doped edge structure preferably has a doping gradient, so that the doping decreases toward the edge of the semiconductor component.

[0013] Here, the passivation layer can be formed on the first surface so that the thickness of the passivation layer increases in the region from the edge of the semiconductor component to the edge of the doped region, and the first region of the field plate is formed on the region of the increased thickness of the passivation layer. This measure advantageously influences the field distribution.

[0014] In a preferred embodiment of the present invention, the semiconductor structure element includes a plurality of source elements, drain elements and gate elements respectively connected in parallel and a plurality of field plates.

[0015] Particularly preferably, the semiconductor component is designed as a power transistor, in particular a power MOSFET component.

[0016] According to another aspect of the present invention, a method for producing a semiconductor component constructed according to the present invention is provided. The method comprises the following steps:

[0017] a. during the production of the edge of the semiconductor structure, etching the semiconductor substrate until the highly doped layer of the semiconductor substrate in the region of the drain element,

[0018] b. depositing a passivation layer at least on the surface of the semiconductor component associated with the source element and on the edge of the semiconductor component,

[0019] c. Applying a field plate to the passivation layer such that the field plate surrounds the edges of the semiconductor component and is connected to the drain component in a low-resistance manner by means of the highly doped layer.

[0020] The field plate may preferably be applied during the source metallization.

[0021] A so-called contact metallization can additionally be deposited between the drain element and the field plate material. This contact metallization can preferably be deposited and structured together with the contact metallization of the source element.

[0022] The present invention provides in an efficient and cost-effective manner a semiconductor component which is protected against electrical breakdown in the edge region of the component and which can therefore have an increased service life and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Embodiments of the present invention are described in detail according to the accompanying drawings and the following description. The accompanying drawings show:

[0024] 1 a) to c): Cross-sections through semiconductor components known from the prior art,

[0025] Figure 2 : a cross section of a semiconductor structure according to a first embodiment of the present invention,

[0026] Figure 3 : A cross section through a semiconductor component according to a second embodiment of the present invention, wherein only an edge region of each semiconductor component is shown.

[0027] In the following description of exemplary embodiments of the present invention, identical elements are denoted by identical reference numerals, wherein a repeated description of these elements is omitted where necessary. The drawings merely schematically illustrate the content of the present invention. DETAILED DESCRIPTION

[0028] FIG. 1a) shows a cross section of an edge region of a semiconductor component 20 according to the prior art. In this example, the semiconductor component 20 comprises an n-doped semiconductor 1 with a p-doped region 2 in order to produce a blocking junction. ). These regions are contacted via the contact 5 of the drain region 15 and the contact 6 of the source region 16. In addition, there is a passivation layer 7, for example an oxide layer, on the surface 21 assigned to the source element 6. Various measures are known from the prior art to reduce the field peaks. In the example according to FIG. 1a), below the passivation layer 7 is a p-doped edge structure with a doping gradient.

[0029] 1 b), to provide so-called guard rings 40, 41, 42 below the passivation layer 7 to reduce field peaks. In the present example, these guard rings 40, 41, 42 are formed as annular p-doped regions on the surface 21 at the edge of the semiconductor component 20.

[0030] Furthermore, it is known, as shown in FIG. 1c), to provide one or more field plates 61 above the passivation layer 7 to reduce field peaks, which are electrically conductively connected to the source region 2, for example via a source contact 6. This usually metallic overhang facilitates the distribution of the potential drop over a larger spatial area and thus reduces the field strength.

[0031] Figure 2 A cross section is shown in the edge region of a semiconductor component 20 according to a first exemplary embodiment of the present invention.

[0032] In this example, the semiconductor component 20 comprises an n-doped semiconductor 1, on a first surface 21 a p-doped region 2 is formed which, together with a source contact 6, forms a source element 16 of the semiconductor component 20. In the region of a second surface 22 opposite the first surface 21, a highly n-doped semiconductor layer 9 is formed which is covered by a metal layer, a drain contact 5. The highly n-doped semiconductor layer 9 and the drain contact 5 form a drain element 15 of the semiconductor component 20. A passivation layer 7 is located on the surface 21 which is associated with the source element 16 and is adjacent to the source contact 6. The semiconductor component 20 also has a p-doped edge structure 3 with a doping gradient.

[0033] During the production of the edge 8 of the semiconductor component 20, the so-called Mesa edge, all except the highly n-doped layer 9 in the region of the drain contact 5 are etched away. After the deposition of the passivation layer 7, the field plate 10 is also produced during the source metallization process, which surrounds the edge 18 of the semiconductor component 20. The field plate 10 is connected to the drain contact 5 in a low-impedance manner via the highly doped semiconductor 9 and covers the edge 8 of the semiconductor component 20 separately from the passivation layer 7. The field plate 10 comprises a first section 11 which is substantially parallel to the first surface 21 of the semiconductor component 20. The field plate 10 surrounds the edge 18 of the semiconductor component 20 and comprises a second section 12 which extends along the edge 8 of the semiconductor component 20 and contacts the drain element 15. On the front side of the semiconductor component 20, the field plate 10 is bent over and thus surrounds the edge 18 of the semiconductor component 20, the first section 11 of the field plate extending, for example, to the outer edge 13 of the p-doped edge structure 3 of the semiconductor component 20. As a result, the drain potential advantageously acts on all semiconductor regions beside and below the field plate 10 , and the potential profile toward the p-doped edge structure 3 can be influenced by the overhang of the field plate and the thickness of the passivation layer 7 .

[0034] Figure 3 FIG. 2 shows a cross section of an edge region of a semiconductor structure 20 according to a second embodiment of the present invention. Figure 2 In a variant of , the semiconductor structure 20 comprises a passivation layer 7 which, on a surface 21 assigned to the source element 16, has a region 17 of increased thickness starting from the edge 8 in the region of the edge 8. The region 17 of increased thickness of the passivation layer 7 is approximately flush with the outer edge 13 of the p-doped edge structure 3. The first section 11 of the field plate 10 is formed on the region 17. Therefore, in the present example, the angle between the first section 11 and the second section 12 of the field plate is greater than 90°.

[0035] Furthermore, the strength of the field plate or its compensating influence on the electric field in the semiconductor and at the transition from the semiconductor to the passivation depends largely on the spatial distance. The embodiment shown here increases the influence of the field plate on the edge continuously and angle-dependently (steeper = faster). This provides greater freedom for optimizing the field distribution.

Claims

1. A semiconductor structure (20) having a semiconductor substrate (1), comprising at least one source element (16), at least one drain element (15) and at least one field plate (10), characterized in that: The at least one field plate (10) surrounds an edge (18) of the semiconductor component (20), and the field plate (10) is in electrical contact with the drain element (5).

2. The semiconductor structure (20) according to claim 1, wherein: The semiconductor structure (20) has a vertical structure, wherein the source element (16) is constructed on a first surface (21) of the semiconductor structure (20), and the drain element (15) is constructed on a second surface (22), wherein the second surface (22) is opposite to the first surface, and wherein the field plate has a first section (11) and a second section (12) connected to the first section (11), wherein the first section (11) is formed on the surface (21) of the semiconductor structure (20), and the second section (12) extends along an edge (8) of the semiconductor structure (20) and contacts the drain element (5).

3. The semiconductor component (20) according to claim 1, wherein: The field plate (10) is in contact with the drain element (5) through the highly doped layer (9) and / or the drain metallization portion (5) of the semiconductor substrate (1).

4. The semiconductor component (20) according to claim 1, wherein: At least one passivation layer (7) is formed on a first surface (21) of the semiconductor component (20) associated with the source element (16) and on an edge (8) of the semiconductor component (20), wherein the field plate (10) is formed on the passivation layer (7).

5. The semiconductor component (20) according to any one of claims 2 to 4, wherein: In the region of the first surface (21), at least one doped edge structure (3) is formed in the semiconductor substrate (1), wherein the doping of the edge structure (3) is in particular different from the doping of the semiconductor substrate (1), and wherein the first region (11) of the field plate (10) extends on the surface (21) as far as an outer edge (13) of the doped edge structure (3).

6. The semiconductor structure (20) according to claim 5, wherein: The thickness of the passivation (7) on the first surface (21) increases in a region (17) starting from an edge (18) of the semiconductor structure (20) to an edge of the doped region (3), and a first region (11) of the field plate (10) is formed on the region (17) of the passivation (7).

7. The semiconductor component (20) according to claim 1, wherein: The semiconductor structure element (20) comprises a plurality of source elements (16), drain elements (15) and gate elements respectively connected in parallel, and a plurality of field plates (10).

8. The semiconductor component (20) according to claim 1, wherein: The semiconductor component is designed as a power transistor, in particular as a power MOSFET component.

9. A method for producing a semiconductor component (20), in particular a semiconductor component (20) according to any one of claims 1 to 8, comprising the following steps: a. during the production of an edge (8) of a semiconductor structure (20) having an edge (18), etching the semiconductor substrate (1) up to a highly doped layer (9) of the semiconductor substrate (1) in the region of the drain element (15), b. depositing a passivation layer (7) at least on a surface (21) of the semiconductor component (20) associated with the source element (16) and on an edge (8) of the semiconductor component (20), c. In particular, during source metallization, a field plate (10) is applied to the passivation layer (7) so that the field plate (10) surrounds an edge (18) of the semiconductor structure (20) and is connected to the drain element (15) in a low-impedance manner by means of the highly doped layer (9).

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