Method for forming embedded source-drain region

Abstract

The invention provides a method for forming an embedded source-drain region. The method comprises the following steps of: covering a semiconductor layer and a gate stack structure to form a sacrificial layer; covering the side wall of the gate stack structure with a sacrificial layer to form an auxiliary side wall; and covering the first device region with a patterned mask layer, etching the second device region by taking the auxiliary side wall and the sacrificial layer as masks to form a sigma trench extending to enter the lower part of the gate stack structure, and simultaneously thinning the sacrificial layer covering the top surface of the gate stack structure of the second device region. According to the forming method, the etching loss of the gate stack structure of the corresponding device region can be reduced, the height difference of the isolation side walls between the PMOS region and the NMOS region is reduced or eliminated, the influence of different etching loads on the subsequent process is avoided, and the process stability is improved on the premise that the process cost and the process complexity are not improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing; in particular, to a method for forming an embedded source / drain region. Background Art

[0002] In the field of semiconductor integrated circuit manufacturing technology, with the development of semiconductor technology, the characteristic dimensions of various semiconductor devices are constantly decreasing, and the requirements for the performance of semiconductor devices are getting higher and higher. However, with the increasing integration of CMOS technology and the shrinking of key dimensions, the stress-lifting method used in the traditional CMOS process has been difficult to meet the needs of high-performance devices, especially from the technology node below 40nm, a larger driving current is required to improve the response speed of the circuit. In order to improve the driving current of NMOS and / or PMOS, a wafer with a crystal orientation is generally used, and different stresses are applied to the channel to improve the performance of NMOS and PMOS field effect tubes respectively. However, due to the different process steps for NMOS and PMOS, different degrees of etching loads on the top surface of the gate stack structure between NMOS and PMOS will be caused, resulting in a height difference. Additional processes need to be introduced later to solve the above problems, otherwise it will affect the execution of the replacement gate process.

[0003] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology part of the present application. Summary of the invention

[0004] In view of the shortcomings of the prior art mentioned above, the object of the present invention is to provide a method for forming an embedded source and drain region, so as to solve the problem that in the existing process of forming a sigma trench, stress source and drain regions are introduced separately or individually in the NMOS and PMOS regions, so that the top surfaces of the gate stack structures in the NMOS and PMOS regions are subjected to different degrees of etching damage, resulting in a height difference between the gate stack structures or the isolation side walls of the two regions, affecting the subsequent replacement gate process.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides a method for forming an embedded source and drain region, comprising the following steps:

[0006] A substrate is provided, on which a semiconductor layer is formed, the semiconductor layer includes a first device region and a second device region separated from each other, a gate stack structure is formed on the first device region and the second device region respectively, the gate stack structure includes a dummy gate and a gate hard mask layer;

[0007] forming a first isolation spacer on the sidewall of the gate stack structure;

[0008] Covering the semiconductor layer and the gate stack structure to form a sacrificial layer;

[0009] forming an auxiliary spacer on the sacrificial layer at the sidewall of the gate stack structure to define the boundary of the sigma trench to be formed;

[0010] The first device region is covered with a patterned mask layer, and the second device region is etched using the auxiliary sidewall and the sacrificial layer as a mask to form a sigma trench extending into the bottom of the gate stack structure, and the sacrificial layer covering the top surface of the gate stack structure in the second device region is thinned;

[0011] A stressed source and drain region is grown in the sigma trench.

[0012] Optionally, the step of forming the patterned mask layer includes: forming a polysilicon material layer covering the semiconductor layer and the gate stack structure; defining a photoresist pattern that exposes the second device area through a photolithography process; and dry etching the polysilicon material layer based on the photoresist pattern.

[0013] Optionally, the step of forming the auxiliary sidewall includes: forming a sidewall material layer on the sacrificial layer; anisotropically etching the sidewall material layer to remove the sidewall material layer covering the semiconductor layer and the top surface of the gate stack structure, thereby forming an auxiliary sidewall located on the sidewall of the gate stack structure.

[0014] Optionally, the step of forming the sacrificial layer includes: using a chemical vapor deposition process to conformally deposit a sacrificial layer on the gate stack structure and the semiconductor layer; wherein the thickness of the sacrificial layer is to The sacrificial layer is a silicon oxide sacrificial layer.

[0015] Optionally, after the step of forming the stress source drain region, the method further comprises: removing the remaining sacrificial layer and the auxiliary sidewall spacer by a wet etching process, wherein the wet etching process is performed using diluted hydrofluoric acid.

[0016] Optionally, the step of forming the gate stack structure includes sequentially forming a high dielectric constant gate dielectric layer, a work function adjustment layer and a dummy gate; wherein the material of the dummy gate includes one of polysilicon and amorphous silicon.

[0017] Optionally, one of the first device region and the second device region is a PMOS region, and the other is an NMOS region.

[0018] Optionally, the first device region is an NMOS region, the second device region is a PMOS region, and the step of forming the stress source drain region includes: growing a SiGe epitaxial layer through an epitaxial process, and simultaneously in-situ doping the SiGe epitaxial layer; wherein the epitaxial process includes a reduced pressure chemical vapor deposition process.

[0019] Optionally, the step of forming the sigma groove includes: using the auxiliary sidewall and the sacrificial layer as masks, anisotropically etching the N-type well region through a dry etching process to form an initial groove; then, selectively etching based on the initial groove through a wet etching process to form a sigma groove; wherein the wet etching process is performed using a TMAH solution.

[0020] The present invention also provides a method for forming a semiconductor structure, comprising the following steps: according to the aforementioned method for forming an embedded source and drain region; removing the remaining sacrificial layer and the auxiliary sidewall; forming a second isolation sidewall outside the first isolation sidewall.

[0021] As described above, the present invention provides a method for forming an embedded source and drain region. Before forming an auxiliary sidewall for defining the boundary of a sigma trench, a sacrificial layer is formed by covering the gate stack structure and the semiconductor layer. This can reduce the etching loss of the gate stack structure of the corresponding device area caused by the etching process sequence of the sigma trench, thereby reducing or eliminating the height difference of the isolation sidewall between the PMOS and NMOS regions, avoiding the influence of different etching loads on subsequent processes, and improving the process stability without increasing the process cost and process complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1A to Figure 1D Schematic diagram showing the structures obtained at different stages of the method for forming an embedded silicon germanium device according to a comparative example of the present invention.

[0023] Figure 2 Shown is a flow chart of a method for forming an embedded silicon germanium device according to an embodiment of the present invention.

[0024] Figure 3A to Figure 3I Schematic diagrams showing structures obtained at different stages of a method for forming a gate stack structure according to an embodiment of the present invention.

[0025] Component number description

[0026] 1.10 Semiconductor layer

[0027] 2.20 Isolation Structure

[0028] 11, 110 N-type well region

[0029] 12, 120 P-type well region

[0030] 3. 30a, 30b Gate stack structure

[0031] 4.40 Source and drain regions

[0032] 310 High dielectric constant gate dielectric layer

[0033] 320 Work function adjustment layer

[0034] 33, 330 Dummy gate

[0035] 34, 340 Gate hard mask layer

[0036] 5 Isolation side wall

[0037] 50 First isolation side wall

[0038] 350 Sacrificial Layer

[0039] 360 Auxiliary Side Wall

[0040] 6 Patterned Hard Mask Layer

[0041] 60 Polysilicon layer

[0042] 221, 2210 Initial groove

[0043] 22, 220 Sigma Groove

[0044] Steps S1~S4, S100~S600 DETAILED DESCRIPTION

[0045] Hereinafter, the embodiments of the present invention are described by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. For the purpose of clarity, parts and steps familiar to those skilled in the art are omitted to avoid unnecessary confusion of the elements of the present invention.

[0046] For ease of description, spatially relative terms such as "under," "below," "below," "below," "above," "on," etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0047] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0048] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0049] The comparative example of the present invention provides a method for forming an embedded source and drain region, which may include:

[0050] Step S1, providing a substrate, on which a semiconductor layer is formed, the semiconductor layer comprising a first device region and a second device region separated from each other, a gate stack structure being formed on the first device region and the second device region respectively, the gate stack structure comprising a dummy gate and a gate hard mask layer;

[0051] Step S2, forming an isolation spacer on the sidewall of the gate stack structure;

[0052] Step S3, covering the first device region with a patterned mask layer, and etching the second device region using the isolation sidewall and the gate stack structure as masks to form a sigma trench extending into a bottom of the gate stack structure;

[0053] Step S4, growing a stress source and drain region in the sigma trench.

[0054] Figure 1A and Figure 1D Shown is a schematic diagram of the structure obtained before and after etching the high dielectric constant gate dielectric layer during the manufacturing process of the gate stack structure of the comparative example.

[0055] In step S1, the semiconductor layer includes a separated PMOS region and an NMOS region, such as Figure 1A As shown, an isolation structure 2 is extended inward from the surface of the semiconductor layer, and an N-type well region 11 and a P-type well region 12 are separated by the isolation structure. A gate stack structure 3 is formed on the N-type well region 11 and the P-type well region 12, and the gate stack structure 3 includes a dummy gate 33 and a gate hard mask layer 34.

[0056] In step S2 , an isolation spacer 5 is formed on the sidewall of the gate stack structure.

[0057] like Figure 1BAs shown, in step S3, the patterned mask layer includes a patterned hard mask layer, and the patterned hard mask layer acts as a barrier layer to prevent the NMOS region from being exposed to the etchant during the etching process of the sigma groove; wherein the hard mask layer can be a silicon nitride hard mask layer. In the above step of forming the patterned hard mask layer, the silicon nitride hard mask layer covering the N-type well region is removed by an anisotropic etching process, and the silicon nitride hard mask layer covering the top surface of the gate stack structure is removed synchronously, so that there are different degrees of etching loss between the hard mask layers covering the top surfaces of the gate stack structures of the NMOS and PMOS.

[0058] like Figure 1C and Figure 1D As shown, in step S3, the step of forming the sigma trench 22 includes: forming initial trenches 221 located on both sides of the gate stack structure by an anisotropic etching process based on the patterned hard mask layer 6; and selectively etching the initial trenches 221 by a wet etching process. Figure 1C As shown, dry etching of the N-type well region 11 based on the patterned hard mask layer 6 will simultaneously sacrifice a portion of the isolation sidewall and consume the gate hard mask layer above the dummy gate. Figure 1D As shown, after the dry etching process is performed, there are different height differences between the gate stack structures located above the N-type well region and the P-type well region, and correspondingly there are height differences between the isolation sidewalls 5 on the sidewalls of the gate stack structures of NMOS and PMOS.

[0059] In step S4, a stress source and drain region is grown in the sigma trench by a selective epitaxial process. In order to improve the carrier mobility of the channel region, stress source and drain regions of NMOS and PMOS are introduced respectively, or a stress source and drain region of PMOS is introduced alone; wherein, the stress source and drain region introduced in the N-type well region can be a SiGe epitaxial layer, and the stress source and drain region introduced in the P-type well region can be a SiC epitaxial layer.

[0060] In addition, after the step of forming the stress source drain region in step S4, the silicon nitride hard mask layer remaining in the PMOS region can be removed by phosphoric acid, but the above method has shortcomings: when the feature size is below 28nm, the polysilicon gate used as a dummy gate needs to be removed by a replacement gate process to form a metal gate electrode and an optional work function metal layer. Due to the different formation processes of the NMOS and PMOS regions, there is a height difference between the first isolation sidewall of the gate stack structure sidewall of the NMOS and PMOS and the second isolation sidewall outside thereof, which not only increases the process difficulty of the subsequent replacement gate process, but also may introduce a risk of damage between the isolation sidewall and the gate electrode, affecting the reliability of the device.

[0061] Compared with the above-mentioned manufacturing method of embedded source and drain regions, the present invention introduces a sacrificial layer before the step of defining the sigma trench boundary to protect the top surface of the gate stack structure from etching loss caused by the process sequence of embedded source and drain regions. The sacrificial layer is removed by an etchant without adding an additional removal step, thereby avoiding the different etching loads of the gate stack structure affecting subsequent processes, and improving its process stability without increasing the process cost and process complexity.

[0062] Hereinafter, the method for forming the embedded source and drain regions of the present invention will be specifically described in conjunction with the accompanying drawings.

[0063] See also Figure 2 , this embodiment provides a method for forming an embedded source and drain region.

[0064] First, step S100 is performed to provide a substrate, on which a semiconductor layer is formed, the semiconductor layer includes a first device region and a second device region separated, a gate stack structure is formed on the first device region and the second device region respectively, and the gate stack structure includes a dummy gate and a gate hard mask layer.

[0065] Specifically, the substrate may be a semiconductor material or an insulating material, and the material of the semiconductor layer 10 may be selected, for example, one of silicon, germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenide, silicon carbide, zinc oxide, gallium oxide, and indium phosphide. Various doping regions are also formed in the semiconductor layer 10 to form necessary parts or structures of semiconductor devices, the isolation structure is, for example, a shallow trench isolation structure (STI), and the doping region is, for example, a lightly doped source and drain region (LDD). The above structure is determined according to the actual semiconductor device manufacturing process, and is well known to those skilled in the art, and will not be repeated here.

[0066] One of the first device region and the second device region is an NMOS region, and the other is a PMOS region; when the first device region is an NMOS region, the stress source drain region to be formed is a SiGe epitaxial layer; when the first device region is an NMOS region, the stress source drain region to be formed is a SiC epitaxial layer.

[0067] like Figure 3AAs shown, the semiconductor layer 10 includes an N-type well region 110 and a P-type well region 120 separated by an isolation structure, a PMOS gate stack structure 30a is formed on the N-type well region 110, and an NMOS gate stack structure 30b is formed on the P-type well region 120. In this embodiment, the steps of forming the gate stack structures 30a and 30b include sequentially forming a high dielectric constant (k) gate dielectric layer 310, a work function adjustment layer 320, a dummy gate 330, and a retained gate hard mask layer 340; wherein the material of the dummy gate 330 includes one of polycrystalline silicon, amorphous silicon, and microcrystalline silicon, and the gate hard mask layer 340 is a single layer composed of one of silicon oxide, silicon nitride, and silicon oxynitride, or a stack of multiple layers.

[0068] In some examples, the step of forming the high-k gate dielectric layer 310 includes: depositing the high dielectric constant material layer by a high-density plasma chemical vapor deposition (HDPCVD) process, an atomic layer deposition (ALD) or a similar process, wherein the material of the high dielectric constant material layer can be selected from materials suitable for making a high dielectric constant gate dielectric layer, including but not limited to metal oxides of the subgroup or lanthanide series, such as HfO2, CeO2, Y2O3, La2O; nitride oxides, such as SiON, AlON, TiON.

[0069] Next, step S200 is performed to form a first isolation spacer on the sidewall of the gate stack structure.

[0070] Specifically, a first isolation spacer is formed simultaneously on the sidewalls of the gate stack structure in the first device region and the second device region.

[0071] Continue to see Figure 3A At step S200, the step of forming the first isolation spacer 50 includes: forming a first spacer material layer covering the gate stack structure and the semiconductor layer, wherein the material of the first spacer material layer includes SiO x 、SiN x 、SiN x O y One of the following: removing the first spacer material layer covering the gate stack structure and the semiconductor layer by an anisotropic etching process, such as Figure 3A As shown, the top surface of the obtained first isolation spacer is flush with the top surface of the gate stack structure.

[0072] In step S200 of this embodiment, after the step of forming the first isolation spacer 50 , ion implantation is performed on the N-type well region 110 and the P-type well region 120 respectively to pre-form source and drain regions 40 on both sides of the gate stack structure.

[0073] Next, step S300 is performed to form a sacrificial layer covering the semiconductor layer and the gate stack structure.

[0074] Specifically, at step S300, Figure 3B As shown, the sacrificial layer 350 is formed to cover the gate stack structure and the semiconductor layer.

[0075] In some examples, the sacrificial layer 350 can be formed by chemical vapor deposition, such as PETEOS, PECVD, or deep aspect ratio subatmospheric pressure chemical vapor deposition. In a specific example, the sacrificial layer 350 can be a silicon oxide sacrificial layer with a thickness of to

[0076] Next, step S400 is performed to form an auxiliary spacer on the sacrificial layer at the sidewall of the gate stack structure to define the boundary of the sigma trench to be formed.

[0077] For some examples, see FIG. 3C to FIG. 3D The specific steps of forming the auxiliary sidewall 360 are as follows: forming a second sidewall material layer 3600; then, removing a portion of the second sidewall material layer by an anisotropic etching process, and retaining the second sidewall material layer covering the sidewall of the gate stack structure to form an auxiliary sidewall 360 for defining the boundary of the sigma trench; wherein the second sidewall material includes silicon nitride.

[0078] In step S400 of this embodiment, the material of the auxiliary spacer 360 includes silicon nitride, and the second spacer material layer 3600 can be formed by, for example, a reactive sputtering process, a thermal chemical vapor deposition (CVD) process, or a plasma enhanced chemical vapor deposition (PECVD) process.

[0079] Then, step S500 is performed to cover the first device area with a patterned mask layer, and the second device area is etched using the auxiliary sidewall and the sacrificial layer as a mask to form a sigma trench extending into the bottom of the gate stack structure. At the same time, the sacrificial layer covering the top surface of the gate stack structure covering the second device area is thinned.

[0080] Specifically, after step S400, a patterned mask layer is formed, the first device area is covered with the patterned mask layer, and the second device area, the auxiliary side wall and a portion of the sacrificial layer are exposed, and the patterned mask layer acts as a barrier layer to shield the first device area in the subsequent etching process.

[0081] Depending on the situation, the patterned mask layer may be a photoresist pattern, or a polysilicon layer covering the first device region obtained by etching based on the photoresist pattern. In step S400 of this embodiment, the patterned mask layer is selected to be a polysilicon layer formed by a patterning process including a photolithography process, and the photoresist remaining on the surface of the polysilicon layer is removed after the patterning process, and the remaining polysilicon layer serves as a barrier layer for shielding the first device region.

[0082] Some examples include Figures 3E to 3G The steps of forming the patterned mask layer include: forming a polysilicon material layer covering the semiconductor layer 10 and the gate stack structures 30a and 30b; defining a photoresist pattern on the polysilicon material layer 600 to expose the second device area through a photolithography process; and performing dry etching based on the photoresist pattern to form a polysilicon layer 60 covering the first device area.

[0083] like FIG. 3H to FIG. 3I The sigma groove 220 is formed by performing a series of etching processes, including the following steps: using the gate stack structure and the auxiliary sidewalls of the sidewalls as masks, etching the N-type well region 110 by an anisotropic etching process to form initial grooves 2210 located on both sides of the gate stack structure; and selectively etching the initial grooves 2210 by a wet etching process.

[0084] At step S500, the dry etching process is performed using a mixed gas containing two or more halogen elements, the halogen gas is used as an etching gas, which includes, for example, a gas containing fluorine, chlorine, or bromine, and the mixed gas also includes a carrier gas, such as one of N2, Ar, and He, for improving the removal effect and improving the removal efficiency. Preferably, the dry etching can be performed by reactive ion etching (RIE) or plasma etching process, which includes the following steps: using a remote plasma generator to generate reactive free radicals and ion species from the above-mentioned etching gas and carrier gas, and guiding them into the process chamber.

[0085] In this embodiment, the anisotropic etching process is performed using an inductively coupled plasma etching device, and the morphology of the initial groove 2210 obtained can be seen in Figure 3HThe process parameters of the etching process include: introducing the etching gas into the process chamber under the condition of a chamber pressure between 1mTorr and 50mTorr, wherein the etching gas includes CF4, HBr and Cl2; during the entire etching process, the bias power applied is 100W-1000W. In step S400 of this embodiment, the first device region is covered with a polysilicon layer, and the anisotropic etching process is performed using the above-mentioned etching gas ratio, so that the etching selectivity of the polysilicon layer relative to the silicon oxide sacrificial layer is improved, and the polysilicon layer covering the first device region can be completely removed in the wet etching process of the sigma groove.

[0086] In a specific example, the dry etching process is performed in situ using an inductively coupled plasma etching device, and the etching gas is introduced into the process chamber at the following flow rates: CF4 flow rate 20-200sccm, HBr flow rate 50-500sccm and Cl2 flow rate 50-500sccm.

[0087] Furthermore, an alkaline etchant may be used to perform the wet etching process, and the wet etching process has anisotropy, for example, a tetramethylammonium hydroxide (TMAH) solution is used to perform the wet etching process. Since a semiconductor layer with a (110) crystal plane is selected to make PMOS, the semiconductor layer with a (110) crystal plane is selectively etched using a TMAH solution. <100> right <111> The etching selectivity ratio makes the wet etching process finally stop at <111> The resulting sigma groove has Fig. 3I The shape shown.

[0088] In some examples, after the step of forming the sigma trench, the surface of the sigma trench is wet cleaned using SPM and SC1, wherein the SPM solution includes H2SO4 and H2O2, and the SC1 solution includes NH4OH and H2O2.

[0089] Compared with the comparative example, after the initial groove etching step is performed in the present scheme, since the dry etching process for forming the initial groove is anisotropic etching, not only silicon will be etched, but also the sacrificial layer covering the top surface of the gate stack structure of the PMOS will be etched, so that the sacrificial layer is thinned. This effectively avoids etching loss on the isolation side wall and the top surface of the gate stack structure, thereby ensuring that after the sacrificial layer is removed, there is no obvious height difference between the gate stack structures of the PMOS region and the NMOS region.

[0090] Then, step S600 is performed to grow a stress source and drain region in the sigma trench.

[0091] At step S600, the step of forming the stress source and drain region includes: growing a SiGe epitaxial layer by an epitaxial process, and simultaneously in-situ doping the SiGe epitaxial layer, wherein the epitaxial process includes a reduced pressure chemical vapor deposition (RPCVD) process.

[0092] When the sacrificial layer is a silicon oxide sacrificial layer, after the step of forming the stress source and drain region, the remaining sacrificial layer and the auxiliary sidewalls can be removed together with diluted hydrofluoric acid without adding an additional removal process.

[0093] This embodiment also provides a method for forming a semiconductor structure, comprising the following steps: the aforementioned method for forming an embedded source and drain region; removing the remaining sacrificial layer and the auxiliary sidewall; and forming a second isolation sidewall outside the first isolation sidewall.

[0094] Specifically, after removing the remaining sacrificial layer and the auxiliary sidewall, Figure 3H As shown, the overall heights of the gate stack structures 30a and 30b of NMOS and PMOS are basically the same. By sequentially performing a deposition process of a third sidewall material and an anisotropic etching process, a second isolation sidewall is synchronously formed outside the first isolation sidewall of the PMOS region and the NMOS region.

[0095] Furthermore, after the step of forming the second isolation sidewall, the deposition of the contact hole etching stop layer and the interlayer dielectric film, the planarization process, and the replacement gate process are sequentially performed, wherein the step of the planarization process is performed by a chemical mechanical polishing process (CMP), which is well known to those skilled in the art and will not be described in detail here. After the embedded source and drain regions are formed based on the above technical solution, there is almost no height difference between the gate stack structures of the NMOS and the PMOS, and the chemical mechanical polishing process performed before the replacement gate process can be reduced from multiple steps to one.

[0096] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for forming an embedded source and drain region, characterized in that: The following steps are involved: A substrate is provided, on which a semiconductor layer is formed, the semiconductor layer includes a first device region and a second device region separated, a gate stack structure is formed on the first device region and the second device region respectively, the gate stack structure includes a dummy gate and a gate hard mask layer; forming a first isolation spacer on the sidewall of the gate stack structure; Covering the semiconductor layer and the gate stack structure to form a sacrificial layer; forming an auxiliary spacer on the sacrificial layer at the sidewall of the gate stack structure to define the boundary of the sigma trench to be formed; The first device region is covered with a patterned mask layer, and the second device region is etched using the auxiliary sidewall and the sacrificial layer as a mask to form a sigma trench extending into the bottom of the gate stack structure, and the sacrificial layer covering the top surface of the gate stack structure in the second device region is thinned; A stressed source and drain region is grown in the sigma trench.

2. The method for forming an embedded source and drain region according to claim 1, characterized in that: The step of forming the patterned mask layer includes: forming a polysilicon material layer covering the semiconductor layer and the gate stack structure; defining a photoresist pattern that exposes the second device area through a photolithography process; and dry etching the polysilicon material layer based on the photoresist pattern.

3. The method for forming an embedded source and drain region according to claim 1, wherein: The step of forming the auxiliary sidewall includes: forming a sidewall material layer on the sacrificial layer; anisotropically etching the sidewall material layer to remove the sidewall material layer covering the semiconductor layer and the top surface of the gate stack structure, thereby forming an auxiliary sidewall located on the sidewall of the gate stack structure.

4. The method for forming an embedded source-drain region according to claim 1 or 3, characterized in that: The step of forming the sacrificial layer comprises: using a chemical vapor deposition process to conformally deposit a sacrificial layer on the gate stack structure and the semiconductor layer; wherein the thickness of the sacrificial layer is to The sacrificial layer is a silicon oxide sacrificial layer.

5. The method for forming an embedded source and drain region according to claim 4, characterized in that: After the step of forming the stress source drain region, the method further comprises: removing the remaining sacrificial layer and the auxiliary sidewall spacer by a wet etching process, wherein the wet etching process is performed using diluted hydrofluoric acid.

6. The method for forming an embedded source and drain region according to claim 1, characterized in that: The step of forming the gate stack structure includes sequentially forming a high dielectric constant gate dielectric layer, a work function adjustment layer and a dummy gate; wherein the material of the dummy gate includes one of polysilicon and amorphous silicon.

7. The method for forming an embedded source and drain region according to claim 1, characterized in that: One of the first device region and the second device region is a PMOS region, and the other is an NMOS region.

8. The method for forming an embedded source and drain region according to claim 2, wherein: The first device region is an NMOS region, the second device region is a PMOS region, and the step of forming the stress source drain region includes: growing a SiGe epitaxial layer by an epitaxial process, and simultaneously in-situ doping the SiGe epitaxial layer; wherein the epitaxial process includes a reduced pressure chemical vapor deposition process.

9. The method for forming an embedded source and drain region according to claim 7, characterized in that: The step of forming the sigma groove includes: using the auxiliary sidewall and the sacrificial layer as masks, anisotropically etching the N-type well region through a dry etching process to form an initial groove; then, selectively etching based on the initial groove through a wet etching process to form a sigma groove; wherein the wet etching process is performed using a TMAH solution.

10. A method for forming a semiconductor structure, characterized in that: The following steps are involved: The method for forming an embedded source-drain region according to any one of claims 1 to 9; The remaining sacrificial layer and the auxiliary sidewall are removed; and a second isolation sidewall is formed outside the first isolation sidewall.

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