Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, and the method comprises the following steps: providing a substrate, forming a gate structure on the substrate, and forming a drain doped region and a source doped region in the substrate at two sides of the gate structure; epitaxial layers are formed on the substrate of the source doped region and the drain doped region, the epitaxial layers are metalized to form a conductive contact layer, and the surface of the conductive contact layer is flush with the surface of the gate structure; an interlayer dielectric layer is formed on the conductive contact layer and the gate structure, a conductive contact hole is formed in the interlayer dielectric layer, and the conductive contact hole penetrates through the interlayer dielectric layer and makes contact with the conductive contact layer and the gate structure so that the gate structure, the source electrode and the drain electrode can be located on the same horizontal plane, the process difficulty of a contact hole photoetching and etching process can be reduced, and the problems occurring in contact hole etching are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a preparation method thereof. Background Art

[0002] In the logic circuit manufacturing process, after the gate structure is formed on the substrate, a metal silicide layer is formed on the surface of the source region S, the drain region D and the gate G, and the SPT (stress proximity process) process is performed to reduce the width of the sidewalls on both sides of the gate G in the lateral direction, and finally a contact hole CT is formed. Figure 1 As shown. However, as the process requirements continue to shrink, the CD (line width) size of the contact hole CT is getting smaller and smaller, which makes the process of etching the contact hole CT more and more difficult, and contact hole CT etching problems often occur on the active area (AA), such as the contact hole CT open circuit (the contact hole CT cannot be connected to the source area S, drain area D or gate G in the MOS tube), thereby affecting the yield, such as Figure 2 shown. Summary of the invention

[0003] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can reduce the process difficulty of contact hole lithography and etching processes and solve the problems that occur in contact hole etching.

[0004] In order to solve the above problems, the present invention provides a method for preparing a semiconductor device, comprising the following steps: Providing a substrate, on which a gate structure is formed, and in which a drain doping region and a source doping region are respectively formed in the substrate on both sides of the gate structure; Forming an epitaxial layer on the substrate of all the source doping regions and the drain doping regions, and metalizing the epitaxial layer to form a conductive contact layer, wherein the surface of the conductive contact layer is flush with the surface of the gate structure; An interlayer dielectric layer is formed on the conductive contact layer and the gate structure, and a plurality of conductive contact holes are formed in the interlayer dielectric layer, all of which penetrate the interlayer dielectric layer and contact the conductive contact layer and the gate structure respectively.

[0005] Optionally, the gate structure includes a gate oxide layer, a polysilicon gate and a side wall, the gate oxide layer is located on the surface of the substrate, the polysilicon gate is stacked on the gate oxide layer, and the side wall is located on both sides of the gate oxide layer and the polysilicon gate and covers the side walls of the gate oxide layer and the polysilicon gate.

[0006] Furthermore, the specific method of forming the conductive contact layer is: Measuring the height of the gate structure by an optical critical dimension measurement process, wherein the height of the gate structure is the total height of the gate oxide layer and the polysilicon gate; An epitaxial layer is formed on the substrate of the source doping region and the substrate of the drain doping region through an epitaxial process, and a polysilicon epitaxial structure is formed on the surface of the polysilicon gate, wherein the height of the epitaxial layer is the same as the height of the gate structure; converting the epitaxial layer and the polysilicon epitaxial structure into a metal silicide layer; The substrate is planarized so that the metal silicide layer on the polysilicon gate, the metal silicide layer above the source doping region, and the metal silicide layer above the drain doping region are on the same level.

[0007] Furthermore, when the metal silicide layer is formed, the thickness of the metal silicide layer on the substrate of the source doping region and the drain doping region is smaller than the thickness of the metal silicide layer on the polysilicon gate.

[0008] Furthermore, the gate structure also includes a hard mask layer, and the hard mask layer covers the polysilicon gate.

[0009] Furthermore, the specific method of forming the conductive contact layer is: Measuring the height of the gate structure by an optical critical dimension measurement process, wherein the height of the gate structure is the total height of the gate oxide layer and the polysilicon gate; Forming an epitaxial layer on the substrate of the source doping region and on the substrate of the drain doping region through an epitaxial process, wherein the height of the epitaxial layer is the same as the height of the gate structure; Planarizing the substrate to expose the polysilicon gate and make the polysilicon gate and the epitaxial layer be on the same level; Performing a metal element implantation process on the epitaxial layer close to the substrate side; A portion of the thickness of the epitaxial layer away from the substrate side and a portion of the thickness of the polysilicon gate are converted into a metal silicide layer, wherein the metal element injection position is located below the metal silicide layer.

[0010] Furthermore, the metal element is at least one of magnesium, calcium and barium, and the doping concentration of the metal element is greater than or equal to 1×10 21 atoms / cm 3 .

[0011] Furthermore, the specific method of forming the conductive contact hole is: forming an etch stop layer, an interlayer dielectric layer, a pattern transfer layer and a patterned photoresist layer in sequence on the metal silicide layer; Using the patterned photoresist layer as a mask, sequentially etching the pattern transfer layer, the interlayer dielectric layer and the etching stop layer, exposing the metal silicide layer, and forming a transition trench at the same time; removing the photoresist layer and the pattern transfer layer and exposing the interlayer dielectric layer to form a second trench; A conductive contact hole is formed in the second trench.

[0012] On the other hand, the present invention also provides a semiconductor device, including a substrate, a gate structure formed on the substrate, a drain doping region and a source doping region are respectively formed in the substrate on both sides of the gate structure, a conductive contact layer is formed on the substrate of all the source doping regions and the drain doping regions, an interlayer dielectric layer is formed on the conductive contact layer and the gate structure, and a plurality of conductive contact holes are formed in the interlayer dielectric layer, all the conductive contact holes penetrate the interlayer dielectric layer and are in contact with the conductive contact layer and the gate structure, respectively, wherein the conductive contact layer includes a metal silicide layer.

[0013] Optionally, the conductive contact layer further includes an epitaxial layer, the epitaxial layer is located between the metal silicide layer and the substrate, and the epitaxial layer is doped with metal elements.

[0014] Compared with the prior art, the present invention has the following unexpected technical effects: The present invention provides a semiconductor device and a method for preparing the same. The method for preparing the semiconductor device comprises the following steps: providing a substrate, on which a gate structure is formed, and drain doping regions and source doping regions are respectively formed in the substrate on both sides of the gate structure; forming an epitaxial layer on the substrate of all the source doping regions and drain doping regions, and metalizing the epitaxial layer to form a conductive contact layer, wherein the surface of the conductive contact layer is flush with the surface of the gate structure; forming an interlayer dielectric layer on the conductive contact layer and the gate structure, and forming a plurality of conductive contact holes in the interlayer dielectric layer, wherein all the conductive contact holes penetrate the interlayer dielectric layer and are respectively in contact with the conductive contact layer and the gate structure. The present invention forms an epitaxial layer and metalizes the epitaxial layer so that the gate structure, the source and the drain are on the same horizontal plane, thereby reducing the process difficulty of the photolithography and etching process of forming the conductive contact hole, reducing the process difficulty and cost of the conductive contact layer, increasing the etching process window of the conductive contact hole, and solving the problem of the conductive contact hole opening in the conductive contact hole etching process, thereby improving the yield, reducing the conductive contact hole overlay alignment specification requirements, and omitting the side wall partial removal (i.e., SPT process), thereby reducing the process cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the structure of a semiconductor device in the prior art.

[0016] Figure 2 This is a schematic diagram of a contact hole open circuit in the prior art.

[0017] Figure 3 A schematic flow chart of a method for preparing a semiconductor device provided by the present invention.

[0018] Figure 4 This is a schematic diagram of the structure of a substrate provided in Embodiment 1 of the present invention.

[0019] Figure 5 It is a schematic diagram of the structure after forming the epitaxial layer according to the first embodiment of the present invention.

[0020] Figure 6 It is a schematic diagram of the structure after forming a metal silicide layer according to the first embodiment of the present invention.

[0021] Figure 7 It is a schematic diagram of the structure after the filling layer is formed according to the first embodiment of the present invention.

[0022] Figure 8 It is a schematic diagram of the structure after forming a patterned photoresist layer according to the first embodiment of the present invention.

[0023] Fig. 9 It is a schematic diagram of the structure after the transition groove is formed in the first embodiment of the present invention.

[0024] Fig.10 It is a schematic diagram of the structure after the conductive contact hole is formed according to the first embodiment of the present invention.

[0025] Fig.11 This is a schematic structural diagram of a substrate provided in Embodiment 2 of the present invention.

[0026] Fig.12 This is a schematic diagram of the structure after the epitaxial layer is formed according to the second embodiment of the present invention.

[0027] Fig.13 This is a schematic diagram of the structure after the filling layer is formed according to the second embodiment of the present invention.

[0028] Fig.14 This is a schematic diagram of the structure of the second embodiment of the present invention when metal elements are injected into the epitaxial layer.

[0029] Fig.15 It is a schematic diagram of the structure after a metal silicide layer is formed according to the second embodiment of the present invention.

[0030] Fig.16 It is a schematic diagram of the structure after a patterned photoresist layer is formed according to the second embodiment of the present invention.

[0031] Fig.17 It is a schematic diagram of the structure after the transition groove is formed in the second embodiment of the present invention.

[0032] Fig.18 It is a schematic diagram of the structure after the conductive contact hole is formed according to the second embodiment of the present invention.

[0033] Description of reference numerals: I-first active area; II-second active area; 100-substrate; 101-first well area; 102-second well area; 103-shallow trench isolation structure; 104-first source doping area; 105-first drain doping area; 106-second source doping area; 107-second drain doping area; 200-gate structure; 201-gate oxide layer; 202-polysilicon gate; 203-sidewall; 204-hard mask layer; 301-epitaxial layer; 302-polysilicon epitaxial structure; 303-first trench; 310-metal silicide layer; 320-filling layer; 330-etching stop layer; 340-interlayer dielectric layer; 350-pattern transfer layer; 360-photoresist layer; 371-second trench; 372-conductive contact hole; DETAILED DESCRIPTION

[0034] A semiconductor device and a method for manufacturing the same of the present invention will be described in further detail below. The present invention will be described in more detail below with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown, and it should be understood that those skilled in the art may modify the present invention described herein and still achieve the beneficial effects of the present invention. Therefore, the following description should be understood as being widely known to those skilled in the art and not as a limitation of the present invention.

[0035] For the sake of clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not described in detail because they would clutter the invention with unnecessary detail. It should be recognized that in the development of any actual embodiment, a large number of implementation details must be made to achieve the developer's specific goals, such as changing from one embodiment to another according to the limitations of the relevant system or the relevant business. In addition, it should be recognized that such development work may be complex and time-consuming, but it is just a routine task for those skilled in the art.

[0036] In order to make the purpose and features of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are further described below in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and use inaccurate ratios, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0037] Embodiment 1 like Figure 3 As shown, this embodiment provides a method for preparing a semiconductor device, comprising the following steps: Step S1: providing a substrate, on which a gate structure is formed, and a source doping region and a drain doping region are respectively formed in the substrate on both sides of the gate structure; Step S2: forming an epitaxial layer on the substrate of all the source doping regions and the drain doping regions, and metalizing the epitaxial layer to form a conductive contact layer, wherein the surface of the conductive contact layer is flush with the surface of the gate structure; Step S3: forming an interlayer dielectric layer on the conductive contact layer and the gate structure, and forming a plurality of conductive contact holes in the interlayer dielectric layer, wherein all the conductive contact holes penetrate the interlayer dielectric layer and contact the conductive contact layer and the gate structure respectively.

[0038] The present invention forms an epitaxial layer and metalizes the epitaxial layer so that the gate structure, the source and the drain are on the same horizontal plane, thereby reducing the process difficulty of the photolithography and etching process of forming the conductive contact hole, reducing the process difficulty and cost of the conductive contact layer, increasing the etching process window of the conductive contact hole, and solving the problem of the conductive contact hole opening in the conductive contact hole etching process, thereby improving the yield, reducing the conductive contact hole overlay alignment specification requirements, and omitting the side wall partial removal (i.e., SPT process), thereby reducing the process cost.

[0039] The following combination Figure 4-Figure 10 A method for preparing a semiconductor device provided in this embodiment is described in detail.

[0040] like Figure 4 As shown, step S1 is first performed to provide a substrate 100 , on which a gate structure 200 is formed, and in which source doping regions and drain doping regions are formed in the substrate 100 on both sides of the gate structure 200 .

[0041] An active area is provided in the substrate 100, and a shallow trench isolation structure 103 is arranged around the outer side of the active area. A well area is formed in the substrate 100 of the active area, and the well area extends from one side of the substrate 100 into the substrate 100 and stops in the substrate 100. A gate structure 200 is formed on the surface of one side of the substrate 100, and the gate structure 200 includes a gate oxide layer 201, a polysilicon gate 202 and a sidewall 203. The gate oxide layer 201 is located on the surface of the substrate 100, and the polysilicon gate 202 is stacked on the gate oxide layer 201. The sidewall 203 is located on both sides of the gate oxide layer 201 and the polysilicon gate 202, and covers the sidewalls of the gate oxide layer 201 and the polysilicon gate 202. A source doping region and a drain doping region are respectively formed in the substrate 100 on both sides of the gate structure 200, a source extension doping region is arranged in the substrate 100 on the side of the source doping region close to the drain doping region, and a drain extension doping region is arranged in the substrate 100 on the side of the drain doping region close to the source doping region, so that the source extension doping region and the drain extension doping region are both located below the gate structure 200, and a pocket doping region is also arranged in the substrate 100 below the source extension doping region and the drain extension doping region.

[0042] In this embodiment, the substrate 100 includes a first active region I and a second active region II for forming a low-voltage device, wherein the first active region I is used to form a low-voltage NMOS transistor, and the second active region II is used to form a low-voltage PMOS transistor. The first active region I and the second active region II are arranged adjacent to each other, and a shallow trench isolation structure 103 is provided around the outer side of the first active region I and the outer side of the second active region II. A first well region 101 is formed in the substrate 100 of the first active region I, and the first well region 101 extends from one side surface of the substrate 100 to the other side surface and stops in the substrate 100. A second well region 102 is formed in the substrate 100 of the second active region II, and the second well region 102 is arranged on the same side as the first well region 101, and the second well region 102 also extends from one side surface of the substrate 100 to the other side surface and stops in the substrate 100. Preferably, the depth of the second well region 102 is the same as the depth of the first well region 101, wherein the first well region 101 is doped with P-type ions and the second well region 102 is doped with N-type ions, and the height of the shallow trench isolation structure 103 is greater than the depth of the first well region 101 and also greater than the depth of the second well region 102.

[0043] In the first active region I, a first source doping region 104 and a first drain doping region 105 are formed in the substrate 100 on both sides of the gate structure 200, wherein the first source doping region 104 and the first drain doping region 105 are both doped with N-type ions; in the second active region II, a second source doping region 106 and a second drain doping region 107 are formed in the substrate 100 on both sides of the gate structure 200, wherein the second source doping region 106 and the second drain doping region 107 are both doped with P-type ions.

[0044] like Figure 4-Figure 7 As shown, step S2 is then performed to form an epitaxial layer 301 on the substrate 100 of all the source doping regions and drain doping regions, and the epitaxial layer 301 is metallized to form a conductive contact layer, wherein the surface of the conductive contact layer is flush with the surface of the gate structure 200 .

[0045] This step specifically includes the following steps: See also Figure 4 First, the height H of the gate structure 200 is measured by an OCD (optical critical dimension) measurement process, that is, the total height of the gate oxide layer 201 and the polysilicon gate 202 is measured.

[0046] See also Figure 5 An epitaxial layer 301 is formed on the substrate 100 in the source doping region and on the substrate 100 in the drain doping region through an epitaxial process, wherein the material of the epitaxial layer 301 is silicon.

[0047] In this embodiment, an epitaxial layer 301 is formed on the surface of the substrate 100 in the first active region I and the second active region II by an epitaxial process, and the epitaxial layer 301 covers the first source doping region 104, the first drain doping region 105, the second source doping region 106 and the second drain doping region 107. At the same time, since the polysilicon gate 202 is exposed to the external environment, a polysilicon epitaxial structure 302 is also formed on the surface of the polysilicon gate 202. At this time, the epitaxial layer 301 is not formed on the shallow trench isolation structure 103, so that a first trench 303 is formed on the shallow trench isolation structure 103. The material of the epitaxial layer 301 is the same as that of the substrate 100, and the material of the polysilicon gate 202 and the polysilicon epitaxial structure 302 is the same.

[0048] See also Figure 6 Then, the epitaxial layer 301 and the polysilicon epitaxial structure 302 are converted into a metal silicide layer 310 to achieve metallization of the epitaxial layer.

[0049] In detail, first, a shielding layer is formed on a portion of the surface of the substrate 100, and the shielding layer covers the area that does not need to be metallized (forming a metal silicide layer). The shielding layer includes a first oxide layer and a first silicon nitride layer from bottom to top, and the material of the first oxide layer is the same as the material of the shallow trench isolation structure 103.

[0050] Next, the natural oxide layer formed on the surface of the epitaxial layer 301 and the polysilicon epitaxial structure 302 is removed by a pre-cleaning process.

[0051] Next, a nickel-platinum (NiPt) alloy film layer of a first preset thickness (e.g., 120Å) and a titanium nitride film layer of a second preset thickness (e.g., 50Å) are sequentially deposited, and the epitaxial layer 301 and the polysilicon epitaxial structure 302 are transformed into a low-resistance nickel-platinum-silicon layer (NiPtSi2) through two heat treatment processes (RTP), and then the excess nickel that has not formed the nickel-platinum-silicon layer (NiPtSi2) is removed. In the two heat treatment processes, since the speed of forming nickel-silicon (NiSi) in the polysilicon epitaxial structure 302 is faster than the speed of forming nickel-silicon (NiSi) in the epitaxial layer 301, when the epitaxial layer 301 is completely transformed into the metal silicide layer 310, the polysilicon epitaxial structure 302 has been transformed first, and a part of the thickness of the polysilicon gate 202 has been transformed, so the thickness of the metal silicide layer 310 above the gate structure 200 is greater than the thickness of the epitaxial layer 301.

[0052] See also Figure 7 Then, an insulating material is filled in the first trench 303, and the substrate is planarized to form a filling layer 320, and the metal silicide layer 310 on the polysilicon gate 202, the metal silicide layer 310 above the source doping region, and the metal silicide layer 310 above the drain doping region are on the same level. In detail, the first silicon nitride layer is first removed, and an oxide material is used in the first trench 303 to form a filling layer 320, and the oxide material also covers the epitaxial layer 301. Then, the excess oxide material is removed by a CMP (chemical mechanical polishing) process to expose the epitaxial layer 301, and a portion of the metal silicide layer 310 above the gate structure 200 is removed at the same time, so that the metal silicide layer 310 on the polysilicon gate 202, the metal silicide layer 310 above the source doping region, and the metal silicide layer 310 above the drain doping region are on the same level. At this time, the filling layer 320 and the shallow trench isolation structure 103 together serve as a new shallow trench isolation structure.

[0053] like Figure 8-Figure 10As shown, step S3 is then performed to form an interlayer dielectric layer 340 on the conductive contact layer and the gate structure 200, and to form a plurality of conductive contact holes 372 in the interlayer dielectric layer 340, wherein all the conductive contact holes 372 pass through the interlayer dielectric layer and contact the conductive contact layer and the gate structure 200 respectively.

[0054] This step specifically includes the following steps: See also Figure 8 First, an etching stop layer 330, an interlayer dielectric layer 340, a pattern transfer layer 350 and a patterned photoresist layer 360 are sequentially formed on the metal silicide layer 310 and the filling layer 320, and the patterned photoresist layer 360 has openings above the source doping region, the drain doping region and the polysilicon gate 202. In this embodiment, the patterned photoresist layer 360 has openings above the first source doping region 104, the first drain doping region 105 and the polysilicon gate 202 of the first active region I, and also has openings above the second source doping region 106, the second drain doping region 107 and the polysilicon gate 202 of the second active region II.

[0055] The material of the interlayer dielectric layer is an oxide layer, the material of the etch stop layer 330 is silicon nitride, and the pattern transfer layer 350 includes an α-carbon film layer, a silicon oxynitride layer, a first silicon oxide layer and a BARC layer from bottom to top.

[0056] See also Fig. 9 Then, using the patterned photoresist layer 360 as a mask, at the opening, the pattern transfer layer 350, the interlayer dielectric layer 340 and the etch stop layer 330 are sequentially etched through a multi-step etching process, and the metal silicide layer 310 is exposed to form a transition groove.

[0057] Next, the photoresist layer 360 and the pattern transfer layer 350 are removed, and the interlayer dielectric layer 340 is exposed to form a second trench 371 .

[0058] See also Fig.10, then, a conductive contact hole 372 is formed in the second trench 371. In detail, a first conductive layer is first formed on the inner wall (bottom wall and side wall) of the second trench 371 by a deposition process, the first conductive layer sequentially including a titanium film layer and a titanium nitride film layer, and the first conductive layer also covers the interlayer dielectric layer 340 outside the second trench 371. Then, a metal material is filled in the second trench 371 by a CVD (chemical vapor deposition) process, and the metal material also covers the first conductive layer on the interlayer dielectric layer 340; finally, the metal material and the first conductive layer on the interlayer dielectric layer 340 are removed by a CMP process to expose the interlayer dielectric layer 340, thereby forming a conductive contact hole 372.

[0059] This embodiment further provides a semiconductor device, including a substrate 100, a gate structure 200 is formed on the substrate 100, a source doping region and a drain doping region are respectively formed in the substrate 100 on both sides of the gate structure 200, a conductive contact layer is formed on the substrate 100 of all the source doping regions and the drain doping regions, an interlayer dielectric layer 340 is formed on the conductive contact layer and the gate structure 200, and a plurality of conductive contact holes 372 are formed in the interlayer dielectric layer 340, all of the conductive contact holes 372 penetrate the interlayer dielectric layer and are respectively in contact with the conductive contact layer and the gate structure 200. The conductive contact layer only includes a metal silicide layer 310.

[0060] Embodiment 2 Compared with the first embodiment, the steps of the method for preparing a semiconductor device provided in this embodiment are different.

[0061] Specifically, in step S1, the gate structure 200 further includes a hard mask layer 204, the hard mask layer 204 covers the polysilicon gate 202, and the hard mask layer 204 includes a second silicon oxide layer and a second silicon nitride layer from bottom to top. The hard mask layer 204 and the partial film layers composed of the sidewall 203 are formed in the same deposition process, but these film layers (i.e., the second silicon oxide layer and the second silicon nitride layer) on the surface of the polysilicon gate 202 are retained when etching to form the sidewall 203, as shown in FIG. Fig.11 shown.

[0062] like Figure 12-13 As shown, step S2 specifically includes the following steps: See also Fig.11 First, the height H of the gate structure 200 is measured by an OCD (optical critical dimension) measurement process, that is, the total height of the gate oxide layer 201 and the polysilicon gate 202 is measured.

[0063] At this time, the thickness of the formed epitaxial layer 301 is still the height H, but since the polysilicon gate 202 is covered by the hard mask layer 204, Fig.12 As shown, then, in the epitaxial process, no polysilicon epitaxial structure 302 is formed on the surface of the polysilicon gate 202, that is, the epitaxial layer 301 is formed only on the substrate 100 of the source doping region and the substrate 100 of the drain doping region through the epitaxial process. In this embodiment, the epitaxial layer 301 is formed on the substrate 100 of the first source doping region 104, the first drain doping region 105, the second source doping region 106, and the second drain doping region 107 through the epitaxial process.

[0064] like Fig.13 As shown, then, an insulating material is filled in the first trench 303, and the substrate is planarized to form a filling layer 320, so as to expose the polysilicon gate 202, and make the polysilicon gate 202 and the epitaxial layer 301 on the same horizontal plane. In detail, a filling material is first deposited in the first trench 303, the filling material covers the epitaxial layer 301, and the filling material and the hard mask layer 204 on the epitaxial layer 301 are removed by a CMP process to form a filling layer 320, at which time, the filling layer 320, the epitaxial layer 301 and the polysilicon gate 202 are on the same horizontal plane.

[0065] like Fig.14 As shown, then, a metal element implantation process is performed on the epitaxial layer 301 close to the substrate side. The metal element may be at least one of metal magnesium (Mg), calcium (Ca) and barium (Ba). Since the material of the epitaxial layer 301 is semiconductor material silicon, and the doping of the metal element adjusts the Schottky barrier height (SBH), thereby effectively reducing the electrical interface resistance of the source / drain electrode. At the same time, the ion implantation process has no effect on the polysilicon gate 202, and since the material of the sidewall 203 is an insulating material, even if the metal element is implanted in the sidewall 203, it is still non-conductive. Therefore, this step only reduces the resistance of the epitaxial layer 301 close to the substrate side. Wherein, the doping concentration of the metal element is greater than or equal to 1×10 21 atoms / cm 3 The epitaxial layer 301 of this step performs a metal element implantation process and does not form a metal silicide layer, so it is different from the step of converting the epitaxial layer 301 and the polysilicon epitaxial structure 302 into a metal silicide layer 310 to achieve epitaxial layer metallization.

[0066] like Fig.15As shown, then, a portion of the thickness of the epitaxial layer 301 away from the substrate side and a portion of the thickness of the polysilicon gate 202 are converted into a metal silicide layer 310 , wherein the metal element injection position is located below the metal silicide layer 310 .

[0067] Step S3 specifically includes: like Fig.16 As shown, first, an etching stop layer 330, an interlayer dielectric layer 340, a pattern transfer layer 350 and a patterned photoresist layer 360 are formed on the surface of the metal silicide layer 310 and the filling layer 320, and the patterned photoresist layer 360 has openings above the first source doping region 104, the first drain doping region 105 and the polysilicon gate 202 in the first active region I, and above the second source doping region 106, the second drain doping region 107 and the polysilicon gate 202 in the second active region II.

[0068] like Fig.17 As shown, then, using the patterned photoresist layer 360 as a mask, at the opening, the pattern transfer layer 350, the interlayer dielectric layer 340 and the etch stop layer 330 are sequentially etched through a multi-step etching process, and the metal silicide layer 310 is exposed to form a transition groove.

[0069] Next, the photoresist layer 360 and the pattern transfer layer 350 are removed, and the interlayer dielectric layer 340 is exposed to form a second trench 371 .

[0070] like Fig.18 As shown, a conductive contact hole 372 is formed in the second trench 371 .

[0071] This embodiment provides a semiconductor device, including a substrate 100, a gate structure 200 is formed on the substrate 100, a source doping region and a drain doping region are respectively formed in the substrate 100 on both sides of the gate structure 200, a conductive contact layer is formed on the substrate 100 of all the source doping regions and the drain doping regions, an interlayer dielectric layer 340 is formed on the conductive contact layer and the gate structure 200, and a plurality of conductive contact holes 372 are formed in the interlayer dielectric layer 340, all of the conductive contact holes 372 penetrate the interlayer dielectric layer and contact the conductive contact layer and the gate structure 200 respectively. The conductive contact layer is composed of an epitaxial layer 301 and a metal silicide layer 310 from bottom to top, and the epitaxial layer 301 is doped with metal elements.

[0072] In summary, the present invention provides a semiconductor device and a method for preparing the same. The method for preparing the semiconductor device comprises the following steps: providing a substrate, on which a gate structure is formed, and drain doping regions and source doping regions are respectively formed in the substrate on both sides of the gate structure; forming an epitaxial layer on the substrate of all the source doping regions and drain doping regions, and metalizing the epitaxial layer to form a conductive contact layer, wherein the surface of the conductive contact layer is flush with the surface of the gate structure; forming an interlayer dielectric layer on the conductive contact layer and the gate structure, and forming a plurality of conductive contact holes in the interlayer dielectric layer, wherein all the conductive contact holes penetrate the interlayer dielectric layer and contact the conductive contact layer and the gate structure, respectively. The present invention forms an epitaxial layer and metalizes the epitaxial layer so that the gate structure, the source and the drain are on the same horizontal plane, thereby reducing the process difficulty of the photolithography and etching process of forming the conductive contact hole, reducing the process difficulty and cost of the conductive contact layer, increasing the etching process window of the conductive contact hole, and solving the problem of the conductive contact hole opening in the conductive contact hole etching process, thereby improving the yield, reducing the conductive contact hole overlay alignment specification requirements, and omitting the side wall partial removal (i.e., SPT process), thereby reducing the process cost.

[0073] In addition, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0074] It is to be understood that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: The following steps are involved: Providing a substrate, on which a gate structure is formed, and in which a drain doping region and a source doping region are respectively formed in the substrate on both sides of the gate structure; Forming an epitaxial layer on the substrate of all the source doping regions and the drain doping regions, and metalizing the epitaxial layer to form a conductive contact layer, wherein the surface of the conductive contact layer is flush with the surface of the gate structure; An interlayer dielectric layer is formed on the conductive contact layer and the gate structure, and a plurality of conductive contact holes are formed in the interlayer dielectric layer, all of which penetrate the interlayer dielectric layer and contact the conductive contact layer and the gate structure respectively.

2. The method for preparing a semiconductor device according to claim 1, wherein: The gate structure includes a gate oxide layer, a polysilicon gate and a sidewall, wherein the gate oxide layer is located on the surface of the substrate, the polysilicon gate is stacked on the gate oxide layer, and the sidewall is located on both sides of the gate oxide layer and the polysilicon gate and covers the sidewalls of the gate oxide layer and the polysilicon gate.

3. The method for preparing a semiconductor device according to claim 2, wherein: The specific method of forming the conductive contact layer is: Measuring the height of the gate structure by an optical critical dimension measurement process, wherein the height of the gate structure is the total height of the gate oxide layer and the polysilicon gate; An epitaxial layer is formed on the substrate of the source doping region and the substrate of the drain doping region through an epitaxial process, and a polysilicon epitaxial structure is formed on the surface of the polysilicon gate, wherein the height of the epitaxial layer is the same as the height of the gate structure; converting the epitaxial layer and the polysilicon epitaxial structure into a metal silicide layer; The substrate is planarized so that the metal silicide layer on the polysilicon gate, the metal silicide layer above the source doping region, and the metal silicide layer above the drain doping region are on the same level.

4. The method for preparing a semiconductor device according to claim 3, wherein: When the metal silicide layer is formed, the thickness of the metal silicide layer on the substrate of the source doping region and the drain doping region is smaller than the thickness of the metal silicide layer on the polysilicon gate.

5. The method for preparing a semiconductor device according to claim 2, wherein: The gate structure further includes a hard mask layer, and the hard mask layer covers the polysilicon gate.

6. The method for preparing a semiconductor device according to claim 5, characterized in that: The specific method of forming the conductive contact layer is: Measuring the height of the gate structure by an optical critical dimension measurement process, wherein the height of the gate structure is the total height of the gate oxide layer and the polysilicon gate; Forming an epitaxial layer on the substrate of the source doping region and on the substrate of the drain doping region through an epitaxial process, wherein the height of the epitaxial layer is the same as the height of the gate structure; Planarizing the substrate to expose the polysilicon gate and make the polysilicon gate and the epitaxial layer be on the same level; Performing a metal element implantation process on the epitaxial layer close to the substrate side; A portion of the thickness of the epitaxial layer away from the substrate side and a portion of the thickness of the polysilicon gate are converted into a metal silicide layer, wherein the metal element injection position is located below the metal silicide layer.

7. The method for preparing a semiconductor device according to claim 6, wherein: The metal element is at least one of magnesium, calcium and barium, and the doping concentration of the metal element is greater than or equal to 1×10 21 atoms / cm 3 .

8. The method for preparing a semiconductor device according to claim 3 or 6, characterized in that: The specific method of forming the conductive contact hole is: forming an etch stop layer, an interlayer dielectric layer, a pattern transfer layer and a patterned photoresist layer in sequence on the metal silicide layer; Using the patterned photoresist layer as a mask, sequentially etching the pattern transfer layer, the interlayer dielectric layer and the etching stop layer, exposing the metal silicide layer, and forming a transition trench at the same time; removing the photoresist layer and the pattern transfer layer and exposing the interlayer dielectric layer to form a second trench; A conductive contact hole is formed in the second trench.

9. A semiconductor device, characterized in that: The invention comprises a substrate, a gate structure is formed on the substrate, a drain doping region and a source doping region are respectively formed in the substrate on both sides of the gate structure, a conductive contact layer is formed on the substrate of all the source doping regions and the drain doping regions, an interlayer dielectric layer is formed on the conductive contact layer and the gate structure, and a plurality of conductive contact holes are formed in the interlayer dielectric layer, all the conductive contact holes penetrate the interlayer dielectric layer and are respectively in contact with the conductive contact layer and the gate structure, wherein the conductive contact layer comprises a metal silicide layer.

10. The semiconductor device according to claim 9, wherein: The conductive contact layer further includes an epitaxial layer, the epitaxial layer is located between the metal silicide layer and the substrate, and the epitaxial layer is doped with metal elements.

Images