Semiconductor device and forming method thereof

Abstract

The invention discloses a semiconductor device and a forming method thereof. The method comprises the following steps: forming a substrate; performing through hole etching on the substrate by adopting a first etching depth to obtain a blind hole; performing pit etching on the substrate by adopting a second etching depth, and performing complementary etching on the blind hole at the same time to obtain a pit and a through hole, the through hole being located in the pit; and forming an isolation material lamination layer on the substrate, wherein the isolation material lamination layer covers the surface of the substrate, the bottom surface and the side wall surface of the pit, and the side wall surface of the through hole. The process limitation can be effectively reduced, the production cost is reduced, and the production efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a method for forming the same. Background Art

[0002] When manufacturing semiconductor devices, it is often necessary to form a pit on the surface of a substrate, and then manufacture structures such as circuits in the pits, so that the top surface after the circuit structure is formed is flush with the area outside the pits.

[0003] However, in the prior art, after forming the pit, it is also necessary to form a through hole between the pit and the metal interconnection structure to form an electrically conductive structure. Since the pit is formed before the through hole, the photoresist coating will be uneven in the etching process of the through hole, resulting in a vortex effect, which affects continuous production.

[0004] In addition, before etching the through hole, an additional protection layer needs to be formed to protect the bottom surface of the pit, and the through hole is etched using the protection layer as a mask. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor device and a method for forming the same, which can effectively reduce process limitations, lower production costs and improve production efficiency.

[0006] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor device, which includes: forming a substrate; using a first etching depth to perform through-hole etching on the substrate to obtain a blind hole; using a second etching depth to perform pit etching on the substrate, and simultaneously performing supplementary etching on the blind hole to obtain a pit and a through-hole, wherein the through-hole is located in the pit; forming an isolation material stack on the substrate, wherein the isolation material stack covers the surface of the substrate, the bottom surface and sidewall surface of the pit, and the sidewall surface of the through-hole.

[0007] Optionally, the isolation material stack includes one or more of the following stacked layers: a linear oxide layer (LinerOxide), an aluminum oxide layer, a tantalum oxide layer, a silicon oxide layer and a silicon nitride layer.

[0008] Optionally, the silicon oxide layer is formed by an atomic layer deposition process.

[0009] Optionally, the second etching depth is used to perform pit etching on the substrate and simultaneously perform supplementary etching on the blind hole, including: using a plasma etching process to perform pit etching on the substrate and simultaneously perform supplementary etching on the blind hole; wherein the plasma etching process includes one or more of the following: a top power of the plasma etching process is higher than a standard top power, and the standard top power is the top power used when pit etching is performed on a sample substrate that does not contain the blind hole; a chamber pressure of the plasma etching process is lower than a standard chamber pressure, and the standard chamber pressure is the chamber pressure used when pit etching is performed on a sample substrate that does not contain the blind hole; a reaction temperature of the plasma etching process is lower than a standard reaction temperature, and the standard reaction temperature is the reaction temperature used when pit etching is performed on a sample substrate that does not contain the blind hole.

[0010] Optionally, the plasma etching process includes one or more of the following: the top power of the plasma etching process is selected from: 800W-2000W; the chamber pressure of the plasma etching process is selected from: 5mT-30mT; the reaction temperature of the plasma etching process is selected from: 30℃-70℃.

[0011] Optionally, the first etching depth is selected from: 0.7um-0.9um.

[0012] Optionally, the second etching depth is selected from: 0.8um-0.9um.

[0013] Optionally, the substrate has a logic circuit area and a pixel area, and the pit is formed on the back side of the substrate in the logic circuit area; the formation of the substrate includes: providing a semiconductor substrate; forming a front isolation structure in the semiconductor substrate in the pixel area and the logic circuit area from the front side of the semiconductor substrate; forming a photodiode in the semiconductor substrate in the pixel area, wherein the front isolation structure is used to isolate adjacent photodiodes.

[0014] Optionally, the forming of the base further includes: forming a semiconductor component structure on the semiconductor substrate in the pixel area, forming a metal interconnection structure on the semiconductor substrate in the pixel area and the logic circuit area, the metal interconnection structure in the pixel area is electrically connected to the semiconductor component structure; bonding the front side of the semiconductor substrate to a carrier wafer, and then thinning the semiconductor substrate from the back side of the semiconductor substrate to obtain the base.

[0015] Optionally, a projection of the through hole on the front surface of the semiconductor substrate is located on the front isolation structure, and the through hole exposes the back surface of the front isolation structure.

[0016] Optionally, after forming the substrate and before performing through-hole etching on the substrate using a first etching depth, the method further includes: forming a grid-shaped back isolation groove within the substrate in the pixel area from the back side of the substrate, the back isolation groove being used to isolate adjacent photodiodes; and in the process of forming the isolation material stack on the substrate, at least a portion of the isolation material stack is filled into the back isolation groove.

[0017] Optionally, the isolation material stack comprises a stack of a linear oxide layer, an aluminum oxide layer, and a tantalum oxide layer formed in sequence; wherein the stack of the linear oxide layer, the aluminum oxide layer, and the tantalum oxide layer is filled into the back isolation trench.

[0018] Optionally, the isolation material stack further includes a stack of silicon oxide layers and silicon nitride layers; the method further includes: using the stack of silicon oxide layers and silicon nitride layers as a protective layer to remove the front isolation structure exposed by the through hole from the back side of the substrate.

[0019] Optionally, the method further comprises: forming a pad structure in the pit and the through hole, wherein the pad structure is electrically coupled to the metal interconnection structure on the front side of the substrate in the logic circuit region.

[0020] Optionally, the pad structure is a multi-layer structure; the method further includes: forming a grid structure on the back side of the substrate in the pixel area, the grid structure being a multi-layer structure; wherein, on the back side of the substrate, the top surface of the pad structure is flush with the top surface of the grid structure.

[0021] Optionally, at least a portion of the multilayer structure of the grid structure and at least a portion of the multilayer structure of the liner structure are formed sequentially using the same process.

[0022] Optionally, the method further includes: forming a filter within the grid structure of the pixel area; and forming a microlens structure on the grid structure of the pixel area and on a portion of the pad structure of the logic circuit area.

[0023] To solve the above technical problems, an embodiment of the present invention further provides a semiconductor device, comprising: a substrate; a pit formed on the substrate; a through hole located in the pit; an isolation material stack formed on the substrate, the isolation material stack covering the surface of the substrate, the bottom surface and side wall surface of the pit, and the side wall surface of the through hole.

[0024] Optionally, the isolation material stack includes one or more stacked layers of the following: a linear oxide layer, an aluminum oxide layer, a tantalum oxide layer, a silicon oxide layer, and a silicon nitride layer.

[0025] Optionally, the substrate has a logic circuit area and a pixel area, and the pit is formed on the back side of the substrate in the logic circuit area; the substrate includes: a semiconductor substrate; a front isolation structure formed on the front side of the semiconductor substrate, within the semiconductor substrate in the pixel area and the logic circuit area; a photodiode formed in the semiconductor substrate in the pixel area, wherein the front isolation structure is used to isolate adjacent photodiodes.

[0026] Optionally, the base also includes: a semiconductor component structure formed on the semiconductor substrate in the pixel area; a metal interconnection structure formed on the semiconductor substrate in the pixel area and the logic circuit area, the metal interconnection structure in the pixel area is electrically connected to the semiconductor component structure; and a carrier wafer bonded to the front side of the semiconductor substrate.

[0027] Optionally, a projection of the through hole on the front surface of the semiconductor substrate is located on the front isolation structure, and the through hole exposes the back surface of the front isolation structure.

[0028] Optionally, the semiconductor device further includes: a grid-shaped back side isolation groove formed on the back side of the substrate in the pixel area, the back side isolation groove being used to isolate adjacent photodiodes; wherein at least a portion of the isolation material stack is filled into the back side isolation groove.

[0029] Optionally, the isolation material stack comprises a stack of a linear oxide layer, an aluminum oxide layer, and a tantalum oxide layer formed in sequence; wherein the stack of the linear oxide layer, the aluminum oxide layer, and the tantalum oxide layer is filled into the back isolation trench.

[0030] Optionally, the semiconductor device further includes: a pad structure formed in the pit and the through hole, wherein the pad structure is electrically coupled to the metal interconnection structure on the front side of the substrate in the logic circuit region.

[0031] Optionally, the pad structure is a multi-layer structure; the semiconductor device also includes: a grid structure formed on the back side of the substrate in the pixel area, and the grid structure is a multi-layer structure; wherein, on the back side of the substrate, the top surface of the pad structure is flush with the top surface of the grid structure.

[0032] Optionally, the semiconductor device further includes: a color filter formed in the grid structure of the pixel area; a microlens structure formed on the grid structure of the pixel area and on a portion of the pad structure of the logic circuit area.

[0033] Optionally, the total thickness of the linear oxide layer, the aluminum oxide layer and the tantalum oxide layer is selected from: 400A-800A.

[0034] Optionally, the total thickness of the stacked layer of the silicon oxide layer and the silicon nitride layer is selected from: 1400A-2200A.

[0035] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0036] In an embodiment of the present invention, a first etching depth is used to perform through-hole etching on the substrate to obtain a blind hole, and then a second etching depth is used to perform pit etching on the substrate while performing supplementary etching on the blind hole to obtain a pit and a through-hole, and then an isolation material stack is formed to cover the surface of the substrate, the bottom surface and sidewall surface of the pit, and the sidewall surface of the through-hole. By adopting the above scheme, the through-hole etching is first performed to form only the blind hole, and then the pit etching is performed. Since the area of ​​the blind hole is smaller than the area of ​​the pit, the uniformity of the photoresist coating is improved, and the influence of the cyclone effect can be effectively reduced. In addition, the through-hole is obtained by performing through-hole etching on the substrate at a first etching depth to obtain a blind hole, and then performing pit etching on the substrate at a second etching depth while supplementary etching on the blind hole. The through-hole etching does not require the formation of an additional protective layer to protect the bottom surface of the pit. Compared with the solution of etching the pit first and then etching the through-hole, which requires the formation of an additional protective layer to protect the bottom surface of the pit during the through-hole etching process, the solution of the embodiment of the present invention can reduce the formation of an isolation material stack, reduce production costs, and speed up product production. In addition, it is precisely because no additional protective layer is required in the process of forming the pit and the through-hole that the isolation material stack can directly cover the side wall surface of the through-hole, effectively protect the inner side wall of the through-hole, and improve the quality of the device.

[0037] Furthermore, the pit etching adopts a plasma etching process. Through the higher top power of the plasma etching process, a plasma with a higher concentration is formed to enhance the etching reaction; the reaction is carried out at low pressure, which increases the molecular mean free path and enhances the bottom etching ability; the etching reaction is carried out at a low temperature to protect the substrate front device. The top power of the plasma etching process is selected from: 800W-2000W; the chamber pressure of the plasma etching process is selected from: 5mT-30mT; the reaction temperature of the plasma etching process is selected from: 30℃-70℃. The step shape of the pit and the blind hole can be maintained during the plasma etching process.

[0038] Furthermore, the isolation material stack also includes a stacked layer of silicon oxide layer and silicon nitride layer. The stacked layer of silicon oxide layer and silicon nitride layer is used as a protective layer. The front isolation structure exposed by the through hole is removed from the back side of the substrate. By adopting the above scheme, blanket etching (Blanket Etch) can be directly performed under the protection of the protective layer, thereby reducing a layer of mask and its corresponding patterned etching steps, effectively improving production efficiency and reducing production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figures 1 to 5 It is a partial schematic diagram of a device cross-sectional structure corresponding to some steps in a method for forming a semiconductor device in the prior art;

[0040] Figure 6 is a flow chart of a method for forming a semiconductor device in an embodiment of the present invention;

[0041] Figures 7 to 14 It is a schematic diagram of a device cross-sectional structure corresponding to each step in a method for forming a semiconductor device in an embodiment of the present invention.

[0042] Reference numerals:

[0043] Semiconductor substrate 100; pit 101; first protective layer 110; through hole 120; second protective layer 130; semiconductor substrate 200; front isolation structure 201; photodiode 202; semiconductor component structure 203; metal interconnect structure 204; carrier wafer 205; back isolation groove 206; first substrate protective layer 210; first mask layer 211; blind hole 212; first etching depth D1; second substrate protective layer 220; second mask layer 221; pit 222; through hole 223; second etching depth D2; isolation material stack 230; pad structure 240; grid structure 241. DETAILED DESCRIPTION

[0044] In the manufacture of semiconductor devices, it is often necessary to form a pit on the surface of the substrate, and then make a circuit or other structure in the pit, so that the top surface after the circuit structure is formed is flush with the area outside the pit. In one prior art, the pit is first etched on the surface of the substrate, and then a first protective layer is formed on the surface of the substrate, the bottom surface and the side wall surface of the pit, and a through hole is etched in the pit. Then a second protective layer is formed on the surface of the substrate, the bottom surface and the side wall surface of the pit, and the side wall surface of the through hole, and then a full etching is performed to remove the exposed substrate in the through hole.

[0045] Figures 1 to 5 It is a partial schematic diagram of a device cross-sectional structure corresponding to some steps in a method for forming a semiconductor device in the prior art.

[0046] Reference Figure 1 , providing a semiconductor substrate 100, and performing pit etching on the semiconductor substrate 100 to form a pit 101.

[0047] Reference Figure 2 A first protective layer 110 is formed on the semiconductor substrate 100, and the first protective layer 110 covers the surface of the semiconductor substrate 100, the bottom surface and the side wall surface of the pit 101. The first protective layer 110 is used to reduce the damage to the semiconductor substrate 100 and the pit 101 during the etching of the through hole.

[0048] Reference Figure 3 , the semiconductor substrate 100 is subjected to through-hole etching to form a through-hole 120 .

[0049] Reference Figure 4 A second protective layer 130 is formed on the semiconductor substrate 100, and the second protective layer 130 covers the surface of the semiconductor substrate 100, the bottom surface and side wall surface of the pit 101, and the side wall surface of the through hole 120. The second protective layer 130 is used to reduce the damage to the semiconductor substrate 100, the pit 101, and the through hole 120 during the comprehensive etching.

[0050] Reference Figure 5 , the semiconductor substrate 100 is fully etched to remove the substrate exposed in the through hole 120.

[0051] The inventor of the present invention has found through research that in the prior art, the presence of the pits will lead to uneven photoresist coating in the through-hole etching process, resulting in a vortex effect, which affects continuous production. In addition, it is necessary to form an additional protective layer before the through-hole etching to protect the bottom surface and side wall surface of the pit, and use the protective layer as a mask to etch the through-hole, which is a relatively complex process and leads to high production costs.

[0052] In an embodiment of the present invention, a substrate is formed; a first etching depth is used to perform through-hole etching on the substrate to obtain a blind hole; a second etching depth is used to perform pit etching on the substrate, and the blind hole is supplementally etched to obtain a pit and a through-hole, wherein the through-hole is located in the pit; an isolation material stack is formed on the substrate, and the isolation material stack covers the surface of the substrate, the bottom surface and side wall surface of the pit, and the side wall surface of the through-hole. With the above scheme, by first performing the through-hole etching and only forming the blind hole, and then performing the pit etching, since the area of ​​the blind hole is smaller than the area of ​​the pit, the uniformity of the photoresist coating is improved, and the influence of the cyclone effect can be effectively reduced. In addition, the through-hole is obtained by performing through-hole etching on the substrate at the first etching depth to obtain a blind hole, and then performing pit etching on the substrate at the second etching depth, and supplementally etching the blind hole. The through-hole etching does not require the formation of an additional protective layer to protect the bottom surface of the pit. Compared with the solution of etching the pit first and then etching the through-hole, which requires the formation of an additional protective layer to protect the bottom surface of the pit during the through-hole etching process, the solution of the embodiment of the present invention can reduce the formation of an isolation material stack, reduce production costs, and speed up product production. In addition, it is precisely because no additional protective layer is required in the process of forming the pit and the through-hole that the isolation material stack can directly cover the side wall surface of the through-hole, effectively protect the inner side wall of the through-hole, and improve the quality of the device.

[0053] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0054] Reference Figure 6 , Figure 6 1 is a flow chart of a method for forming a semiconductor device in an embodiment of the present invention. The method for forming a semiconductor device may include steps S61 to S64:

[0055] Step S61: forming a substrate;

[0056] Step S62: using a first etching depth to perform through-hole etching on the substrate to obtain a blind hole;

[0057] Step S63: using a second etching depth to perform pit etching on the substrate and simultaneously perform complementary etching on the blind hole to obtain a pit and a through hole, wherein the through hole is located in the pit;

[0058] Step S64: forming an isolation material stack on the substrate, wherein the isolation material stack covers the surface of the substrate, the bottom surface and the side wall surface of the pit, and the side wall surface of the through hole.

[0059] Combine the following Figures 7 to 11 Each of the above steps is described below.

[0060] Figures 7 to 11 It is a schematic diagram of a device cross-sectional structure corresponding to each step in a method for forming a semiconductor device in an embodiment of the present invention.

[0061] Reference Figure 7 , forming a substrate having a logic circuit area and a pixel area.

[0062] In some embodiments, the step of forming a base may include: providing a semiconductor substrate 200 , wherein the semiconductor substrate 200 has a front side and a back side.

[0063] In a specific implementation, the semiconductor substrate 200 can be a silicon substrate, or the material of the semiconductor substrate 200 can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. The semiconductor substrate 200 can also be a silicon substrate on an insulator surface or a germanium substrate on an insulator surface, or a substrate on which an epitaxial layer (Epi layer) is grown.

[0064] Preferably, the semiconductor substrate 200 is a lightly doped semiconductor substrate, and the doping type is opposite to that of the photodiode formed in the semiconductor substrate 200 in the subsequent process. If the doping ion type of the photodiode is N-type, the doping ion of the semiconductor substrate 200 is P-type ion, for example, including B, Ga or In; conversely, if the doping ion type of the photodiode is P-type, the doping ion of the semiconductor substrate 200 is N-type ion, for example, including P, As or Sb.

[0065] The step of forming a base may further include: forming a front isolation structure 201 in the semiconductor substrate 200 in the pixel region and the logic circuit region from the front side of the semiconductor substrate 200 .

[0066] Specifically, the front isolation structure 201 can be a shallow trench isolation (STI) structure, and its specific process includes: forming a shallow trench on a substrate, the shallow trench is used to isolate the active area on the substrate, and the shallow trench can be formed by an etching process; filling a dielectric into the shallow trench and forming a dielectric layer on the surface of the substrate, and the dielectric material can be silicon oxide; annealing the dielectric; and processing the dielectric layer by chemical mechanical polishing (Chemical Mechanical Polishing, CMP).

[0067] A photodiode 202 is formed in the semiconductor substrate 200 in the pixel region, wherein the front isolation structure 201 is used to isolate adjacent photodiodes 202 .

[0068] Specifically, when the doping type of the photodiode 202 is N-type, the doping ions of the photodiode 202 can be set to include P, As or Sb; when the doping type of the photodiode 202 is P-type, the doping ions of the photodiode 202 can be set to include B, Ga or In.

[0069] Preferably, the doping ions of the photodiode 202 may be boron ions (P) or arsenic ions (As).

[0070] It should be noted that the thickness of the photodiode 202 can be greater than the depth of the front isolation structure 201, so as to obtain a larger full well capacity. The depth of the front isolation structure 201 and the thickness of the photodiode 202 are both perpendicular to the surface of the semiconductor substrate 200.

[0071] Then, a semiconductor component structure 203 may be formed on the semiconductor substrate 200 in the pixel region, and a metal interconnection structure 204 may be formed on the semiconductor substrate 200 in the pixel region and the logic circuit region, wherein the metal interconnection structure 204 in the pixel region is electrically connected to the semiconductor component structure 203. The front surface of the semiconductor substrate 200 is bonded to a carrier wafer 205, and then the semiconductor substrate 200 is thinned from the back surface of the semiconductor substrate 200 to obtain the base.

[0072] The semiconductor component structure 203 may include logic devices in a logic circuit region, pixel devices in a pixel region (eg, other semiconductor component structures except the photodiode 202 ), and the like.

[0073] It should be noted that, in the embodiment of the present invention, the processing process performed on the front surface of the semiconductor substrate 200 may also include any conventional processing process of an existing image sensor, and the embodiment of the present invention does not limit this.

[0074] After the substrate is formed, a grid-shaped back side isolation trench 206 is formed in the substrate in the pixel region from the back side of the substrate. The back side isolation trench 206 is used to isolate the adjacent photodiodes 202 .

[0075] Specifically, the back side isolation trench 206 may be formed by an etching process.

[0076] Reference Figure 8A first substrate protection layer 210 and a patterned first mask layer 211 are formed on the back side of the substrate and in the back side isolation trench 206 .

[0077] The material of the first substrate protection layer 210 may be an oxide layer, and specifically, may be formed by a thermal oxidation process or a chemical vapor deposition process.

[0078] It should be noted that the material of the first substrate protection layer 210 may also be other appropriate materials, such as a nitride layer.

[0079] Among them, the material of the first substrate protective layer 210 can be determined according to the material of the semiconductor substrate 200. For example, if the semiconductor substrate 200 is a silicon substrate, the material of the first substrate protective layer 210 can be silicon oxide; for example, if the semiconductor substrate 200 is a germanium substrate, the material of the first substrate protective layer 210 can be germanium oxide.

[0080] The patterned first mask layer 211 may be a patterned first photoresist layer.

[0081] Reference Fig. 9 Using the first mask layer 211 as a mask and adopting a first etching depth D1, the substrate is subjected to through-hole etching (Via Etch) to obtain a blind hole 212 .

[0082] It should be noted that in some embodiments, when the semiconductor device is an image sensor, after a through hole is obtained by supplementary etching, the through hole needs to expose the back side of the front isolation structure. Therefore, the first etching depth D1 should not be too small, otherwise it is difficult to obtain a through hole with sufficient depth after supplementary etching and obtaining the required pit depth; the first etching depth D1 should not be too large, otherwise it is difficult to obtain a pit with sufficient depth after obtaining the required through hole depth.

[0083] Further, the first etching depth D1 may be a difference between a standard depth of the through hole and a standard depth of the pit.

[0084] The standard depth may be determined according to a design rule and a standard recipe flow.

[0085] In a specific embodiment, the first etching depth D1 can be selected from: 0.7um-0.9um.

[0086] Reference Fig.10 A second substrate protection layer 220 and a patterned second mask layer 221 are formed on the back side of the substrate and in the back side isolation trench 206 .

[0087] For the materials, formation methods and beneficial effects of the second substrate protection layer 220 and the second mask layer 221, please refer to the above and Figure 8 The description is executed and will not be repeated here.

[0088] Reference Fig.11 Using the second mask layer 221 as a mask and adopting a second etching depth D2, the substrate is pit etched and the blind hole 212 is supplementarily etched to obtain a pit 222 and a through hole 223 .

[0089] The pit 222 is formed on the back side of the substrate in the logic circuit area, and the through hole 223 is located in the pit 222. The projection of the through hole 223 on the front side of the semiconductor substrate 200 is located on the front isolation structure 201, and the through hole 223 exposes the back side of the front isolation structure 201.

[0090] In the above specific embodiment, the second etching depth D2 may be a standard depth of the etching process of the pit 222 .

[0091] Specifically, the second etching depth D2 of the pit may be selected from: 0.8um-0.9um.

[0092] Furthermore, the pit etching may adopt a plasma etching process.

[0093] The plasma etching process includes one or more of the following: the top power of the plasma etching process is higher than the standard top power, and the standard top power is the top power used when pit etching is performed on the sample substrate that does not contain the blind hole; the chamber pressure of the plasma etching process is lower than the standard chamber pressure, and the standard chamber pressure is the chamber pressure used when pit etching is performed on the sample substrate that does not contain the blind hole; the reaction temperature of the plasma etching process is lower than the standard reaction temperature, and the standard reaction temperature is the reaction temperature used when pit etching is performed on the sample substrate that does not contain the blind hole.

[0094] In some embodiments, by using a higher top power of the plasma etching process, a plasma with a higher concentration can be formed to enhance the etching reaction.

[0095] In a specific embodiment, the top power of the plasma etching process may be selected from: 800W-2000W, for example, selected from 1200W-1600W, such as 1400W.

[0096] In some embodiments, by performing the etching reaction at a low pressure, the molecular mean free path can be increased and the bottom etching ability can be enhanced.

[0097] In a specific embodiment, the chamber pressure of the plasma etching process may be selected from: 5mT-30mT, for example, selected from 15mT-25mT.

[0098] In some embodiments, by performing the etching reaction at a low temperature, the substrate front side devices can be protected.

[0099] In a specific embodiment, the reaction temperature of the plasma etching process may be selected from: 30°C-70°C, for example, selected from 40°C-60°C, such as 50°C.

[0100] It should be noted that, by adopting one or more of the above process parameters, the step shape of the pit and the blind hole can be maintained during the plasma etching process.

[0101] It should be pointed out that by first performing the through-hole etching and only forming the blind hole 212, and then performing the pit etching, since the area of ​​the blind hole 212 is smaller than the area of ​​the pit 222, the uniformity of the photoresist coating is improved, and the influence of the wind vortex effect can be effectively reduced. In addition, the through-hole 223 is obtained by using a first etching depth D1 to perform through-hole etching on the substrate to obtain the blind hole 212, and then performing pit etching on the substrate with a second etching depth D2, and at the same time performing supplementary etching on the blind hole 212. The through-hole etching does not require the formation of an additional protective layer to protect the bottom surface of the pit 222. Compared with the solution of first etching the pit and then etching the through-hole, which requires the formation of an additional protective layer to protect the bottom surface of the pit 222 during the through-hole etching process, the solution of the embodiment of the present invention can reduce the formation of a stack of isolation materials, reduce production costs, and speed up product production.

[0102] Reference Fig.12 , an isolation material stack 230 is formed on the substrate, and the isolation material stack 230 covers the surface of the substrate, the bottom surface and the side wall surface of the pit 222, and the side wall surface of the through hole 223.

[0103] Specifically, the isolation material stack 230 may include one or more of the following stacked layers: a linear oxide layer, an aluminum oxide layer, a tantalum oxide layer, a silicon oxide layer, and a silicon nitride layer.

[0104] Among them, the linear oxide layer (Liner Oxide) can be formed by a thermal oxidation process, and its material can be determined according to the material of the semiconductor substrate 200. For example, if the semiconductor substrate 200 is a silicon substrate, the material of the linear oxide layer can be silicon oxide; for example, if the semiconductor substrate 200 is a germanium substrate, the material of the linear oxide layer can be germanium oxide.

[0105] It should be noted that the dielectric constant (K value) of aluminum oxide (Al2O3) is 39.922, and the dielectric constant (K value) of tantalum oxide (Ta2O5) can be adjusted between 11.6 and 34.3 according to requirements. Therefore, when one or more of the aluminum oxide layer and the tantalum oxide layer are used to form an isolation material stack, a high-K (HK) material layer can be obtained, which helps to obtain better thermal stability and lower leakage current.

[0106] Furthermore, the silicon oxide layer may be formed by an atomic layer deposition (ALD) process to improve the coverage performance and material density of the step and sidewall surfaces.

[0107] It should be noted that the silicon oxide layer may also be formed by other appropriate processes, such as other chemical vapor deposition processes besides the atomic layer deposition process.

[0108] In some embodiments, the total thickness of the linear oxide layer, the aluminum oxide layer, and the tantalum oxide layer may be selected from: 400 Å-800 Å, to achieve a better balance between process cost control and protection performance.

[0109] In some embodiments, the total thickness of the stacked layer of the silicon oxide layer and the silicon nitride layer is selected from: 1400 Å-2200 Å, so as to achieve a better balance between process cost control and protection performance.

[0110] In the embodiment of the present invention, a dielectric material is filled in the back isolation trench 206. The dielectric material is a stacked layer of a linear oxide layer, an aluminum oxide layer, and a tantalum oxide layer. By filling the back isolation trench 206 with a dielectric material, an isolation structure for isolating an active area can be formed.

[0111] It should be pointed out that, precisely because no additional protective layer is required in the process of forming the pit 222 and the through hole 223, the isolation material stack 230 can directly cover the side wall surface of the through hole 223, effectively protecting the inner wall of the through hole 223 and improving the device quality.

[0112] Reference Fig.13 , a full etching is performed from the back side of the substrate to remove the front isolation structure exposed by the through hole 223.

[0113] It is understandable that, in another specific implementation, a patterned mask layer may be formed, and etching may be performed using the patterned mask layer as a mask.

[0114] It should be pointed out that, when the isolation material stack 230 also includes a stacked layer of silicon oxide layer and silicon nitride layer, the comprehensive etching can use the stacked layer of silicon oxide layer and silicon nitride layer formed in the previous process as a protective layer, and directly etch the substrate under the protection of the protective layer. Compared with the patterned etching process, one mask layer and its photolithography process are reduced, thereby improving production efficiency.

[0115] It should be noted that after full etching, a portion of the thickness of the stacked layer of the silicon oxide layer and the silicon nitride layer will be consumed, thereby achieving protection of the HK material layer.

[0116] Reference Fig.14 A pad structure 240 is formed in the pit 222 and the through hole 223. The pad structure 240 is a multi-layer structure. The pad structure 240 is electrically coupled to the metal interconnect structure 204 on the front side of the substrate in the logic circuit region. A grid structure 241 is formed on the back side of the substrate in the pixel region. The grid structure 241 is a multi-layer structure. On the back side of the substrate, the top surface of the pad structure 240 is flush with the top surface of the grid structure 241.

[0117] Specifically, at least a portion of the multi-layer structure of the grid structure 241 and at least a portion of the multi-layer structure of the pad structure 240 are formed sequentially using the same process.

[0118] Furthermore, a color filter is formed in the grid structure 241 in the pixel area; a micro-lens structure is formed on the grid structure 241 in the pixel area and on a portion of the pad structure 240 in the logic circuit area.

[0119] It should be noted that by keeping the top surface of the pad structure 240 in the pixel area flush with the top surface of the grid structure 241, a better bottom foundation can be provided for forming the filter, which can effectively improve the wind vortex effect when coating the photoresist.

[0120] It should be noted that, in the embodiment of the present invention, after the microlens structure is formed, the processing process performed on the substrate may be any conventional processing process of an existing image sensor, and the embodiment of the present invention does not limit this.

[0121] In an embodiment of the present invention, a semiconductor device is further provided, referring to Fig.14The semiconductor device may include: a substrate; a pit 222 formed on the substrate; a through hole 223, wherein the through hole 223 is located in the pit 222; an isolation material stack 230 formed on the substrate, wherein the isolation material stack 230 covers the surface of the substrate, the bottom surface and side wall surface of the pit 222, and the side wall surface of the through hole 223.

[0122] Furthermore, the isolation material stack 230 includes one or more stacked layers of the following: a linear oxide layer, an aluminum oxide layer, a tantalum oxide layer, a silicon oxide layer, and a silicon nitride layer.

[0123] Furthermore, the substrate has a logic circuit region and a pixel region, and the pit 222 is formed on the back side of the substrate in the logic circuit region; the substrate comprises: a semiconductor substrate 200; a front isolation structure 201 (refer to Fig.12 ) is formed on the front side of the semiconductor substrate 200, within the semiconductor substrate 200 in the pixel area and the logic circuit area; a photodiode 202 is formed in the semiconductor substrate 200 in the pixel area, wherein the front isolation structure 201 is used to isolate adjacent photodiodes 202.

[0124] Furthermore, the base also includes: a semiconductor component structure 203, formed on the semiconductor substrate 200 in the pixel area; a metal interconnection structure 204, formed on the semiconductor substrate 200 in the pixel area and the logic circuit area, the metal interconnection structure 204 in the pixel area is electrically connected to the semiconductor component structure 203; and a carrier wafer 205, bonded to the front side of the semiconductor substrate 200.

[0125] Furthermore, the projection of the through hole 223 on the front surface of the semiconductor substrate 200 is located on the front isolation structure 201 , and the through hole 223 exposes the back surface of the front isolation structure 201 .

[0126] Furthermore, the semiconductor device also includes: a grid-shaped back isolation groove 206 formed on the back side of the substrate in the pixel area, and the back isolation groove 206 is used to isolate the adjacent photodiodes 202; wherein at least a portion of the isolation material stack 230 is filled into the back isolation groove 206.

[0127] Furthermore, the isolation material stack 230 includes a stack of a linear oxide layer, an aluminum oxide layer, and a tantalum oxide layer formed in sequence; wherein the stack of the linear oxide layer, the aluminum oxide layer, and the tantalum oxide layer is filled into the back isolation trench 206 .

[0128] Furthermore, the semiconductor device further includes: a pad structure 240 formed in the pit 222 and the through hole 223 , and the pad structure 240 is electrically coupled to the metal interconnect structure 204 on the front side of the substrate in the logic circuit region.

[0129] Furthermore, the pad structure 240 is a multi-layer structure; the semiconductor device also includes: a grid structure 241, formed on the back side of the substrate in the pixel area, and the grid structure 241 is a multi-layer structure; wherein, on the back side of the substrate, the top surface of the pad structure 240 is flush with the top surface of the grid structure 241.

[0130] Furthermore, the semiconductor device also includes: a filter formed in the grid structure 241 of the pixel area; a microlens structure formed on the grid structure 241 of the pixel area and on a portion of the pad structure 240 of the logic circuit area.

[0131] Furthermore, the total thickness of the linear oxide layer, the aluminum oxide layer and the tantalum oxide layer is selected from: 400A-800A.

[0132] Furthermore, the total thickness of the stacked layer of the silicon oxide layer and the silicon nitride layer is selected from: 1400A-2200A.

[0133] For the principle, specific implementation and beneficial effects of this semiconductor device, please refer to the previous article and Figures 7 to 14 The related description about the method for forming the semiconductor device shown is not repeated here.

[0134] It should be understood that the term "and / or" herein is merely an association relationship describing associated objects, indicating that three relationships may exist, for example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " herein indicates that the associated objects before and after are in an "or" relationship. As used herein, unless otherwise expressly stated, the term "or" covers all possible combinations unless not feasible. For example, if a component is stated to include A or B, then unless otherwise expressly stated or not feasible, the component may include A, or B, or A and B. As a second example, if a component is stated to include A, B, or C, then unless otherwise expressly stated or not feasible, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0135] The "plurality" appearing in the embodiments of the present application refers to two or more.

[0136] Relational terms appearing in the embodiments of the present application, such as first, second, etc., are only used to distinguish an entity or operation from another entity or operation, and do not require or imply any actual relationship or order between these entities or operations. In addition, the words "include", "have", "include" and other similar forms are intended to be equivalent in meaning and are open-ended, and one or more items following any of these words are not meant to be an exhaustive list of such one or more items, or to be limited to the listed one or more items.

[0137] It should be pointed out that the serial numbers of the steps in this embodiment do not limit the execution order of the steps.

[0138] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor device, characterized in that: include: forming a base; Using a first etching depth, the substrate is subjected to through-hole etching to obtain a blind hole; Using a second etching depth, the substrate is etched into a pit, and the blind hole is supplementally etched to obtain a pit and a through hole, wherein the through hole is located in the pit; An isolation material stack is formed on the substrate, the isolation material stack covers the surface of the substrate, the bottom surface and the sidewall surface of the pit, and the sidewall surface of the through hole.

2. The method according to claim 1, characterized in that The insulating material stack comprises stacked layers of one or more of the following: Linear oxide layer, aluminum oxide layer, tantalum oxide layer, silicon oxide layer and silicon nitride layer.

3. The method according to claim 2, characterized in that The silicon oxide layer is formed by an atomic layer deposition process.

4. The method according to claim 1, characterized in that: The method of using the second etching depth to perform pit etching on the substrate and simultaneously performing supplementary etching on the blind hole comprises: Using a plasma etching process, the substrate is etched into pits, and the blind holes are etched at the same time; Wherein, the plasma etching process includes one or more of the following: The top power of the plasma etching process is higher than the standard top power, and the standard top power is the top power used when pit etching is performed on a sample substrate that does not contain the blind hole; The chamber pressure of the plasma etching process is lower than the standard chamber pressure, and the standard chamber pressure is the chamber pressure used when pit etching is performed on a sample substrate that does not contain the blind hole; The reaction temperature of the plasma etching process is lower than the standard reaction temperature, which is the reaction temperature used when pit etching is performed on a sample substrate that does not include the blind hole.

5. The method according to claim 4, characterized in that The plasma etching process includes one or more of the following: The top power of the plasma etching process is selected from: 800W-2000W; The chamber pressure of the plasma etching process is selected from: 5mT-30mT; The reaction temperature of the plasma etching process is selected from: 30°C-70°C.

6. The method according to claim 1, characterized in that The first etching depth is selected from: 0.7um-0.9um.

7. The method according to claim 1, characterized in that The second etching depth is selected from: 0.8um-0.9um.

8. The method according to claim 1, characterized in that: The substrate has a logic circuit area and a pixel area, and the pit is formed on the back side of the substrate in the logic circuit area; The forming of the substrate comprises: providing a semiconductor substrate; From the front side of the semiconductor substrate, forming a front side isolation structure in the semiconductor substrate in the pixel area and the logic circuit area; A photodiode is formed in the semiconductor substrate in the pixel region, wherein the front isolation structure is used to isolate adjacent photodiodes.

9. The method according to claim 8, characterized in that The forming of the substrate further comprises: Forming a semiconductor component structure on the semiconductor substrate in the pixel area, forming a metal interconnection structure on the semiconductor substrate in the pixel area and the logic circuit area, wherein the metal interconnection structure in the pixel area is electrically connected to the semiconductor component structure; The front side of the semiconductor substrate is bonded to a carrier wafer, and then the semiconductor substrate is thinned from the back side of the semiconductor substrate to obtain the base.

10. The method according to claim 8, characterized in that The projection of the through hole on the front surface of the semiconductor substrate is located on the front isolation structure, and the through hole exposes the back surface of the front isolation structure.

11. The method according to claim 8, characterized in that After forming the substrate and before etching the substrate with a first etching depth to form a through hole, the method further includes: forming a grid-shaped back isolation groove in the substrate in the pixel region from the back side of the substrate, the back isolation groove being used to isolate adjacent photodiodes; During the process of forming the isolation material stack on the substrate, at least a portion of the isolation material stack fills into the backside isolation trench.

12. The method according to claim 11, characterized in that The isolation material stack comprises a stack of linear oxide layers, aluminum oxide layers, and tantalum oxide layers formed in sequence; Wherein, the stacked layer of the linear oxide layer, the aluminum oxide layer and the tantalum oxide layer is filled into the back isolation trench.

13. The method according to claim 11, characterized in that The isolation material stack further includes a stack of silicon oxide layers and silicon nitride layers; The method further comprises: The stacked layer of the silicon oxide layer and the silicon nitride layer is used as a protective layer to remove the front isolation structure exposed by the through hole from the back side of the substrate.

14. The method according to claim 13, characterized in that The method further comprises: A pad structure is formed in the pit and the through hole, and the pad structure is electrically coupled to the metal interconnect structure on the front side of the substrate in the logic circuit area.

15. The method according to claim 14, characterized in that The liner structure is a multi-layer structure; The method further comprises: forming a grid structure on the back side of the substrate in the pixel area, wherein the grid structure is a multi-layer structure; Wherein, on the back side of the substrate, the top surface of the pad structure is flush with the top surface of the grid structure.

16. The method according to claim 15, characterized in that At least a portion of the multilayer structure of the grid structure and at least a portion of the multilayer structure of the pad structure are formed sequentially using the same process.

17. The method according to claim 15, characterized in that The method further comprises: forming a filter within the grid structure of the pixel region; A microlens structure is formed on the grid structure in the pixel region and on a portion of the pad structure in the logic circuit region.

18. A semiconductor device, characterized in that: include: substrate; A pit formed on the substrate; a through hole, wherein the through hole is located in the pit; An isolation material stack is formed on the substrate, and the isolation material stack covers the surface of the substrate, the bottom surface and the side wall surface of the pit, and the side wall surface of the through hole.

19. The semiconductor device according to claim 18, characterized in that The insulating material stack comprises stacked layers of one or more of the following: Linear oxide layer, aluminum oxide layer, tantalum oxide layer, silicon oxide layer and silicon nitride layer.

20. The semiconductor device according to claim 18, wherein: The substrate has a logic circuit area and a pixel area, and the pit is formed on the back side of the substrate in the logic circuit area; The substrate comprises: Semiconductor substrate; A front isolation structure is formed on the front side of the semiconductor substrate, in the semiconductor substrate in the pixel region and the logic circuit region; A photodiode is formed in the semiconductor substrate in the pixel area, wherein the front isolation structure is used to isolate adjacent photodiodes.

21. The semiconductor device according to claim 20, characterized in that The substrate further comprises: A semiconductor component structure formed on the semiconductor substrate in the pixel area; A metal interconnect structure is formed on the semiconductor substrate in the pixel region and the logic circuit region, wherein the metal interconnect structure in the pixel region is electrically connected to the semiconductor component structure; A carrier wafer is bonded to the front side of the semiconductor substrate.

22. The semiconductor device according to claim 20, characterized in that The projection of the through hole on the front surface of the semiconductor substrate is located on the front isolation structure, and the through hole exposes the back surface of the front isolation structure.

23. The semiconductor device according to claim 20, characterized in that The semiconductor device further comprises: a grid-shaped back side isolation groove formed on the back side of the substrate in the pixel region, the back side isolation groove being used to isolate the adjacent photodiodes; Wherein, at least a portion of the isolation material stack is filled into the back side isolation trench.

24. The semiconductor device according to claim 23, characterized in that The isolation material stack comprises a stack of linear oxide layers, aluminum oxide layers, and tantalum oxide layers formed in sequence; Wherein, the stacked layer of the linear oxide layer, the aluminum oxide layer and the tantalum oxide layer is filled into the back isolation trench.

25. The semiconductor device according to claim 23, characterized in that The semiconductor device further includes a pad structure formed in the pit and the through hole, wherein the pad structure is electrically coupled to the metal interconnection structure on the front side of the substrate in the logic circuit region.

26. The semiconductor device according to claim 25, characterized in that The liner structure is a multi-layer structure; The semiconductor device further comprises: A grid structure is formed on the back side of the substrate in the pixel area, and the grid structure is a multi-layer structure; Wherein, on the back side of the substrate, the top surface of the pad structure is flush with the top surface of the grid structure.

27. The semiconductor device according to claim 26, characterized in that The semiconductor device further comprises: a filter formed in the grid structure of the pixel region; A microlens structure is formed on the grid structure in the pixel area and on a portion of the pad structure in the logic circuit area.

28. The semiconductor device according to claim 18, wherein: The total thickness of the linear oxide layer, the aluminum oxide layer and the tantalum oxide layer is selected from: 400A-800A.

29. The semiconductor device according to claim 18, wherein: The total thickness of the stacked layer of the silicon oxide layer and the silicon nitride layer is selected from: 1400A-2200A.

Images