Vertical nanosheet inverter structure manufacturing method and inverter structure

Abstract

The invention discloses a method for manufacturing a vertical nanosheet inverter structure. The method comprises the following steps: providing bulk silicon; executing a BPR process; forming a multi-layer stacked epitaxial structure; forming a vertical conductive channel; forming a grid electrode; forming an isolation side wall; manufacturing a first epitaxy at the bottom of the back surface of the device, manufacturing a second epitaxy at the bottom of the back of the device, wherein the second epitaxy is used for connecting two device source regions; forming an SOC layer; removing the top epitaxial layer; forming an interconnection dielectric layer; forming a top epitaxy; forming top epitaxial layer contact; the nanosheet is manufactured through the double patterns; forming a high dielectric constant insulator metal gate; and connecting the BPR and the bottom device drain region through the back contact hole, connecting the two device source regions through the back contact hole, connecting the top device drain region and the metal layer through the contact hole, and executing a back-end process. According to the invention, the physical size of the chip can be reduced, the process complexity of connecting the contact holes outside the multi-layer alternate stacking structure is reduced, the production and implementation are facilitated, and the miniaturization of the device is also facilitated.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a method for manufacturing a vertical nanosheet inverter structure and an inverter structure. Background Art

[0002] The vertical nanosheet inverter is an advanced semiconductor device structure that uses vertically arranged nanosheets as the channel of the transistor to achieve higher performance and smaller size. This structure has natural advantages in reducing the area of ​​standard cells, improving performance and improving parasitic effects. It can meet the design requirements of power consumption, performance, area and cost, and has become a key research and development direction for chips with 2nm and below technology nodes. In the structure of the vertical nanosheet inverter, the channel of the transistor is completely surrounded by the gate. This gate-all-around (GAA) structure has the advantages of high carrier mobility, avoiding polysilicon gate depletion and short channel effect. The vertical nanosheet inverter helps to reduce chip area, improve performance, reduce power consumption and cost by staggered stacking of N-type and P-type transistors in the vertical direction. This architecture allows more transistors to be accommodated in the same chip area while reducing the interconnection length between transistors, thereby increasing speed and reducing power consumption.

[0003] In order to achieve more efficient space utilization and performance improvement, especially in continuing to advance Moore's Law, the vertical nanosheet inverter structure has vertically alternating stacks of N-type complementary field effect transistors and P-type complementary field effect transistors. During production, it is necessary to connect the vertical conductive structures of different layers, so contact holes are required to achieve precise alignment, and then to achieve external connection of multiple layers of alternating stacks, which requires the use of complex contact hole processes. Complex contact hole processes are not conducive to production implementation and are not conducive to the miniaturization of devices. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention, which are all simplifications of the prior art in the field, and will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention of the present invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] The technical problem to be solved by the present invention is to provide a method for manufacturing a vertical nanosheet inverter structure and an inverter structure which can reduce the complexity of the contact hole connection process without affecting the device performance.

[0006] In order to solve the above technical problems, the present invention provides a method for manufacturing a vertical nanosheet inverter structure, comprising the steps of: S1, providing bulk silicon; S2, execute the BPR process; S3, forming a nanosheet multilayer stacked epitaxial structure S4, forming the vertical conductive channel of the nanosheet transistor; S5, forming a gate; S6, forming an isolation spacer to define the contours of the source region, the drain region, and the gate region of the transistor; S7, manufacturing the first epitaxial at the bottom of the back side of the device, the first epitaxial is used to connect the BPR; S8, forming a second epitaxial extension at the bottom of the back side of the device, the second epitaxial extension is used to connect two device source regions; S9, performing spin coating of SOC and SOC back etching to form a SOC layer; S10, removing the top epitaxial layer; S11, depositing an interconnection layer dielectric and etching back to form an interconnection dielectric layer; S12, forming top epitaxy; S13, forming a top epitaxial layer contact; S14, silicon germanium etching to make nanosheets via double patterning; S15, forming a high dielectric constant insulator metal gate; S16, connecting the BPR and the bottom device drain region through the back contact hole, connecting the two device source regions through the back contact hole, connecting the top device drain region and the metal layer through the contact hole, and performing the back-end process.

[0007] Preferably, the method for manufacturing the vertical nanosheet inverter structure is further improved, and when implementing step S3, a SiGe layer, a Si layer, a SiGe layer and Si epitaxy are used to form the multi-layer stacked epitaxial structure.

[0008] In semiconductor manufacturing, Nano-sheet (NS) SiGe / Si / SiGe / Si epi is an advanced process technology used to create multi-layer stacked structures with nanometer-scale thickness. This structure is commonly used in high-performance complementary metal oxide semiconductor (CMOS) devices, such as field effect transistors with vertical gates or gate-all-around (GAA) transistors.

[0009] Preferably, the method for manufacturing the vertical nanosheet inverter structure is further improved so that it can be used for process nodes less than or equal to 16 nm.

[0010] Preferably, the method for manufacturing the vertical nanosheet inverter structure is further improved so that it can be used in logic devices.

[0011] Preferably, the method for manufacturing the vertical nanosheet inverter structure is further improved, wherein the vertical nanosheet inverter structure is formed by vertically arranging two complementary field effect transistors with opposite type of doping.

[0012] In order to solve the above technical problems, the present invention provides a vertical nanosheet inverter structure. The other structures of the vertical nanosheet inverter structure are the same as those of the prior art and are not repeated here. The improvements are: a BPR is formed in the bulk silicon, and the BPR is connected to the bottom device drain region by a contact hole; the top device source region and the bottom device source region are connected by a contact hole; and the top device drain region is connected to the metal layer by a contact hole.

[0013] The vertical nanosheet inverter structure manufacturing method and the inverter structure provided by the present invention can reduce the physical size of the chip and reduce the process complexity of the contact hole external connection in the multi-layer alternating stacking structure through the combination of BPR and back contact hole connection process. In addition, the vertical nanosheet inverter structure manufacturing method and the inverter structure provided by the present invention are easy to produce and implement, and are also conducive to the miniaturization of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The drawings of the present invention are intended to illustrate the general characteristics of the methods, structures and / or materials used in specific exemplary embodiments of the present invention, and to supplement the description in the specification. However, the drawings of the present invention are schematic diagrams not drawn to scale, and thus may not accurately reflect the precise structure or performance characteristics of any given embodiment, and the drawings of the present invention should not be interpreted as limiting or restricting the range of values ​​or properties covered by the exemplary embodiments of the present invention. The present invention is further described in detail below in conjunction with the drawings and specific embodiments: Figure 1 It is a schematic diagram of the prior art process.

[0015] Figure 2 It is a schematic diagram of the process of the present invention.

[0016] Figure 3 It is a schematic diagram of the three-dimensional effect of the vertical nanosheet inverter structure provided by the present invention.

[0017] Figure 4 yes Figure 2 Schematic diagram of the cross section of the CUT position. DETAILED DESCRIPTION

[0018] The following is an explanation of the embodiments of the present invention by specific specific embodiments, and those skilled in the art can fully understand other advantages and technical effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and the details in this specification can also be applied based on different viewpoints, and various modifications or changes can be made without deviating from the general design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in a variety of different forms and should not be interpreted as being limited to the specific embodiments described here. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary specific embodiments to those skilled in the art. It should be understood that when an element is referred to as "connected" or "coupled" to another element, the element can be directly connected or coupled to another element, or there can be an intermediate element. The difference is that when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intermediate element. In all the drawings, the same reference numerals always represent the same elements.

[0019] First embodiment; refer to Figure 2 As shown, the present invention provides a method for manufacturing a vertical nanosheet inverter structure, comprising the steps of: S1, provides bulk silicon, Bulk Si; S2, perform BPR process, Buried Power Rail; BPR (Buried Power Rail) process is a special manufacturing technology in semiconductors used to achieve more efficient power distribution in integrated circuits (ICs). BPR technology improves the efficiency and performance of power distribution by creating power rails in the internal layers of silicon wafers; S3, forming a nanosheet multilayer stacked epitaxial structure, Nano-sheet (NS)SiGe / Si / SiGe / Si epi; the present invention uses SiGe / Si / SiGe / Si epi to make a multilayer stacked epitaxial structure; A nanosheet is a very thin layer of semiconductor material, with a thickness on the order of nanometers, that can be used to make more advanced transistors, such as gate-all-around transistors (GAAFETs).

[0020] "SiGe / Si / SiGe / Si epi" is a specific epitaxial structure in which silicon germanium and silicon layers are alternately stacked. This structure can be used to manufacture high-performance semiconductor devices such as high-speed transistors. By precisely controlling the thickness and composition of each layer, the electrical characteristics of the device, such as the mobility of carriers and the switching speed of the device, can be optimized.

[0021] S4, forming a vertical conductive channel of the nanosheet transistor; for example, removing the material covering the vertical silicon wafer of the nanosheet to facilitate subsequent gate formation; S5, forming a gate module; S6, forming isolation sidewalls, defining the outlines of the source region, drain region and gate region of the transistor, spacer and innerspacer; The isolation side wall includes Spacer (side wall) and Inner Spacer (inner wall); Spacer (sidewall) is a thin layer of material formed during the semiconductor manufacturing process, usually used to isolate and protect different parts of the transistor, such as the source, drain and gate. They are usually formed during the manufacturing process of the transistor by chemical vapor deposition (CVD) or atomic layer deposition (ALD) technology.

[0022] The sidewall material can be oxide, nitride or other insulating materials, which prevents short circuits between different parts and acts as a mask during ion implantation.

[0023] Inner Spacers are sidewall structures located inside a transistor, usually between the gate and source / drain. Inner spacers help define the channel length of a transistor because they form an isolation layer on either side of the gate, limiting the width of the channel.

[0024] During the manufacturing process, the steps for manufacturing the sidewalls and inner sidewalls typically include: Photolithography: Use photolithography to define the location of the sidewalls on the silicon wafer.

[0025] Etching: The sidewall grooves are formed in the silicon wafer through the etching process.

[0026] Deposition: Deposit sidewall material in the groove to form the desired sidewall structure.

[0027] Chemical Mechanical Polishing (CMP): Use CMP technology to flatten the surface of the silicon wafer and remove excess sidewall material.

[0028] S7, making the first epitaxial at the bottom of the back side of the device, the first epitaxial is used to connect to BPR, Back-side bottom Device epi contact; S8, making the second epitaxial at the bottom of the back side of the device, the second epitaxial is used to connect the two device source regions, Bottom Epi; S9, performing SOC spin coating and SOC etch back to form a SOC layer, SOC coating and SOC etch back; SOC stands for Spin on Carbon, which is a process used to form an insulating layer or hard mask.

[0029] SOC Coating: The process of coating a layer of SOC material on a semiconductor wafer. SOC is a material composed of carbon and is usually used as an insulating layer or hard mask in devices.

[0030] SOC Etch Back: refers to the process of removing part of the SOC layer by chemical or physical methods after SOC coating. The purpose of etch back is to accurately control the thickness of the SOC layer, or to remove unwanted SOC materials to form a specific device structure. The etch back process can be wet etching, using a specific chemical solution to dissolve the SOC material; it can also be dry etching, using plasma or ion beams to remove the SOC material.

[0031] S10, remove the top epitaxial layer, Top Epi removal; S11, depositing an interconnect layer dielectric and etching back to form an interconnect dielectric layer, ILD dep and etch back; Interconnect layer dielectric (ILD) is an insulating material used to isolate different metal layers in an integrated circuit to prevent electrical short circuits. The deposition of ILD can be performed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) or other deposition techniques.

[0032] Deposited interconnect layer etch back is the partial or complete removal of deposited material layers by chemical or physical methods, usually used to precisely control the thickness of dielectric layers or to form specific structures.

[0033] S12, forming a top epitaxial layer, Top Epi; the top epitaxial layer is a single crystal silicon layer grown on a semiconductor wafer, usually used to form the active area of ​​a transistor or a specific part of other electronic devices; S13, forming a top epitaxial layer contact, Top Epi contact, for forming a contact region electrically connected to the top epitaxial layer; S14, DPR and NS formation by SiGeetching; Double patterning is a lithography technique used in semiconductor manufacturing that allows two different patterns to be created in a single lithography step.

[0034] In the fabrication of nanosheet transistors, silicon germanium etching is used to precisely form the nanosheet structure, as well as to create the desired pattern in a double patterning technique.

[0035] S15, forming a high dielectric constant insulator metal gate, HKMG; S16, connect the BPR and the bottom device drain region through the back contact hole, connect the two device source regions through the back contact hole, connect the top device drain region and the metal layer through the contact hole, and perform the back-end process, BEoL. Finally, the Figure 3 and Figure 4 The device structure shown.

[0036] Alternatively, the first embodiment is formed by vertically arranging two complementary field effect transistors with opposite type doping, and can be used for logic devices with a process node of less than or equal to 16 nm.

[0037] Second embodiment; The present invention provides a vertical nanosheet inverter structure, and other structures of the vertical nanosheet inverter structure are the same as those of the prior art and will not be repeated here. The difference is that, Figure 2 Combination Figure 3 As shown, a BPR is formed in the bulk silicon, and the BPR is connected to the bottom device drain region by a contact hole; the top device source region and the bottom device source region are connected by a contact hole; and the top device drain region is connected to the connection metal layer by a contact hole.

[0038] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. It will also be understood that, unless expressly defined herein, terms such as those defined in general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not interpreted in an ideal or overly formal sense.

[0039] The present invention has been described in detail above through specific implementation modes and embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may also make many variations and improvements, which should also be regarded as the protection scope of the present invention.

Claims

1. A method for manufacturing a vertical nanosheet inverter structure, characterized in that: The steps include: S1, providing bulk silicon; S2, execute the BPR process; S3, forming a nanosheet multilayer stacked epitaxial structure; S4, forming the vertical conductive channel of the nanosheet transistor; S5, forming a gate; S6, forming an isolation spacer to define the contours of the source region, the drain region, and the gate region of the transistor; S7, manufacturing the first epitaxial at the bottom of the back side of the device, the first epitaxial is used to connect the BPR; S8, forming a second epitaxial extension at the bottom of the back side of the device, the second epitaxial extension is used to connect two device source regions; S9, performing spin coating of SOC and SOC back etching to form a SOC layer; S10, removing the top epitaxial layer; S11, depositing an interconnection layer dielectric and etching back to form an interconnection dielectric layer; S12, forming top epitaxy; S13, forming a top epitaxial layer contact; S14, silicon germanium etching to make nanosheets via double patterning; S15, forming a high dielectric constant insulator metal gate; S16, connecting the BPR and the bottom device drain region through the back contact hole, connecting the two device source regions through the back contact hole, connecting the top device drain region and the metal layer through the contact hole, and performing the back-end process.

2. The method for manufacturing a vertical nanosheet inverter structure according to claim 1, characterized in that: When performing step S3, the multi-layer stacked epitaxial structure is formed by using SiGe layer, Si layer, SiGe layer and Si epitaxy.

3. The method for manufacturing a vertical nanosheet inverter structure according to claim 1, characterized in that: It can be used in process nodes less than or equal to 16nm.

4. The method for manufacturing a vertical nanosheet inverter structure according to claim 3, characterized in that: It can be used in logic devices.

5. The method for manufacturing a vertical nanosheet inverter structure according to claim 1, characterized in that: It is formed by two complementary field effect transistors of opposite type doping arranged vertically.

6. A vertical nanosheet inverter structure, characterized in that: A BPR is formed in the bulk silicon, and the BPR is connected to the bottom device drain region through a contact hole; Its top device source region and bottom device source region are connected by a contact hole; The top device drain region is connected to the metal layer via a contact hole.

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