Radiation-resistant all-digital high-frequency low-level control system

Abstract

The invention discloses a radiation-resistant all-digital high-frequency low-level control system which is characterized in that the system can be arranged on an accelerator site with strong radiation and is used for solving the problem that signals are interfered due to the fact that the signal transmission distance is too long. According to the system, the functions of all peripheral chips which cannot work normally due to strong radiation on the accelerator site are included in the radiation-resistant FPGA chip, and the functions of all the external chips and the original functions of the radiation-resistant FPGA chip are achieved through the radiation-resistant FPGA chip. The system is realized by using a single radiation-resistant FPGA chip, a high-frequency digital control algorithm is realized through firmware program design of the radiation-resistant FPGA chip, the control function of a high-frequency low-level control system is met, and the radiation-resistant problem of the whole system is directly solved. The system can be placed on the site of an accelerator, breaks through the limitation that a transmission cable needs to penetrate through a wall, is closer to a controlled object, and does not need a radio frequency cable to penetrate through a pipeline in the wall.

Description

Technical Field

[0001] The invention belongs to the technical field of cyclotron accelerators, and in particular relates to a radiation-resistant full-digital high-frequency low-level control system. Background Art

[0002] During the operation of the cyclotron, the previous high-frequency low-level control system is usually arranged behind a shielded wall 30, 40 meters or even farther away from the accelerator site, and the high-frequency signal transmission cable of the system needs to be designed to pass through the wall, away from other components of the high-frequency system, especially the high-frequency resonant cavity. The longer transmission distance and cable through the wall design make the transmission distance of the high-frequency signal long and the loop delay of the entire high-frequency low-level control system large, resulting in a decrease in signal power and a decrease in signal-to-noise ratio, affecting the signal quality and system response speed. This requires the full digital high-frequency low-level control system to be directly arranged at the cyclotron site, thereby reducing the high-frequency signal loop delay and improving the system response speed.

[0003] The difficulty of placing the high-frequency low-level control system directly into the cyclotron site is that the complex working environment on site makes it difficult for the existing high-frequency low-level control system to maintain normal operation on the cyclotron site:

[0004] One of the reasons: During operation, the strong magnetic field of the cyclotron main magnet, the cyclotron radiation and neutron radiation generated by the particle accelerator and other factors may cause the chip used in the system to shift, deform or fail due to damage. These changes will directly cause the reliability and durability of the high-frequency low-level control system to decrease;

[0005] The second reason is that when working on-site at the cyclotron accelerator, the high-frequency signal detected by the high-frequency low-level control system will be subject to electromagnetic interference generated by various interference sources, such as stepper motors, vacuum pumps and ultra-low temperature refrigerators. These interferences will cause the quality of the high-frequency signal to deteriorate or the signal to be lost. Electromagnetic radiation will also cause the energy of the high-frequency signal to attenuate.

[0006] The third reason is: if the existing high-frequency, low-level control system adopts a radiation-resistant design, all chips need to be replaced with radiation-resistant chips, which makes system transformation and upgrading difficult and costly. Summary of the invention

[0007] In view of the deficiencies of the prior art, the present invention proposes a radiation-resistant all-digital high-frequency low-level control system, aiming to solve the problem that it is difficult to maintain normal operation when the high-frequency low-level control system is directly placed on-site at a cyclotron.

[0008] The present invention adopts the following technical solutions to solve the technical problems:

[0009] A radiation-resistant all-digital high-frequency low-level control system, characterized in that: the system can be deployed at an accelerator site with strong radiation to solve the problem of signal interference caused by long signal transmission distance; the system includes the functions of all peripheral chips that cannot work normally due to strong radiation at the accelerator site in a radiation-resistant FPGA chip, and uses the radiation-resistant FPGA chip to realize the functions of all external chips and its own original functions.

[0010] Furthermore, the use of a radiation-resistant FPGA chip to realize the functions of all external chips and its own original functions, that is, using 5 unidirectional inputs to the board and the radiation-resistant FPGA chip A / D conversion signals: drive signal, cavity voltage signal, forward power signal, motor indication signal and reflection signal, the 5 signals obtained after A / D conversion are transmitted to the FPGA chip, and a single radiation-resistant FPGA chip is used to realize a fully digital high-frequency low-level control system including all control functions of the external chip.

[0011] Furthermore, the use of a radiation-resistant FPGA chip to implement the functions of all external chips includes: using a newly designed clock distribution module inside the radiation-resistant FPGA chip to replace the clock distribution chip of the original system external chip, and the FPGA generates clock control signals for various components.

[0012] Furthermore, the use of a radiation-resistant FPGA chip to implement the functions of all external chips includes: using a newly designed phase comparator inside the radiation-resistant FPGA chip and the original two amplitude and phase demodulators to replace the analog phase detector of the original system external chip: specifically: adding an amplitude and phase demodulator to the external forward power signal, obtaining the phase information of the forward power signal from the amplitude and phase demodulator, and then passing the phase information to the phase comparator; retaining the amplitude and phase demodulation signal of the original cavity voltage signal, and then passing the phase information of the cavity voltage signal to the phase comparator.

[0013] Furthermore, the use of a radiation-resistant FPGA chip to implement the functions of all external chips includes: using a newly designed updated reflection protection function inside the radiation-resistant FPGA chip to replace the detector and comparator of the original system external chip; the radiation-resistant FPGA chip directly performs ADC sampling and demodulation on the external reflected signal to obtain its amplitude information, thereby replacing the external detector chip; and the newly designed reflection protection threshold inside the radiation-resistant FPGA replaces the comparator of the external chip.

[0014] Furthermore, a counter is newly added inside the radiation-resistant FPGA to count the number of times the reflection protection threshold is exceeded. When it is detected that the reflected signal exceeds the reflection protection threshold, the transmitter drive signal is quickly shut down.

[0015] Furthermore, the radiation-resistant FPGA chip, five ADC chips and one DAC chip are arranged in a system board; and the external signals are connected to the radiation-resistant FPGA chip through respective analog / digital conversion signals.

[0016] Furthermore, respective high-frequency filters are provided between the external drive signal, the cavity voltage signal, the forward power signal, the motor indication signal and the reflected signal and their respective ADCs.

[0017] Furthermore, the radiation-resistant FPGA chip outputs two external signals, which are a driving signal for the motor and a driving signal for the transmitter.

[0018] Furthermore, the radiation-resistant FPGA chip also includes a reference source, an amplitude PID controller, a phase PID controller, an amplitude and phase modulator, a tuning controller, a motor information readback module and a PWM driver; the reference source module uses the driving signal after analog / digital conversion inside the radiation-resistant FPGA chip as the reference source of the system, which is used to control the amplitude and phase modulator modules; the amplitude PID controller and the phase PID controller modules respectively perform PID operations on the amplitude information and phase information of the cavity voltage signal obtained by the amplitude and phase demodulators, and the operation results are input to the amplitude and phase modulator modules; the amplitude and phase demodulator module is controlled by the reference source module, and modulates the amplitude information and phase information after the PID operation, and the modulated signal is output as a transmitter drive signal through a DAC; the tuning controller module determines the tuning state of the accelerator resonant cavity according to the output signal of the phase comparator, and then controls the PWM driver module; the motor information readback module is used to process the real-time information of the stepper motor obtained from the motor indication signal; the PWM driver module is controlled by the motor information readback module and the tuning control module, and controls the speed and number of steps of the stepper motor by generating PWM waves with different duty cycles and frequencies, and the motor drive signal is output by the radiation-resistant FPGA chip.

[0019] Advantages and effects of the present invention

[0020] 1. The present invention uses a single radiation-resistant FPGA chip to realize a fully digital high-frequency low-level control system, and realizes a high-frequency digital control algorithm through the firmware program design of the radiation-resistant FPGA chip, which satisfies the control function of the high-frequency low-level control system and directly solves the radiation resistance problem of the entire system. The radiation-resistant fully digital high-frequency low-level control system can be placed at the accelerator site, breaking through the limitations of placing the system behind a shielded wall away from the accelerator site and the need for transmission cables to pass through the wall in order to reduce the impact of radiation, etc., and is closer to the controlled object and does not require RF cables to pass through pipes in the wall.

[0021] 2. Since the radiation-resistant all-digital high-frequency low-level control system is closer to the transmission distance of the resonant cavity, directional coupler and transmitter, the required RF cable length is shorter, the detected signal power is stronger, the signal-to-noise ratio is higher, the signal quality is improved, and the signal response speed is faster. The radiation-resistant all-digital high-frequency low-level control system is arranged near the cyclotron radiation field to reduce the loop delay of the system and improve the amplitude and phase stability margin of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a layout diagram of a high-frequency low-level system with a shielding wall in the prior art;

[0023] Figure 2 A layout diagram of a high-frequency low-level system that eliminates the shielding wall of the present invention;

[0024] Figure 3 This is a structural diagram of a high-frequency and low-level system based on a non-radiation-resistant FPGA chip in the prior art;

[0025] Figure 4 This is a structural diagram of a high-frequency, low-level system based on a radiation-resistant FPGA chip according to the present invention;

[0026] Figure 5 It is a schematic diagram of a high-frequency, low-level system based on a non-radiation-resistant FPGA chip in the prior art;

[0027] Figure 6 This is a schematic diagram of a high-frequency, low-level system based on a radiation-resistant FPGA chip of the present invention; DETAILED DESCRIPTION

[0028] Design principle of the present invention

[0029] 1. The innovation of the present invention: The innovation lies in the new software developed inside the radiation-resistant FPGA chip that can replace the external chip or external circuit, so that by adopting a radiation-resistant FPGA chip, all the hardware circuits or hardware chips inside and outside the original system FPGA that may be harmed by the strong radiation at the accelerator site are protected. The effect brought about is: a radiation-resistant FPGA chip becomes a protective shell or shielding cover for the entire all-digital high-frequency low-level control system. Since the parts of the entire all-digital high-frequency low-level control system that are easily radiated by the accelerator site are all moved from outside the FPGA to inside the FPGA, the entire all-digital high-frequency low-level control system can be placed at the accelerator site, solving the problem that the long transmission distance and the cable through the wall design make the transmission distance of the high-frequency signal long, the loop delay of the entire all-digital high-frequency low-level control system is large, resulting in a decrease in signal power, a decrease in signal-to-noise ratio, and an impact on signal quality and system response speed.

[0030] 2. The solution of the present invention:

[0031] New clock distribution modules, phase comparators, and reflection protection thresholds are designed inside the radiation-resistant FPGA chip, and these modules are organically combined with related modules inside the FPGA of the original system, thus achieving a smooth transition from FPGA external chips or external circuits to FPGA internal modules.

[0032] Based on the above invention principle, the present invention designs a radiation-resistant all-digital high-frequency low-level control system, such as Figure 2 , Figure 4 , Figure 6 As shown, its characteristics are: the system can be deployed at an accelerator site with strong radiation to solve the problem of signal interference caused by long signal transmission distance; the system includes the functions of all peripheral chips that cannot work normally due to strong radiation at the accelerator site in a radiation-resistant FPGA chip, and uses a radiation-resistant FPGA chip to realize the functions of all external chips and its own original functions.

[0033] Supplementary Note 1: Layout comparison before and after improvement

[0034] 1) Figure 1 and Figure 2 This is a comparison chart before and after the improvement. Figure 1 This is the layout diagram of the "high-frequency low-level system" before improvement; the "high-frequency low-level system" is placed at the far end. Figure 2 This is the layout diagram of the improved "high-frequency low-level system resistant to strong magnetic fields and strong radiation". Figure 1 There is a shielding wall in the middle. The signal of the high-frequency low-level system first passes through the transmitter and then through the shielding wall before reaching the accelerator resonant wall. Figure 2 In the process, there is no shielding wall between the transmitter and the accelerator. A "high-frequency, low-level system resistant to strong magnetic fields and strong radiation" is placed at the accelerator site. This system transmits signals directly to the accelerator's resonant cavity through the transmitter.

[0035] Supplementary Note 2: Relationship between the original system FPGA and external chip

[0036] From the following relationship between the original system FPGA and external chips, it can be seen that after the improvement, all the external chips of the original system have been moved inside the FPGA.

[0037] 1) The driving signal is transmitted to the FPGA chip through the ADC and used as a reference source for the amplitude and phase modulators inside the FPGA chip. The driving signal is also input into the clock distribution chip after being limited and amplified by the analog circuit. The chip is purchased from a third party, such as the AD9520 chip. The clock distribution chip generates clock control signals for various components of the original high-frequency and low-level control system.

[0038] 2) The cavity voltage signal is transmitted to the FPGA chip through the ADC, and the amplitude and phase demodulators are implemented inside the FPGA chip. The demodulator obtains the amplitude and phase information of the resonant cavity voltage and inputs them into the amplitude and phase modulators through the amplitude PID controller and the phase PID controller respectively. The signal output by the modulator is passed through the DAC to obtain a high-frequency signal, i.e., the output signal.

[0039] 3) The phase difference between the cavity voltage signal and the forward power signal is obtained by using an analog phase detector. The output value of the phase detector is transmitted to the tuning controller of the FPGA chip through the ADC to determine the tuning state of the cavity. The tuning controller is used to control the PWM driver. The phase detector circuit consists of two limiting amplifiers, two triggers, and one XOR gate. The limiting amplifier can select the AD8306 chip, the trigger can select the MC10EP16D chip, and the XOR gate can select the MC10EL107D chip.

[0040] 4) The motor indication signal is transmitted to the FPGA chip through the ADC. The FPGA chip generates PWM waves with different duty cycles and frequencies to control the speed and number of steps of the stepper motor according to the motor information readback and the tuning state of the cavity, and outputs the motor drive signal through a high-frequency low-level control system.

[0041] 5) The reflected signal passes through the detector to obtain its envelope, and then passes through the comparator to input the ADC to the FPGA chip for reflection protection. When the reflection is too large, the reflection protection shuts off the output signal. The detector can be implemented by the RF detector ADL5511 chip, and the comparator is implemented by the window comparator circuit.

[0042] like Figure 6 As shown, a radiation-resistant FPGA chip is used to realize the functions of all external chips and its own original functions, that is, five unidirectional analog / digital conversion signals are input to the board and the radiation-resistant FPGA chip: a drive signal, a cavity voltage signal, a forward power signal, a motor indication signal and a reflection signal, and the five analog / digital converted signals are transmitted to the FPGA chip, and a single radiation-resistant FPGA chip is used to realize a fully digital high-frequency low-level control system including all control functions of the external chip.

[0043] like Figure 6 As shown, the functions of all external chips are realized by using a radiation-resistant FPGA chip, including: using a newly designed clock distribution module inside the radiation-resistant FPGA chip to replace the clock distribution chip of the original system external chip, and the FPGA generates clock control signals for each component.

[0044] like Figure 6As shown, the functions of all external chips are realized by using a radiation-resistant FPGA chip, including: using a newly designed phase comparator inside the radiation-resistant FPGA chip and the original two amplitude and phase demodulators to replace the analog phase detector of the external chip of the original system: specifically: adding an amplitude and phase demodulator to the external forward power signal, obtaining the phase information of the forward power signal by the amplitude and phase demodulator, and then passing the phase information to the phase comparator; retaining the amplitude and phase demodulation signal of the original cavity voltage signal, and then passing the phase information of the cavity voltage signal to the phase comparator.

[0045] like Figure 6 As shown, the functions of all external chips are realized by using a radiation-resistant FPGA chip, including: using the updated reflection protection function newly designed inside the radiation-resistant FPGA chip to replace the detector and comparator of the original system external chip; the radiation-resistant FPGA chip directly performs ADC sampling and demodulation on the external reflection signal to obtain its amplitude information, thereby replacing the external detector chip; the reflection protection threshold newly designed inside the radiation-resistant FPGA replaces the comparator of the external chip.

[0046] like Figure 6 As shown, a new counter is added inside the radiation-resistant FPGA to count the number of times the reflection protection threshold is exceeded. When it is detected that the reflected signal exceeds the reflection protection threshold, the transmitter drive signal is quickly turned off.

[0047] like Figure 6 As shown, the radiation-resistant FPGA chip, 5 ADC chips and 1 DAC chip are arranged in the system board; the external signals are connected to the radiation-resistant FPGA chip through their respective analog / digital conversion signals.

[0048] like Figure 6 As shown, respective high-frequency filters are provided between the external drive signal, the cavity voltage signal, the forward power signal, the motor indication signal and the reflected signal and their respective ADCs.

[0049] like Figure 6 As shown, the radiation-resistant FPGA chip outputs two external signals, namely a driving signal for the motor and a driving signal for the transmitter.

[0050] like Figure 6As shown, the radiation-resistant FPGA chip also includes a reference source, an amplitude PID controller, a phase PID controller, an amplitude and phase modulator, a tuning controller, a motor information readback module and a PWM driver; the reference source module uses the driving signal after analog / digital conversion inside the radiation-resistant FPGA chip as the reference source of the system to control the amplitude and phase modulator modules; the amplitude PID controller and the phase PID controller modules respectively perform PID operations on the amplitude information and phase information of the cavity voltage signal obtained by the amplitude and phase demodulators, and the operation results are input to the amplitude and phase modulator modules; the amplitude and phase demodulator modules are controlled by the reference source module to modulate the amplitude information and phase information after the PID operation, and the modulated signal is output as a transmitter drive signal through the DAC; the tuning controller module determines the tuning state of the accelerator resonant cavity according to the output signal of the phase comparator, and then controls the PWM driver module; the motor information readback module is used to process the real-time information of the stepper motor obtained from the motor indication signal; the PWM driver module is controlled by the motor information readback module and the tuning control module, and controls the speed and number of steps of the stepper motor by generating PWM waves with different duty cycles and frequencies, and the motor drive signal is output by the radiation-resistant FPGA chip.

[0051] It should be emphasized that the above specific embodiments are merely explanations of the present invention, and they are not limitations of the present invention. After reading this specification, those skilled in the art can make modifications to the above embodiments without any creative contribution as needed, but as long as they are within the scope of the claims of the present invention, they are protected by patent law.

Claims

1. A radiation-resistant all-digital high-frequency low-level control system, characterized in that: The system can be deployed at accelerator sites with strong radiation to solve the problem of signal interference caused by long signal transmission distance; the system includes the functions of all peripheral chips that cannot work normally at the accelerator site due to strong radiation in a radiation-resistant FPGA chip, and uses a radiation-resistant FPGA chip to realize the functions of all external chips and its own original functions.

2. A radiation-resistant all-digital high-frequency low-level control system according to claim 1, characterized in that: The method uses a radiation-resistant FPGA chip to realize the functions of all external chips and its own original functions, that is, using 5 unidirectional analog / digital conversion signals input to the board and the radiation-resistant FPGA chip: drive signal, cavity voltage signal, forward power signal, motor indication signal and reflection signal, and transmitting the 5 signals obtained after analog / digital conversion to the FPGA chip, and using a single radiation-resistant FPGA chip to realize a fully digital high-frequency low-level control system including all control functions of external chips.

3. A radiation-resistant all-digital high-frequency low-level control system according to claim 1, characterized in that: The method of using a radiation-resistant FPGA chip to realize the functions of all external chips includes: using a newly designed clock distribution module inside the radiation-resistant FPGA chip to replace the clock distribution chip of the original system external chip, and the FPGA generates clock control signals for various components.

4. A radiation-resistant all-digital high-frequency low-level control system according to claim 1, characterized in that: The method uses a radiation-resistant FPGA chip to realize the functions of all external chips, including: using a newly designed phase comparator inside the radiation-resistant FPGA chip and the original two amplitude and phase demodulators to replace the analog phase detector of the external chip of the original system: specifically: adding an amplitude and phase demodulator to the external forward power signal, obtaining the phase information of the forward power signal from the amplitude and phase demodulator, and then passing the phase information to the phase comparator; retaining the amplitude and phase demodulation signal of the original cavity voltage signal, and then passing the phase information of the cavity voltage signal to the phase comparator.

5. A radiation-resistant all-digital high-frequency low-level control system according to claim 1, characterized in that: The method of using a radiation-resistant FPGA chip to implement the functions of all external chips includes: using a newly designed updated reflection protection function inside the radiation-resistant FPGA chip to replace the detector and comparator of the original system external chip; the radiation-resistant FPGA chip directly performs ADC sampling and demodulation on the external reflected signal to obtain its amplitude information, thereby replacing the external detector chip; and a newly designed reflection protection threshold inside the radiation-resistant FPGA to replace the comparator of the external chip.

6. A radiation-resistant all-digital high-frequency low-level control system according to claim 5, characterized in that: A new counter is added inside the radiation-resistant FPGA to count the number of times the reflection protection threshold is exceeded. When the reflected signal is detected to exceed the reflection protection threshold, the transmitter drive signal is quickly shut down.

7. A radiation-resistant all-digital high-frequency low-level control system according to claim 2, characterized in that: The radiation-resistant FPGA chip, five ADC chips and one DAC chip are arranged in a system board; the external signals are connected to the radiation-resistant FPGA chip through respective analog / digital conversion signals.

8. A radiation-resistant all-digital high-frequency low-level control system according to claim 7, characterized in that: Respective high-frequency filters are provided between the external drive signal, the cavity voltage signal, the forward power signal, the motor indication signal and the reflected signal and their respective ADCs.

9. A radiation-resistant all-digital high-frequency low-level control system according to claim 7, characterized in that: The radiation-resistant FPGA chip outputs two external signals, namely a driving signal for the motor and a driving signal for the transmitter.

10. The radiation-resistant all-digital high-frequency low-level control system according to claim 1, characterized in that: The radiation-resistant FPGA chip also includes a reference source, an amplitude PID controller, a phase PID controller, an amplitude and phase modulator, a tuning controller, a motor information readback module and a PWM driver; The reference source module uses the driving signal after analog / digital conversion inside the radiation-resistant FPGA chip as the reference source of the system to control the amplitude and phase modulator modules; the amplitude PID controller and the phase PID controller modules respectively perform PID operations on the amplitude information and phase information of the cavity voltage signal obtained by the amplitude and phase demodulators, and the operation results are input to the amplitude and phase modulator modules; The amplitude and phase demodulator module is controlled by the reference source module, and modulates the amplitude information and phase information after PID operation. The modulated signal is output as the transmitter drive signal through the DAC; the tuning controller module determines the tuning state of the accelerator resonant cavity according to the output signal of the phase comparator, and then controls the PWM driver module; The motor information readback module is used to process the real-time information of the stepper motor obtained from the motor indication signal; the PWM driver module is controlled by the motor information readback module and the tuning control module, and controls the speed and number of steps of the stepper motor by generating PWM waves with different duty cycles and frequencies, and the motor drive signal is output by the radiation-resistant FPGA chip.

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