Preparation method of organic thin film transistor and organic thin film transistor
By making the gate electrode on the insulated substrate of the organic thin film transistor, and imprinting the semiconductor layer with a preset solvent and a flexible mold, combining deposition and annealing operations, the problem of semiconductor material damage in the prior art is solved, and high-quality organic thin film transistor preparation is achieved.
Patent Information
- Application Number
- CN202411130627.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-16
- Publication Date
- 2025-03-14
AI Technical Summary
The prior art is difficult to avoid damage to semiconductor materials during the multi-layer stamping process of organic thin film transistors, affecting the quality of preparation.
The semiconductor layer and conductive layer are prepared by making a gate electrode on the insulating substrate and preparing a dielectric layer on its surface, and imprinting is performed using a preset solvent and a flexible mold, and the semiconductor layer is protected in combination with deposition and annealing operations.
The preparation of organic thin film transistors through multi-layer imprinting technology is realized, avoiding damage to the semiconductor layer and improving the reliability and quality of the preparation process.
Smart Images
Figure CN119630247A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of organic photoelectric materials, and in particular to a method for preparing an organic thin film transistor and an organic thin film transistor. Background Art
[0002] Organic thin film transistor (OTFT) is a thin film transistor that uses organic matter as a semiconductor material. It is mostly used on plastic substrates. Due to its characteristics of being rollable and having low process costs, it has become the most promising new array board technology for the next generation of flexible displays. The production method of organic thin film transistors is simpler than that of traditional inorganic thin film transistors. It has very low requirements for the conditions and purity of the film-forming atmosphere. Since the cost of solution-printed organic thin film transistors is relatively low, it has aroused great interest among researchers.
[0003] However, the existing technical means have great difficulties in realizing multi-layer imprinting of organic thin film transistors, because plasma cleaning of semiconductor materials is required during the imprinting process, and this process usually causes damage to the semiconductor materials. Therefore, it is necessary to propose a method for preparing an organic thin film transistor, which can realize the preparation of an organic thin film transistor through multi-layer imprinting technology while avoiding damage to the semiconductor layer during the preparation process. Summary of the invention
[0004] The present application provides a method for preparing an organic thin film transistor and an organic thin film transistor, aiming to realize the preparation of the organic thin film transistor by multi-layer imprinting technology while avoiding damage to the semiconductor layer during the preparation process.
[0005] To achieve the above object, the present application provides a method for preparing an organic thin film transistor, comprising:
[0006] Providing an insulating substrate, and forming a gate electrode on the insulating substrate;
[0007] Preparing a dielectric layer on the surfaces of the insulating substrate and the gate electrode;
[0008] A semiconductor layer is prepared on the surface of the dielectric layer by embossing with a preset solvent and a flexible mold, and a charge injection layer is deposited on the semiconductor layer, wherein the preset solvent includes at least 4-vinylphenol and polyvinyl pyrrolidone;
[0009] A conductive layer is formed on the surface of the charge injection layer by pressing.
[0010] Optionally, the step of preparing the semiconductor layer on the surface of the dielectric layer by using a preset solvent and a flexible mold for printing comprises:
[0011] Dropping the preset solvent on the surface of the electrolyte layer, and imprinting the preset solvent with the flexible mold;
[0012] After the preset solvent evaporates, removing the flexible mold to obtain a negative structure of the semiconductor layer;
[0013] The negative structure of the semiconductor layer is deposited and annealed, and the preset solvent is dissolved to obtain the semiconductor layer.
[0014] Optionally, the depositing and annealing operations on the negative structure of the semiconductor layer include:
[0015] Performing a primary annealing on the negative structure of the semiconductor layer at 120° C. to obtain a primary annealed negative structure of the semiconductor layer;
[0016] Adding a water suspension dropwise to the negative structure of the semiconductor layer after the primary annealing for deposition to obtain the negative structure of the semiconductor layer after deposition;
[0017] The negative structure of the deposited semiconductor layer was annealed again at 120°C.
[0018] Optionally, depositing a charge injection layer on the semiconductor layer comprises:
[0019] Depositing the charge injection layer on the semiconductor layer by at least one of thermal evaporation, magnetron sputtering, atomic layer deposition, and pulsed laser deposition;
[0020] Wherein, the charge injection layer includes at least one of molybdenum oxide, aluminum oxide, magnesium oxide, lithium oxide, lithium fluoride, and magnesium fluoride.
[0021] Optionally, the step of preparing a conductive layer by embossing on the surface of the charge injection layer comprises:
[0022] Dropping the preset solvent on the surface of the charge injection layer, and imprinting the preset solvent with the flexible mold;
[0023] After the preset solvent evaporates, removing the flexible mold to obtain a negative structure of the conductive layer;
[0024] The negative structure of the conductive layer is deposited and annealed, and the preset solvent is dissolved to obtain the conductive layer.
[0025] Optionally, the insulating substrate includes a silicon wafer, glass or plastic film with an insulating film; the material of the gate electrode includes one of gold, platinum, silver, copper, nickel, aluminum, titanium, iron and chromium metal conductive materials, or PEDOT:PSS conductive organic matter, or conductive oxide.
[0026] Optionally, the dielectric layer is prepared by atomic layer deposition ALD technology.
[0027] Optionally, the semiconductor layer is one of the organic semiconductor materials selected from the group consisting of pentacene, tetracene, copper phthalocyanine, a polymer of 3-hexylthiophene, thiophene and rubrene.
[0028] To achieve the above-mentioned purpose, the present application also provides an organic thin film transistor, which is prepared by the method according to claims 1 to 9, comprising: an insulating substrate, a gate electrode, a dielectric layer, a semiconductor layer, a charge injection layer and a conductive layer; wherein:
[0029] The insulating substrate is located at the bottom layer of the organic thin film transistor; the gate electrode is located on the upper surface of the insulating substrate; the dielectric layer covers the insulating substrate and the gate electrode; the semiconductor layer is located on the upper surface of the dielectric layer; the charge injection layer covers the dielectric layer and the semiconductor layer; and the conductive layer is located on the upper surface of the charge injection layer.
[0030] The present application discloses a method for preparing an organic thin film transistor and an organic thin film transistor. The method includes: providing an insulating substrate and making a gate electrode on the insulating substrate; preparing a dielectric layer on the surface of the insulating substrate and the gate electrode; preparing a semiconductor layer on the surface of the dielectric layer by embossing with a preset solvent and a flexible mold, and depositing a charge injection layer on the semiconductor layer, wherein the preset solvent includes at least 4-vinylphenol and polyvinyl pyrrolidone; and preparing a conductive layer by embossing on the surface of the charge injection layer. Compared with the prior art, the present application realizes the preparation of an organic thin film transistor by multi-layer embossing technology while avoiding damage to the semiconductor layer during the preparation process. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0032] Figure 1 It is a schematic flow chart of a method for preparing an organic thin film transistor provided in an embodiment of the present application;
[0033] Figure 2 It is a schematic diagram of a process for preparing a semiconductor layer provided in an embodiment of the present application;
[0034] Figure 3 This is a schematic diagram of a scenario for preparing a semiconductor layer provided in an embodiment of the present application;
[0035] Figure 4It is a schematic diagram of a semiconductor layer imprinting process provided by an embodiment of the present application;
[0036] Figure 5 a is a schematic structural diagram of a negative structure of a semiconductor layer provided in an embodiment of the present application;
[0037] Figure 5 b is a schematic diagram of the structure of a semiconductor layer provided in an embodiment of the present application;
[0038] Figure 6 It is a schematic flow chart of another method for preparing an organic thin film transistor provided in an embodiment of the present application;
[0039] Figure 7 It is a schematic diagram of the structure of an organic thin film transistor provided in an embodiment of the present application. DETAILED DESCRIPTION
[0040] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0041] The flowcharts shown in the accompanying drawings are only examples and do not necessarily include all the contents and operations / steps, nor do they have to be executed in the order described. For example, some operations / steps can also be decomposed, combined or partially merged, so the actual execution order may change according to actual conditions. In addition, although the functional modules are divided in the device schematic, in some cases, the module division can be different from that in the device schematic.
[0042] Reference to "embodiment" in this application means that a particular feature, structure or characteristic described in conjunction with the embodiment may be included in at least one embodiment of this application. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments.
[0043] The term "and / or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
[0044] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.
[0045] See also Figure 1 , Figure 1FIG. 1 is a schematic diagram of a method for preparing an organic thin film transistor provided in an embodiment of the present application. Figure 1 As shown, the preparation of the organic thin film transistor can be achieved through steps S11 to S14.
[0046] Step S11: providing an insulating substrate and forming a gate electrode on the insulating substrate.
[0047] Among them, the insulating substrate includes a silicon wafer, glass or plastic film with an insulating film; the material of the gate electrode includes one of gold, platinum, silver, copper, nickel, aluminum, titanium, iron and chromium metal conductive materials, or PEDOT:PSS conductive organic matter, or conductive oxide, which is not limited in this application.
[0048] Furthermore, the gate electrode is prepared by vacuum thermophysical deposition, electron beam deposition or sputtering of metal electrodes, inkjet printing or spin coating of organic electrodes, etc., which is not limited in the present application.
[0049] Step S12: preparing a dielectric layer on the surface of the insulating substrate and the gate electrode.
[0050] The dielectric layer can be prepared by atomic layer deposition (ALD) technology. In addition, BCB polymer can be deposited by solution method (spin coating, scraping) before depositing the dielectric layer to make the surface of the dielectric layer flat.
[0051] Step S13: preparing a semiconductor layer on the surface of the dielectric layer by embossing with a preset solvent and a flexible mold, and depositing a charge injection layer on the semiconductor layer.
[0052] The preset solvent includes at least 4-vinylphenol and polyvinylpyrrolidone; the flexible mold may be a PDMS mold. This application takes the preset solvent as 4-vinylphenol (its concentration may be 30 mg / ml to 100 mg / ml) and the flexible mold as a PDMS mold as an example for explanation.
[0053] The semiconductor layer is one of pentacene, tetracene, copper phthalocyanine, a polymer of 3-hexylthiophene, thiophene and rubrene organic semiconductor materials, which is not limited in the present application.
[0054] It should be noted that the PDMS mold can be prepared in the following manner: spin-coating a photoresist on a silicon wafer, and then using photolithography to prepare a desired structure on the photoresist (as an example, the structure on the photoresist here is a circular hole array); pouring an appropriate amount of commercial polydimethylsiloxane (PDMS) precursor (SYLGARD 184) on the structured photoresist surface, curing at 70°C for 1 hour, and then peeling off the PDMS and the photoresist to obtain a PDMS mold with a cylindrical array.
[0055] See also Figure 2 as well as Figure 3 , Figure 2 is a schematic diagram of a process for preparing a semiconductor layer provided in an embodiment of the present application; Figure 3 Schematic diagram of a scenario for preparing a semiconductor layer provided in an embodiment of the present application. Figure 2 As shown, the semiconductor layer can be prepared through steps S131 to S133.
[0056] Step S131: dripping a preset solvent onto the surface of the electrolyte layer, and imprinting the preset solvent with a flexible mold.
[0057] Step S132: After the preset solvent evaporates, the flexible mold is removed to obtain a negative structure of the semiconductor layer.
[0058] Specifically, the 4-vinylphenol solvent may be dripped onto the surface of the electrolyte layer, and then the PDMS mold may be gently pressed onto the 4-vinylphenol solvent. Alternatively, the 4-vinylphenol solvent may be dripped onto the surface of the PDMS mold, and then the electrolyte layer and the PDMS mold may be gently pressed face to face, which is not limited in the present application. Furthermore, the PDMS mold soaked with the solvent may be placed together with the electrolyte layer on a special fixture (such as Figure 4 The fixture has the function of adjusting the pressure. A small pressure (such as ~5Mpa) is applied to ensure that the PDMS mold is in close contact with the bottom of the electrolyte layer. The entire device is placed in a fume hood to evaporate the solvent for half an hour. The PDMS mold is removed to obtain the negative structure of the semiconductor layer (such as Figure 5 as shown in a).
[0059] Optionally, if the bottom of the negative structure of the semiconductor layer obtained above is not clean enough, the negative structure of the semiconductor layer may be lightly treated with plasma (such as oxygen plasma) to clean the bottom.
[0060] Step S133: performing deposition and annealing operations on the negative structure of the semiconductor layer, and dissolving a preset solvent to obtain a semiconductor layer.
[0061] Optionally, the negative structure of the semiconductor layer is deposited and annealed, including: initially annealing the negative structure of the semiconductor layer at 120°C to obtain the negative structure of the semiconductor layer after the initial annealing; adding a water suspension to the negative structure of the semiconductor layer after the initial annealing for deposition to obtain the negative structure of the deposited semiconductor layer; and annealing the negative structure of the deposited semiconductor layer again at 120°C.
[0062] Specifically, the negative structure of the prepared semiconductor layer is annealed at 120° C. in air to obtain the negative structure of the semiconductor layer after the initial annealing. Then, a water suspension (such as a water suspension of P3HT nanoparticles) is dripped onto the surface of the negative structure of the semiconductor layer after the initial annealing for spin coating to achieve deposition. Further, the negative structure of the deposited semiconductor layer can be used to enhance the adhesion between semiconductor particles and between semiconductor particles and the substrate. Finally, the 4-vinylphenol solvent can be dissolved to obtain a semiconductor layer (such as Figure 5 b).
[0063] Based on the above embodiments, a charge injection layer is deposited on the semiconductor layer, including: depositing the charge injection layer on the semiconductor layer by at least one of thermal evaporation, magnetron sputtering, atomic layer deposition, and pulsed laser deposition; wherein the charge injection layer includes at least one of molybdenum oxide, aluminum oxide, magnesium oxide, lithium oxide, lithium fluoride, and magnesium fluoride.
[0064] It should be noted that the charges injected by the charge injection layer may be holes or electrons. The charge injection layer may protect the structured functional layer during subsequent plasma treatment.
[0065] Step S14: preparing a conductive layer by embossing on the surface of the charge injection layer.
[0066] A conductive layer is prepared by imprinting on the surface of a charge injection layer, comprising: dripping a preset solvent on the surface of the charge injection layer, and imprinting the preset solvent with a flexible mold; after the preset solvent evaporates, removing the flexible mold to obtain a negative structure of the conductive layer; depositing and annealing the negative structure of the conductive layer, and dissolving the preset solvent to obtain a conductive layer.
[0067] Specifically, the 4-vinylphenol solvent can be dripped onto the surface of the charge injection layer, and then the PDMS mold can be gently pressed onto the 4-vinylphenol solvent. Alternatively, the 4-vinylphenol solvent can be dripped onto the surface of the PDMS mold, and then the charge injection layer and the PDMS mold can be gently pressed face to face, which is not limited in the present application. Further, the PDMS mold soaked with the solvent can be placed on a special fixture together with the charge injection layer, and the entire device can be placed in a fume hood to volatilize the solvent for half an hour, and the PDMS mold can be removed to obtain the negative structure of the conductive layer.
[0068] Further, the prepared negative structure of the conductive layer is annealed at 120° C. in air to obtain the negative structure of the conductive layer after the initial annealing. Then, a water suspension (such as a water suspension of P3HT nanoparticles) is dripped onto the surface of the negative structure of the conductive layer after the initial annealing for spin coating to achieve deposition. Further, the negative structure of the deposited conductive layer can be used to enhance the adhesion between the particles of the conductive layer and between the particles of the conductive layer and the substrate. Finally, the 4-vinylphenol solvent can be dissolved to obtain the conductive layer.
[0069] Optionally, after obtaining the negative structure of the conductive layer, it also includes: cleaning the negative structure of the conductor by plasma to obtain the negative structure of the cleaned conductive layer; performing deposition and annealing operations on the negative structure of the conductive layer, and dissolving a preset solvent to obtain a conductive layer, including: performing deposition and annealing operations on the negative structure of the cleaned conductive layer, and dissolving a preset solvent to obtain a conductive layer.
[0070] Specifically, since a thin film of process material will remain on the side of the negative structure of the conductive layer during the preparation process, the negative structure of the conductive layer can be lightly cleaned by plasma (such as oxygen plasma) to remove the residual process material around the negative structure of the conductive layer.
[0071] The method for preparing an organic thin film transistor disclosed in the embodiment of the present application includes: providing an insulating substrate, and making a gate electrode on the insulating substrate; preparing a dielectric layer on the surface of the insulating substrate and the gate electrode; preparing a semiconductor layer on the surface of the dielectric layer by embossing with a preset solvent and a flexible mold, and depositing a charge injection layer on the semiconductor layer, wherein the preset solvent includes at least 4-vinylphenol and polyvinyl pyrrolidone; and preparing a conductive layer by embossing on the surface of the charge injection layer. Compared with the prior art, the present application realizes the preparation of an organic thin film transistor by multi-layer embossing technology while avoiding damage to the semiconductor layer during the preparation process.
[0072] See also Figure 7 , Figure 7 The organic thin film transistor 100 provided in the present application includes an insulating substrate 10 , a gate electrode 20 , a dielectric layer 30 , a semiconductor layer 40 , a charge injection layer 50 and a conductive layer 60 .
[0073] The insulating substrate 10 is located at the bottom layer of the organic thin film transistor 100; the gate electrode 20 is located on the insulating substrate 10; the dielectric layer 30 covers the insulating substrate 10 and the gate electrode 20; the semiconductor layer 40 is located on the upper surface of the dielectric layer 30; the charge injection layer 50 covers the dielectric layer 30 and the semiconductor layer 40; and the conductive layer 60 is located on the upper surface of the charge injection layer 50.
[0074] It should be noted that the various optional implementations introduced in the embodiments of the present application can be implemented in combination with each other or can be implemented separately, and the embodiments of the present application are not limited to this.
[0075] In the description of the present application, it should be understood that the terms "upper", "lower", "left", "right", etc. indicate orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, and a specific orientation structure and operation. Therefore, it cannot be understood as a limitation on the present application. In addition, "first" and "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, "multiple" means two or more.
[0076] The above embodiments are described with reference to the accompanying drawings. Other different forms and embodiments are also feasible without departing from the principles of the present application, so the present application should not be constructed as a limitation of the embodiments proposed herein. More specifically, these embodiments are provided so that the present application will be perfect and complete, and the scope of the present application will be conveyed to those skilled in the art. In the accompanying drawings, the component sizes and relative sizes may be exaggerated for clarity. The terms used herein are only based on the purpose of describing specific embodiments and are not intended to be limiting. The terms "comprising" and / or "including" when used in this specification indicate the presence of the features, integers, components and / or components but do not exclude the presence or increase of one or more other feature integers, components, components and / or their groups. Unless otherwise indicated, when stated, the numerical range includes the upper and lower limits of the range and any sub-ranges therebetween.
[0077] The above descriptions are only some embodiments of the present application, and do not limit the protection scope of the present application. Any equivalent device or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.
Claims
1. A method for preparing an organic thin film transistor, characterized in that: include: Providing an insulating substrate, and forming a gate electrode on the insulating substrate; Preparing a dielectric layer on the surfaces of the insulating substrate and the gate electrode; A semiconductor layer is prepared on the surface of the dielectric layer by embossing with a preset solvent and a flexible mold, and a charge injection layer is deposited on the semiconductor layer, wherein the preset solvent includes at least 4-vinylphenol and polyvinyl pyrrolidone; A conductive layer is formed on the surface of the charge injection layer by pressing.
2. The method according to claim 1, characterized in that The method of preparing a semiconductor layer on the surface of the dielectric layer by using a preset solvent and a flexible mold for printing comprises: Dropping the preset solvent on the surface of the electrolyte layer, and imprinting the preset solvent with the flexible mold; After the preset solvent evaporates, removing the flexible mold to obtain a negative structure of the semiconductor layer; The negative structure of the semiconductor layer is deposited and annealed, and the preset solvent is dissolved to obtain the semiconductor layer.
3. The method according to claim 2, characterized in that The depositing and annealing operations on the negative structure of the semiconductor layer include: performing a primary annealing on the negative structure of the semiconductor layer at 120° C. to obtain a negative structure of the semiconductor layer after primary annealing; Adding a water suspension dropwise to the negative structure of the semiconductor layer after the primary annealing for deposition to obtain the negative structure of the semiconductor layer after deposition; The negative structure of the deposited semiconductor layer was annealed again at 120°C.
4. The method according to claim 1, characterized in that: The step of depositing a charge injection layer on the semiconductor layer comprises: Depositing the charge injection layer on the semiconductor layer by at least one of thermal evaporation, magnetron sputtering, atomic layer deposition, and pulsed laser deposition; Wherein, the charge injection layer includes at least one of molybdenum oxide, aluminum oxide, magnesium oxide, lithium oxide, lithium fluoride, and magnesium fluoride.
5. The method according to claim 2, characterized in that: The step of preparing the conductive layer by embossing on the surface of the charge injection layer comprises: Dropping the preset solvent on the surface of the charge injection layer, and imprinting the preset solvent with the flexible mold; After the preset solvent evaporates, removing the flexible mold to obtain a negative structure of the conductive layer; The negative structure of the conductive layer is deposited and annealed, and the preset solvent is dissolved to obtain the conductive layer.
6. The method according to claim 5, characterized in that After obtaining the negative structure of the conductive layer, the method further comprises: Cleaning the negative structure of the conductor by plasma to obtain the negative structure of the cleaned conductive layer; The negative structure of the conductive layer is deposited and annealed, and the preset solvent is dissolved to obtain the conductive layer, comprising: The negative structure of the cleaned conductive layer is subjected to deposition and annealing operations, and the preset solvent is dissolved to obtain the conductive layer.
7. The method according to claim 1, characterized in that The insulating substrate includes a silicon wafer, glass or plastic film with an insulating film; the material of the gate electrode includes one of gold, platinum, silver, copper, nickel, aluminum, titanium, iron and chromium metal conductive materials, or PEDOT:PSS conductive organic matter, or conductive oxide.
8. The method according to claim 1, characterized in that The dielectric layer is prepared by using atomic layer deposition ALD technology.
9. The method according to claim 1, characterized in that: The semiconductor layer is one of pentacene, tetracene, copper phthalocyanine, a polymer of 3-hexylthiophene, thiophene and rubrene organic semiconductor materials.
10. An organic thin film transistor prepared by the method according to claims 1 to 9, characterized in that: include: insulating substrate, gate electrode, dielectric layer, semiconductor layer, charge injection layer and conductive layer; wherein, The insulating substrate is located at the bottom layer of the organic thin film transistor; the gate electrode is located on the upper surface of the insulating substrate; the dielectric layer covers the insulating substrate and the gate electrode; the semiconductor layer is located on the upper surface of the dielectric layer; the charge injection layer covers the dielectric layer and the semiconductor layer; and the conductive layer is located on the upper surface of the charge injection layer.