Low-noise infrared detector reading circuit

Abstract

The invention provides a low-noise infrared detector reading circuit. The low-noise infrared detector reading circuit comprises an integral input module, a sampling and holding module, a source follower module, a column-level switched capacitor module and an analog-to-digital conversion module which are connected in sequence, the sampling and holding module is used for sampling the two voltage signals output by the integral input module twice according to the time difference of sampling pulses; wherein a voltage value before integration is sampled for one time and a voltage value after integration is sampled for the other time; controlling the time difference between two times of pulse sampling to enable the noise at the two points to be the same; and the voltage obtained by two times of sampling is subjected to difference calculation processing through the column-level switched capacitor module, and is finally output through the analog-to-digital conversion module. The infrared detector reading circuit can solve the technical problems that an existing infrared detector reading circuit is not low enough in noise and not large enough in dynamic range.

Description

Technical Field

[0001] The invention relates to the technical field of infrared detector readout circuits, and in particular to a low-noise infrared detector readout circuit. Background Art

[0002] Infrared detection technology uses the difference in infrared radiation energy between the detection target and the imaging background to enable people to obtain information that cannot be directly obtained by the naked eye. Infrared detectors can be used for temperature control, fire prevention and machine vision systems, body temperature monitoring and disease diagnosis, monitoring greenhouse gas emissions, etc. As the performance requirements for infrared detectors increase, the requirements for the dynamic range of the detector readout circuit are also increased. The dynamic range is greatly affected by circuit noise. Reducing circuit noise can effectively improve the dynamic range.

[0003] Therefore, there is an urgent need for a circuit structure that can reduce noise and use it in an infrared detector readout circuit to increase the dynamic range of the readout circuit. Summary of the invention

[0004] In view of the shortcomings of the prior art, the present invention proposes a low-noise infrared detector readout circuit to solve the technical problems in the prior art that the infrared detector readout circuit has insufficient noise and insufficient dynamic range.

[0005] The technical solution adopted by the present invention is as follows:

[0006] In a first aspect, a low-noise infrared detector readout circuit is provided, comprising: an integral input module, a sample-and-hold module, a source follower module, a column-level switch capacitor module, and an analog-to-digital conversion module connected in sequence;

[0007] The integral input module is used to integrate and reset the input photocurrent to obtain two voltage signals;

[0008] The sampling and holding module is used to sample the two voltage signals output by the integral input module twice according to the time difference of the sampling pulses; one sampling is the voltage value before the integration, and the other sampling is the voltage value at the end of the integration; the time difference of the two sampling pulses is controlled to make the noise at the two points the same; the voltages obtained by the two samplings are then subjected to difference calculation processing through the column-level switch capacitor module, and finally output through the analog-to-digital conversion module.

[0009] Furthermore, the integral input module includes a photodiode, an operational transconductance amplifier, two transmission gate switches S1 and S2, and two capacitors C1 and C2.

[0010] Furthermore, the sample-and-hold module includes a transmission gate switch S3 and a capacitor C3.

[0011] Furthermore, the source follower module includes NMOS tubes M1 and M2.

[0012] Furthermore, the column-level switch capacitor module includes capacitors C4 and C5, NMOS switches S5 and S6, a transmission gate switch S4 and a second operational amplifier.

[0013] Furthermore, the column-level switch capacitor module works in the following manner: when Vpix samples the reset voltage, first open switches S4 and S5 to obtain the charge Q4 stored on capacitor C4 and the charge Q5 stored on capacitor C5; when Vpix samples the integral voltage, turn off switches S4 and S5, open switch S6, the charge Q4' stored on capacitor C4 and the charge Q5' stored on capacitor C5, the sum of Q4 and Q5 is equal to the sum of Q4' and Q5', and the output voltage is the difference between the two voltages; the noise voltage and the offset voltage cancel each other out, eliminating the noise and voltage offset.

[0014] Furthermore, the analog-to-digital conversion module is a SAR ADC with a resolution of 10 bits and a speed of 20 Mbps.

[0015] Furthermore, the low-noise infrared detector readout circuit is of array type, and the control signal includes a row selection signal and a column selection signal.

[0016] In a second aspect, a low-noise infrared detector is provided, which uses the low-noise infrared detector readout circuit described in the first aspect to read the input photocurrent signal, integrate it to obtain a voltage signal, and then sequentially read it out as a digital signal.

[0017] It can be seen from the above technical solution that the beneficial technical effects of the present invention are as follows:

[0018] 1. The circuit structure adopts a single switch capacitor sampling at the pixel level, followed by a source follower, and then connected to a column-level switch capacitor circuit as a subtractor, which can save more area and use the extra area for a larger sampling capacitor, which can suppress KT / C noise. At the same time, the column-level subtractor is placed after the source follower, which can eliminate the fixed pattern noise brought by the source follower when the existing circuit structure is adopted, further reduce the circuit noise, improve the signal-to-noise ratio, and increase the dynamic range of the readout circuit.

[0019] 2. Perform two samplings based on the time difference of the sampling pulses; one sampling is the voltage value before integration, and the other sampling is the voltage value at the end of integration; the time difference of the two sampling pulses is controlled to make the noise at the two points the same, and then the voltages obtained from the two samplings are processed by difference calculation through the column-level switching capacitor module, which can eliminate reset noise and suppress low-frequency noise, and can significantly improve the circuit signal-to-noise ratio.

[0020] 3. The offset voltage Vos and circuit noise Vnoise of the second operational amplifier remain unchanged during the two samplings. The noise voltage and offset voltage cancel each other out, eliminating the noise and voltage offset. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for the specific embodiments or the prior art description. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn according to the actual scale.

[0022] Figure 1 A schematic diagram of the structure of a low-noise infrared detector readout circuit according to an embodiment of the present invention;

[0023] Figure 2 A schematic diagram of the structure of a two-stage operational amplifier used in an embodiment of the present invention;

[0024] Figure 3 This is a schematic diagram of the structure of an improved switched capacitor module according to an embodiment of the present invention;

[0025] Figure 4 This is a schematic diagram of the working sequence of each switch in an embodiment of the present invention;

[0026] Figure 5 Schematic diagram of voltage / time correspondence when the readout circuit according to an embodiment of the present invention is working. DETAILED DESCRIPTION

[0027] The following embodiments of the technical solution of the present invention are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and are therefore only used as examples, and cannot be used to limit the protection scope of the present invention.

[0028] It should be noted that, unless otherwise specified, the technical terms or scientific terms used in this application should have the common meanings understood by those skilled in the art to which the present invention belongs.

[0029] Example

[0030] This embodiment provides a low-noise infrared detector readout circuit, such as Figure 1 As shown, it includes an integral input module, a sampling and holding module, a source follower module, a column-level switch capacitor module and an analog-to-digital conversion module (ADC module) connected in sequence. The details are as follows:

[0031] 1. Integral input module

[0032] The integral input module is used to integrate the input photocurrent and reset after the integration is completed to obtain two voltage signals; it includes a photodiode, an operational transconductance amplifier (OTA), two transmission gate switches S1 and S2, and two capacitors C1 and C2. In a specific implementation:

[0033] The positive input terminal of the operational transconductance amplifier is connected to the bandgap reference voltage source Vref, and the negative input terminal is connected to the cathode of the photodiode, giving the photodiode a constant reverse bias voltage.

[0034] The transmission gate switch S2 is connected between the input and output terminals of the operational transconductance amplifier as a reset switch. After the integration is completed, S2 is opened to reset the voltage at the output terminal of the operational transconductance amplifier to the Vref value.

[0035] C1 is used as an integrating capacitor. The upper board of the capacitor is connected to the output of the operational amplifier, and the lower board is connected to the negative input of the operational transconductance amplifier. The capacitance of C1 is smaller than that of C2, and it is suitable for passive searchlighting. At this time, the light signal is weak and the photocurrent generated is smaller. A small capacitor is used to integrate it to increase the dynamic range.

[0036] The transmission gate switch S1 and capacitor C2 are connected in series, the upper board of capacitor C2 is connected to the output of the operational amplifier, the lower board is connected to the output of switch S1, and the input of switch S1 is connected to the negative input of the operational transconductance amplifier. Switch S1 and capacitor C2 are suitable for active searchlighting. When switch S1 is turned on, C1 and C2 are connected in parallel, and the equivalent integral capacitor is larger. At this time, the light signal is strong and the photocurrent is larger. A large capacitor is used to integrate it to prevent charge capacity saturation and increase the dynamic range.

[0037] The circuit structure of the integral input module is used in the input stage of the low-noise infrared detector readout circuit, and has the advantages of high injection efficiency, high linearity, stable bias, and large dynamic range. The test data shows that when the op amp gain is greater than 80dB, the injection efficiency can reach 99% and the linearity can reach 99%. The positive input of the operational transconductance amplifier is connected to the bandgap reference voltage, which can provide a stable bias that hardly changes with temperature for the infrared detector. The high output swing of the operational transconductance amplifier can provide a wide dynamic range for the readout circuit.

[0038] 2. Sample and hold module

[0039] The sample and hold module is used to sample the two voltage signals output by the integral input module.

[0040] In a specific implementation: the sampling and holding module includes a transmission gate switch S3 and a capacitor C3. The input end of the switch S3 is connected to the output end of the operational transconductance amplifier; the upper plate of the capacitor C3 is connected to the output end of the switch S3 and the gate of the source follower NMOS tube M1, and the lower plate is grounded. The Vint voltage is sampled by closing or opening the S3 switch. Specifically, S3 is closed before the reset switch S2 is about to be closed, and the voltage at the end of the integration is sampled; it is opened again after the reset is disconnected, and the voltage at a short time point after the integration is just started is sampled. The two voltage values ​​are subsequently subtracted to obtain the integrated voltage value.

[0041] 3. Source Follower Module

[0042] In a specific implementation, the source follower module includes NMOS tubes M1 and M2;

[0043] The gate of the NMOS tube M1 is connected to the upper plate of the capacitor C3, the drain is connected to the working voltage VDD, and the source is connected to the source of the NMOS tube M2;

[0044] The gate of the NMOS tube M2 is connected to the row control signal ROW, and the drain is connected to the column bus and the upper plate of the capacitor C4;

[0045] Among them, ROW is used as a row selection switch to control the voltage on the sampling capacitor C3 to be input to the subtractor.

[0046] 4. Column-level switched capacitor module

[0047] In a specific implementation, the column-level switch capacitor module includes capacitors C4 and C5, NMOS switches S5 and S6, a transmission gate switch S4, and a second operational amplifier.

[0048] The upper plate of capacitor C4 is connected to the column bus, and the lower plate is connected to the negative input terminal of the second operational amplifier;

[0049] The positive input terminal of the second operational amplifier is grounded, and the output terminal is connected to the analog-to-digital conversion module;

[0050] The transmission gate switch S4 is connected across the input terminal and the output terminal of the second operational amplifier;

[0051] The lower plate of capacitor C5 is connected to the negative input terminal of the second operational amplifier, and the upper plate is connected to the source of NMOS switches S5 and S6;

[0052] The drain of the NMOS switch S5 is grounded, and the gate is connected to the control signal;

[0053] The gate of the NMOS switch S6 is connected to the control signal, and the drain is connected to the output end of the transmission gate switch S4 and the output end of the second operational amplifier.

[0054] In a specific implementation, the control signal connected to the gate of switches S5 and S6 is a voltage signal applied to the gate of the NMOS tube. When the gate voltage is high (ie, VDD), the switch is opened, and when the gate voltage is low (ie, GND), the switch is opened.

[0055] 5. Analog-to-digital conversion module

[0056] In a specific implementation, the analog-to-digital conversion module (ADC module) is composed of a 10-bit, 20M SAR ADC, which reads the Vcds signal sequentially as a digital signal, and then obtains the image signal through DSP processing. As a chip-level ADC, the SAR ADC must meet the speed and accuracy requirements of the readout circuit. 20M corresponds to the readout circuit speed requirement, that is, the readout time of each pixel is no more than 50ns, and 10bit corresponds to the accuracy requirement of the readout circuit, that is, the minimum voltage value that can be distinguished is 1mV.

[0057] Figure 1 The dotted box in the figure indicates that the circuit structure in the dotted box is a circuit module that each pixel has, because the entire infrared detector readout circuit is column-level.

[0058] The synergistic effects of the above-mentioned module circuits are as follows: the integral input module can reduce the noise of the readout circuit, because the subtractor of the column-level switch capacitor module is placed at the column level, and a single pixel has only one sampling capacitor, the integral capacitor of the integral input module can be set larger, and the KT / C noise of the switch capacitor can become smaller; at the same time, the integral capacitor of the integral input module is Miller equivalent, and the capacitance equivalent to the input end is (1+Av)Cint, which can suppress the input noise; the input-stage operational transconductance amplifier of the integral input module has a large gain, and the injection efficiency can reach 99%, which can also suppress the fluctuation noise of the current signal.

[0059] Compared with the circuit structures of other existing infrared detection readout circuits, the circuit structure of this embodiment adopts a single switch capacitor sampling at the pixel level, followed by a source follower, and then connected to a column-level switch capacitor circuit as a subtractor, which can save more area and use the extra area for a larger sampling capacitor, which can suppress KT / C noise. At the same time, the column-level subtractor is placed after the source follower, which can eliminate the fixed pattern noise brought by the source follower when the prior art circuit structure is adopted, further reduce circuit noise, improve signal-to-noise ratio, and increase the dynamic range of the readout circuit.

[0060] The low-noise infrared detector readout circuit provided in this embodiment can not only eliminate reset noise, but also suppress low-frequency noise, and can significantly improve the circuit signal-to-noise ratio. In the same circuit, the noise has a certain correlation in time, and its working principle is: in a signal output cycle, two short pulses are applied to the readout circuit, and the output signal is sampled twice by controlling the two pulses, one of which is located at the beginning of the output signal, one sampling voltage value before integration; the other sampling voltage value at the end of integration; as long as the time difference between the two sampling pulses is properly controlled, the noise at the two sampling time points can be made the same or almost the same. After that, it is only necessary to perform difference calculation on the voltage obtained from the two samples through a subtractor to suppress most of the 1 / f noise, obtain the actual effective amplitude of the signal level, and further improve the dynamic range of the circuit.

[0061] In some embodiments, reference Figure 2 , is the circuit structure of the operational transconductance amplifier in the integral input module and the second operational amplifier in the column-level switch capacitor module, hereinafter referred to as the secondary operational amplifier. The left side of the secondary operational amplifier is the bias circuit of the operational amplifier. M9 and M11 are common source and common gate structures, which effectively suppress the channel length modulation effect. M7, M8, M10, and M12 are self-biased current mirrors. The resistor R is added to provide a stable operating point for the current mirror, and the bias circuit provides a stable current source for the secondary operational amplifier. The middle is a five-tube OTA structure, M19 and M20 are differential input tubes of the operational amplifier, M3 and M4 are first-stage load tubes, M0 is a tail current source tube, and the drain of M2 is the first-stage output terminal. M5 and M6 tubes are the second stage of the operational amplifier, M6 is the second-stage input tube, M5 is the second-stage load tube, and the drain of M6 is the second-stage output terminal. M13 and capacitor Cc are Miller compensation structures, which separate the primary and secondary poles of the operational amplifier, increase the phase margin of the operational amplifier, and improve the stability of the operational amplifier. A secondary operational amplifier is provided in the entire circuit to provide high gain and higher bandwidth to meet the readout circuit design requirements.

[0062] In some embodiments, reference Figure 3 The working principle of the column-level switch capacitor module is as follows: when Vpix samples the reset voltage, first open the S4 and S5 switches, and the charge stored on the capacitor C4 can be obtained as Q4=C4(Vrst+Vnoise―Vos―Vref), and the charge stored on the capacitor C5 can be obtained as Q5=C5(Vos). When Vpix samples the integral voltage, turn off S4 and S5, and open S6. The charge stored on the capacitor C4 is Q4'=C4(Vsig+Vnoise―Vos―Vref), and the charge stored on the capacitor C5 is Q5'=C5(Vcds―Vos―Vref). According to the principle of charge conservation, Q4+Q5=Q4'+Q5', and the output voltage can be obtained as the difference between the two sampling voltages, that is, Vcds=Vref―(Vsig―Vrst), realizing the subtraction effect. At the same time, the offset voltage Vos and the circuit noise Vnoise of the second operational amplifier remain unchanged during the two samplings. According to the charge conservation principle, the noise voltage Vnoise and the offset voltage Vos cancel each other out, thereby eliminating the noise and voltage offset.

[0063] To facilitate understanding of the working sequence of the low-noise infrared detector readout circuit of this embodiment, an example is given: Figure 4, is a timing control diagram of each switch. The sampling switch S3 is turned off after a short time after the reset switch S2 is turned off. At this time, the capacitor C3 stores the reset voltage Vrst and enters the integration state; the ROW switch is opened before the sampling switch S3 is closed, and the switches S4 and S5 are opened at the same time. At this time, the Vpix voltage is the reset voltage Vrst sampled on the capacitor C3; the sampling switch S3 is closed a short time before the reset switch S2 is closed. At this time, the voltage sampled on the capacitor C3 is the integrated voltage value Vsig, and the switch ROW is kept closed. The switch S6 is also closed after the sampling switch S3 is closed. At this time, the Vpix voltage value is the integrated voltage value Vsig. Through the action of the subtractor, Vcds is the voltage value of the subtraction between the two voltages Vsig and Vrst, which is transmitted to the SAR ADC for analog-to-digital conversion to convert the input current signal into a digital signal.

[0064] In some embodiments, the low-noise infrared detector readout circuit of this embodiment may be of array type, and the control signal includes a row selection signal and a column selection signal.

[0065] The low-noise infrared detector readout circuit of this embodiment has a voltage / time correspondence relationship when working as follows: Figure 5 shown.

[0066] This embodiment also provides a low-noise infrared detector, which uses the low-noise infrared detector readout circuit described above to read the input photocurrent signal, integrate it to obtain a voltage signal, and then sequentially read it out as a digital signal.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. These modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be included in the scope of the claims and specification of the present invention.

Claims

1. A low-noise infrared detector readout circuit, characterized in that: include: An integral input module, a sample-and-hold module, a source follower module, a column-level switch capacitor module and an analog-to-digital conversion module connected in sequence; The integral input module is used to integrate and reset the input photocurrent to obtain two voltage signals; The sampling and holding module is used to sample the two voltage signals output by the integration input module twice according to the time difference of the sampling pulses; one sampling is the voltage value before the integration, and the other sampling is the voltage value at the end of the integration; the time difference of the two sampling pulses is controlled so that the noise of the two sampling points is the same; the voltage obtained by the two samplings is then subjected to difference calculation processing through the column-level switch capacitor module, and finally output through the analog-to-digital conversion module.

2. The low-noise infrared detector readout circuit according to claim 1, characterized in that: The integral input module includes a photodiode, an operational transconductance amplifier, two transmission gate switches S1 and S2, and two capacitors C1 and C2.

3. The low-noise infrared detector readout circuit according to claim 1, characterized in that: The sample-and-hold module includes a transmission gate switch S3 and a capacitor C3.

4. The low-noise infrared detector readout circuit according to claim 1, characterized in that: The source follower module includes NMOS tubes M1 and M2.

5. The low-noise infrared detector readout circuit according to claim 1, characterized in that: The column-level switch capacitor module includes capacitors C4 and C5, NMOS switches S5 and S6, a transmission gate switch S4 and a second operational amplifier.

6. The low-noise infrared detector readout circuit according to claim 5, characterized in that: The column-level switch capacitor module works in the following manner: when Vpix samples the reset voltage, switches S4 and S5 are first opened to obtain a charge Q4 stored on capacitor C4 and a charge Q5 stored on capacitor C5; When Vpix samples the integrated voltage, switches S4 and S5 are turned off, and switch S6 is turned on. The charge stored on capacitor C4 is Q4', and the charge stored on capacitor C5 is Q5'. The sum of Q4 and Q5 is equal to the sum of Q4' and Q5', and the output voltage is the difference between the two voltages. The noise voltage and the offset voltage cancel each other out, eliminating the noise and voltage offset.

7. The low-noise infrared detector readout circuit according to claim 1, characterized in that: The analog-to-digital conversion module is a SAR ADC with a 10-bit and 20-M speed.

8. The low-noise infrared detector readout circuit according to claim 1, characterized in that: The low-noise infrared detector readout circuit is of array type, and the control signal includes a row selection signal and a column selection signal.

9. A low-noise infrared detector, characterized in that: The low-noise infrared detector readout circuit according to any one of claims 1 to 8 is used to read the input photocurrent signal, integrate it to obtain a voltage signal, and then sequentially read it out as a digital signal.

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