Semiconductor process method

Abstract

The invention provides a semiconductor process method. The semiconductor process method comprises the following steps: sequentially forming a hard mask layer and a patterned photoresist layer on a layer to be etched; taking the patterned photoresist layer as a mask, and etching the hard mask layer by adopting a dry etching process to form a groove for exposing the layer to be etched; wherein in the dry etching, a silicon coating is arranged in a reaction chamber, direct current voltage is applied to the silicon coating, the silicon coating is reverse voltage, and the silicon coating is bombarded by plasma to release silicon which is attached to the upper surface of the patterned photoresist layer to form a protective layer so as to protect the patterned photoresist layer. Through the arrangement of the direct-current silicon coating, the protective layer is formed on the patterned photoresist layer to protect the patterned photoresist layer, the patterned photoresist layer is prevented from being damaged in dry etching, and meanwhile, the patterned photoresist layer is modified and hardened, so that the consumption of high-energy bombardment on the vertex angle of the patterned photoresist layer can be resisted, and the service life of the patterned photoresist layer is prolonged. And generation of stripes on the side wall of the groove is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a semiconductor process method. Background Art

[0002] SI-CAP (silicon capacitor) has an operating voltage of 5V. Its size after photoresist exposure is smaller than other products. Therefore, when etching the hard mask layer with the exposed photoresist as a mask, the plasma energy bombardment makes the top right angle of the photoresist easy to be damaged and the side is easy to cause depression to form a stripe-like morphology. After etching the hard mask layer, Figure 1 As shown in the figure, through the measurement results of the key dimensions, the sidewall A of the hard mask layer 11 shows uneven stripe morphology, and the FA (failure analysis) slice results also show that the sidewall has many stripe morphologies. The existence of sidewall stripes will cause the same stripe morphology to be formed when the hard mask layer is used as a mask to etch the etched layer, and when the oxide layer or other materials are filled in the subsequent process, the material filling will be incomplete, affecting the electrical parameters of the device.

[0003] The existing solution is to etch the hard mask layer in the traditional way of opening the hard mask layer by using higher power and lower pressure, which is mainly to make the ions open the hard mask layer by high-speed impact under the premise of maintaining a higher average free energy. In this way of etching, the stripes on the side wall produced by the ions bombarding downward at high speed are deep and difficult to eliminate, and more polymers are easily produced. Especially in the case of low exposure rate, the polymers are not easy to remove and adhere to the side wall surface, which increases the difficulty of eliminating the stripes.

[0004] Therefore, how to reduce or avoid the generation of stripe morphology on the sidewall when etching the hard mask layer to form a groove is a technical problem that those skilled in the art need to solve urgently. Summary of the invention

[0005] The object of the present invention is to provide a semiconductor process method for solving the problem of stripe morphology in the etching process of a hard mask layer in the prior art.

[0006] In order to solve the above technical problems, the present invention provides a semiconductor process method, comprising the following steps:

[0007] sequentially forming a hard mask layer and a patterned photoresist layer on the layer to be etched;

[0008] Using the patterned photoresist layer as a mask, a dry etching process is used to etch the hard mask layer to form a groove exposing the layer to be etched; wherein,

[0009] In the dry etching, a silicon coating is arranged in a reaction chamber, a DC voltage is applied to the silicon coating, and the silicon coating is a reverse voltage. The silicon coating is bombarded by plasma and the released silicon adheres to the upper surface of the patterned photoresist layer to form a protective layer to protect the patterned photoresist layer.

[0010] Optionally, during the dry etching, the low-frequency power of the lower electrode is less than or equal to 3000W.

[0011] Optionally, during the dry etching, the low-frequency power of the lower electrode is between 1000W and 3000W.

[0012] Optionally, during the dry etching, the pressure in the reaction chamber is between 10mT and 100mT, and the low-frequency power of the upper electrode is between 250W and 800W.

[0013] Optionally, the voltage applied to the silicon coating is between 100V and 400V.

[0014] Optionally, in the dry etching, the reaction gas includes an etching gas and a dilution gas, the etching gas includes at least one of CF4, CH2F2, CHF3 or C4F8, and the dilution gas includes N2 or Ar.

[0015] Optionally, the flow rate of the reaction gas is between 5 sccm and 1500 sccm.

[0016] Optionally, the reaction gas also includes O2.

[0017] Optionally, O2 is introduced into the reaction chamber through two pipes, the flow rate of O2 in the first pipe is between 5 sccm and 30 sccm, and the flow rate of O2 in the second pipe is between 5 sccm and 200 sccm.

[0018] Optionally, the material of the hard mask layer includes silicon dioxide, and the material of the layer to be etched includes silicon.

[0019] Compared with the prior art, the technical solution of the present invention has at least the following technical effects:

[0020] In the semiconductor process method provided by the present invention, in the process of dry etching a hard mask layer with a patterned photoresist layer as a mask to form a groove exposing a layer to be etched, a silicon coating is arranged in a reaction chamber, a DC voltage is applied to the silicon coating, and the silicon coating is a reverse voltage. The silicon coating is bombarded with ions to release silicon to adhere to the upper surface of the patterned photoresist layer to form a protective layer. The silicon material is denser than the photoresist, and can well protect the patterned photoresist layer to avoid the patterned photoresist layer being damaged during dry etching; at the same time, the electrons released by the silicon coating modify and harden the patterned photoresist layer to resist the consumption of the top corner of the patterned photoresist layer by high-energy bombardment, so that the patterned photoresist layer can well protect the hard mask layer below it, thereby avoiding the generation of groove sidewall stripes.

[0021] In addition, during dry etching, the low-frequency power of the lower electrode is less than or equal to 3000 W. Compared with the prior art, the low-frequency power of the lower electrode is reduced, thereby reducing the free energy of the plasma and the intensity of bombarding the hard mask layer, which can reduce the rate of polymer production and the breadth of the distribution range and reduce the loss of the top corner of the patterned photoresist layer, thereby further avoiding the generation of groove sidewall stripes. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a microscopic magnified view of the structure in which stripes are formed on the side wall after dry etching of the hard mask layer in the prior art.

[0023] Figure 2 It is a flow chart of a semiconductor process method provided by one embodiment of the present invention.

[0024] Figures 3 to 5 It is a schematic diagram of the structure of each step of a semiconductor process method provided by an embodiment of the present invention.

[0025] Figure 6 It is a microscopic magnified view of the structure with smooth side walls after dry etching of the hard mask layer in the semiconductor process method of the present application.

[0026] Description of reference numerals:

[0027] 10 - layer to be etched; 11 - hard mask layer; 12 - patterned photoresist layer; 13 - groove; 14 - silicon coating; 15 - protective layer. DETAILED DESCRIPTION

[0028] In view of the above technical problems, the present invention provides a semiconductor process method, in which a patterned photoresist layer is used as a mask, and a hard mask layer is dry-etched to form a groove exposing a layer to be etched. A silicon coating is arranged in a reaction chamber, a DC voltage is applied to the silicon coating, and the silicon coating is a reverse voltage. The silicon coating is bombarded with ions to release silicon that adheres to the upper surface of the patterned photoresist layer to form a protective layer. The silicon material is denser than the photoresist, and can well protect the patterned photoresist layer to avoid the patterned photoresist layer being damaged during dry etching; at the same time, the electrons released by the silicon coating modify and harden the patterned photoresist layer to resist the consumption of the top corners of the patterned photoresist layer by high-energy bombardment, so that the patterned photoresist layer can well protect the hard mask layer below it, thereby avoiding the generation of groove sidewall stripes.

[0029] In addition, during dry etching, the low-frequency power of the lower electrode is less than or equal to 3000 W. Compared with the prior art, the low-frequency power of the lower electrode is reduced, thereby reducing the free energy of the plasma and the intensity of bombarding the hard mask layer, which can reduce the rate of polymer production and the breadth of the distribution range and reduce the loss of the top corner of the patterned photoresist layer, thereby further avoiding the generation of groove sidewall stripes.

[0030] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0031] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, unless the content clearly indicates otherwise. As used in the present invention, the term "or" is generally used in a sense that includes "and / or", unless the content clearly indicates otherwise. As used in the present invention, the term "several" is generally used in a sense that includes "at least one", unless the content clearly indicates otherwise. As used in the present invention, the term "at least two" is generally used in a sense that includes "two or more", unless the content clearly indicates otherwise. In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0032] Figure 2 FIG. 1 is a flow chart of a semiconductor process method provided by an embodiment of the present invention. Figure 2 As shown, the semiconductor process method provided in this embodiment includes the following steps:

[0033] S1: forming a hard mask layer and a patterned photoresist layer in sequence on the layer to be etched;

[0034] S2: Using the patterned photoresist layer as a mask, a dry etching process is used to etch the hard mask layer to form a groove exposing the layer to be etched; wherein, during the dry etching, a silicon coating is arranged in a reaction chamber, a DC voltage is applied to the silicon coating, and the silicon coating is a reverse voltage, and the silicon coating is bombarded by plasma to release silicon that adheres to the upper surface of the patterned photoresist layer to form a protective layer to protect the patterned photoresist layer.

[0035] Figures 3 to 5 FIG. 1 is a schematic diagram of the structure of each step of a semiconductor process method provided by an embodiment of the present invention. Figure 2 , Figures 3 to 5 The semiconductor process method provided by the embodiment of the present invention is described in detail.

[0036] In step S1, refer to Figure 3 As shown, a hard mask layer 11 and a patterned photoresist layer 12 are sequentially formed on the layer to be etched 10 .

[0037] In this embodiment, a hard mask layer 11 and a photoresist layer (not shown) are sequentially formed on the layer to be etched 10 , and then the photoresist layer is exposed and developed to form a patterned photoresist layer 12 .

[0038] In one embodiment of the present invention, an anti-reflection layer (not shown) is further provided between the hard mask layer 11 and the patterned photoresist layer 12 to reduce the reflection of light occurring during the photolithography process. Specifically, during the photolithography of the photoresist layer, there may be a light reflection problem on the surface of the hard mask layer 11. When light is irradiated to the surface of the hard mask layer 11, part of the light is reflected, and the other part penetrates the hard mask layer 11 and enters the surface of the layer to be etched 10 below. The light reflected from the hard mask layer 11 and the layer to be etched 10 will be reflected to the photoresist layer, which may cause overexposure of the photoresist layer and produce problems such as blur and distortion of the pattern formed by the final etching. In order to avoid this situation, an anti-reflection layer is formed between the hard mask layer 11 and the photoresist layer. The anti-reflection layer can absorb or interfere with the reflected light to reduce the light reflection occurring during the photolithography process. The anti-reflection layer can be an organic anti-reflection layer or an inorganic anti-reflection layer.

[0039] In this embodiment, the layer to be etched 10 may be any layer to be etched, for example, the layer to be etched 10 may be a substrate, for example, a substrate such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, or a silicon-on-insulator substrate or a germanium-on-insulator substrate. The layer to be etched 10 may also be an epitaxial layer formed on a substrate, which is not limited in the present invention.

[0040] The material of the hard mask layer 11 includes silicon dioxide, but is not limited thereto. The hard mask layer 11 may be formed by any suitable process known to those skilled in the art, such as an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, etc. Exemplarily, in this embodiment, the thickness of the hard mask layer 11 is, for example, 3.5 μm, and the thickness of the patterned photoresist layer 12 is, for example, 2.4 μm.

[0041] In step S2, please refer to Figure 5 As shown, the patterned photoresist layer 12 is used as a mask, and the hard mask layer 11 is etched by a dry etching process to form a groove 13 exposing the layer to be etched 10; wherein, in the dry etching, please refer to Figure 4 As shown, a silicon coating 14 is arranged in a reaction chamber, a DC voltage is applied to the silicon coating 14, and the silicon coating 14 is a reverse voltage. The silicon coating 14 is bombarded by plasma to release silicon that adheres to the upper surface of the patterned photoresist layer 12 to form a protective layer 15 to protect the patterned photoresist layer 12. At the same time, the silicon coating 14 releases electrons to modify and harden the patterned photoresist layer 12.

[0042] In this embodiment, a dry etching process is used to etch the hard mask layer 11 through the upper surface of the hard mask layer 11 exposed by the patterned photoresist layer 12 to form a groove 13 in the hard mask layer 11, and the groove 13 exposes the layer 10 to be etched.

[0043] During dry etching, a silicon coating 14 is disposed in the reaction chamber, a DC voltage is applied to the silicon coating 14, and the silicon coating 14 is in reverse voltage, that is, the silicon coating 14 is connected to the negative electrode of the DC power supply, and the positive electrode of the DC power supply is grounded. The silicon coating 14 is in reverse voltage, and the plasma (such as Figure 4 The plasma + in the silicon coating 14 is attracted to move toward the silicon coating 14 and bombard the silicon coating 14. After being bombarded, the silicon coating 14 releases silicon (such as Figure 4 The silicon is attached to the upper surface of the patterned photoresist layer 12 to form a protective layer 15. The silicon material is denser than the photoresist, and can well protect the patterned photoresist layer 12 to prevent the patterned photoresist layer 12 from being damaged during the dry etching process. At the same time, the silicon coating 14 releases electrons (such as Figure 4 The ion e -) makes the patterned photoresist layer 12 modified and hardened to resist the consumption of the top angle of the patterned photoresist layer 12 (i.e., the angle formed by the top surface and the side wall of the patterned photoresist layer 12) by high energy bombardment, so that the patterned photoresist layer 12 can well protect the hard mask layer 11 thereunder, thereby avoiding the generation of stripes on the side walls of the hard mask layer 11 (i.e., the side walls of the groove 13).

[0044] In one embodiment of the present invention, the voltage applied to the silicon coating 14 is between 100V and 400V, but is certainly not limited thereto.

[0045] In one embodiment of the present invention, in the dry etching, the low-frequency power of the lower electrode is less than or equal to 3000 W. Compared with the prior art, the present invention reduces the low-frequency power of the lower electrode, thereby reducing the free energy of the plasma and the intensity of bombarding the hard mask layer 11, which can reduce the rate of polymer generation and the breadth of the distribution range and reduce the loss of the top angle of the patterned photoresist layer 12, thereby further avoiding the generation of sidewall stripes of the groove 13. In addition, the reduction of the low-frequency power of the lower electrode in the present invention prolongs the life of the parts in the cavity to a certain extent.

[0046] In one embodiment of the present invention, during the dry etching, the pressure in the reaction chamber is between 10mT and 100mT, the low-frequency power of the upper electrode is between 250W and 800W, and the low-frequency power of the lower electrode is between 1000W and 3000W, but this is not limited to the above.

[0047] In one embodiment of the present invention, in the dry etching, the reaction gas includes an etching gas and a dilution gas, and the etching gas includes at least one of CF4, CH2F2, CHF3 or C4F8, but is not limited thereto. The etching gas is ionized into a plasma, and chemically reacts with the hard mask layer 11 to produce volatile products, thereby removing the etched hard mask layer 11. The dilution gas includes N2 or Ar, which is used to dilute the etching gas to adjust the concentration of the gas in the reaction chamber, thereby controlling the etching rate and uniformity. The flow rate of the reaction gas is between 5sccm and 1500sccm, but is not limited thereto, and can be determined according to actual etching conditions and process conditions.

[0048] The reaction gas also includes O2, which is introduced during the dry etching process, so that the polymer can be better swept away from the etched sidewalls by the introduction of O2, so as to reduce the stripe morphology formed by the plasma bombarding the polymer on the sidewalls, and a smooth sidewall morphology can be obtained in the hard mask layer 11. Exemplarily, O2 is introduced into the reaction chamber through two pipes, the flow rate of O2 in the first pipe is between 5sccm and 30sccm, and the flow rate of O2 in the second pipe is between 5sccm and 200sccm.

[0049] Figure 6 This is a microscopic enlarged view of the structure with smooth sidewalls after dry etching of the hard mask layer in the semiconductor process method of this application. Please refer to Figure 6 As shown, by adopting the semiconductor process method of the present invention, a smooth sidewall morphology B is obtained after dry etching of the hard mask layer 11 .

[0050] In one embodiment of the present invention, when an anti-reflection layer is disposed between the hard mask layer 11 and the patterned photoresist layer 12 , the anti-reflection layer above the hard mask layer 11 to be etched is first etched away before etching the hard mask layer 11 .

[0051] It should be noted that the protective layer 15 formed on the patterned photoresist layer 12 is inevitably etched during the dry etching process. At the same time, silicon is continuously released from the silicon coating 14 and adheres to the upper surface of the patterned photoresist layer 12 to form the protective layer 15. At the end of the dry etching, the protective layer 15 on the patterned photoresist layer 12 may just be removed, forming a Figure 5 In the structure shown, it is of course possible that a portion of the thickness of the protective layer 15 is retained on the patterned photoresist layer 12. The protective layer 15 is removed at the same time as the patterned photoresist layer 12, and the protective layer 15 does not affect the subsequent process.

[0052] In one embodiment of the present invention, after the groove 13 exposing the layer to be etched 10 is formed in the hard mask layer 11, the process further includes etching the layer to be etched 10 using the hard mask layer 11 as a mask to form a groove, and then filling the groove with an oxide layer or other substances. Since the sidewalls of the hard mask layer 11 are smooth and have no stripe morphology, when the layer to be etched 10 is etched using the hard mask layer 11 as a mask, no stripe morphology will appear on the sidewalls, thereby avoiding the problem of incomplete filling in the subsequent filling process and avoiding affecting the electrical parameters of the device.

[0053] In one embodiment of the present invention, when the layer to be etched 10 is etched to form a groove using the hard mask layer 11 as a mask, the semiconductor process method of the present invention can also be used to etch the layer to be etched 10, but different adaptive adjustments need to be made to the process parameters of dry etching and the etching gas to achieve the etching effect on the layer to be etched 10.

[0054] Of course, before the layer to be etched 10 is etched using the hard mask layer 11 as a mask, the patterned photoresist layer 12 may be removed, or after the layer to be etched 10 is etched, the patterned photoresist layer 12 may be removed.

[0055] In summary, in the semiconductor process method provided by the present invention, a silicon coating is arranged in a reaction chamber, a DC voltage is applied to the silicon coating, and the silicon coating is a reverse voltage. The silicon coating is bombarded with ions to release silicon, which adheres to the upper surface of the patterned photoresist layer to form a protective layer. The silicon material is denser than the photoresist, and can well protect the patterned photoresist layer to avoid the patterned photoresist layer being damaged during dry etching. At the same time, the electrons released by the silicon coating modify and harden the patterned photoresist layer to resist the consumption of the top corners of the patterned photoresist layer by high-energy bombardment, so that the patterned photoresist layer can well protect the hard mask layer below it, thereby avoiding the generation of groove sidewall stripes.

[0056] In addition, during dry etching, the low-frequency power of the lower electrode is less than or equal to 3000 W. Compared with the prior art, the low-frequency power of the lower electrode is reduced, thereby reducing the free energy of the plasma and the intensity of bombarding the hard mask layer, which can reduce the rate of polymer production and the breadth of the distribution range and reduce the loss of the top corner of the patterned photoresist layer, thereby further avoiding the generation of groove sidewall stripes.

[0057] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A semiconductor process method, characterized in that: The following steps are involved: sequentially forming a hard mask layer and a patterned photoresist layer on the layer to be etched; Using the patterned photoresist layer as a mask, a dry etching process is used to etch the hard mask layer to form a groove exposing the layer to be etched; wherein, In the dry etching, a silicon coating is arranged in a reaction chamber, a DC voltage is applied to the silicon coating, and the silicon coating is a reverse voltage. The silicon coating is bombarded by plasma and the released silicon adheres to the upper surface of the patterned photoresist layer to form a protective layer to protect the patterned photoresist layer.

2. The semiconductor process method according to claim 1, characterized in that: During the dry etching, the low-frequency power of the lower electrode is less than or equal to 3000W.

3. The semiconductor process method according to claim 2, characterized in that: During the dry etching, the low-frequency power of the lower electrode is between 1000W and 3000W.

4. The semiconductor process method according to claim 1, characterized in that: During the dry etching, the pressure in the reaction chamber is between 10mT and 100mT, and the low-frequency power of the upper electrode is between 250W and 800W.

5. The semiconductor process method according to claim 1, characterized in that: The voltage applied to the silicon coating is between 100V and 400V.

6. The semiconductor process method according to claim 1, characterized in that: In the dry etching, the reaction gas includes an etching gas and a dilution gas, the etching gas includes at least one of CF4, CH2F2, CHF3 or C4F8, and the dilution gas includes N2 or Ar.

7. The semiconductor process method according to claim 6, characterized in that: The flow rate of the reaction gas is between 5 sccm and 1500 sccm.

8. The semiconductor process method according to claim 6, characterized in that: The reaction gas also includes O2.

9. The semiconductor process method according to claim 8, characterized in that: O2 is introduced into the reaction chamber through two pipes, the flow rate of O2 in the first pipe is between 5sccm and 30sccm, and the flow rate of O2 in the second pipe is between 5sccm and 200sccm.

10. The semiconductor process method according to any one of claims 1 to 9, characterized in that: The material of the hard mask layer includes silicon dioxide, and the material of the layer to be etched includes silicon.

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