Memory, preparation method thereof and electronic equipment
By surface-treating the initial electrode layer to form a concave and convex structure and removing the tip, the capacitance size design and tip discharge problems of existing memory devices when achieving high device density and integration are solved, achieving higher integration and capacitance density.
Patent Information
- Application Number
- CN202311203779.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-18
- Publication Date
- 2025-03-18
AI Technical Summary
When existing memory devices achieve high device density and integration, they are difficult to meet the capacitor size design requirements, and there is also the problem of capacitor tip discharge.
By surface treatment of the initial electrode layer, an uneven structure is formed, and the tip of the convex portion is removed, forming a first electrode layer with a larger surface area, thereby achieving higher integration and capacitance density in the 3D laminated structure.
The capacitor capacitance is increased, the area of a single layer capacitor area is reduced, more transistors and capacitor pairs can be accommodated in the 3D stacked structure, and the capacitor tip discharge is avoided.
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Figure CN119654062A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and more specifically, to a memory device and a method for preparing the same, and an electronic device. Background Art
[0002] Memory is the main medium for storing data in computers. With the development and progress of storage technology, storage devices are constantly moving towards miniaturization, high device density and high integration. Summary of the invention
[0003] The present application proposes a memory and a preparation method thereof, and an electronic device. By changing the surface morphology of the capacitor plate, increasing the capacitor plate area, and improving the capacitance of the capacitor, the area of the single-layer capacitor region can be reduced to achieve a single layer in the 3D stacked structure to accommodate more transistors and capacitor pairs; to achieve the same integration level while using fewer stacking layers; and to achieve a higher integration level under the same technical conditions.
[0004] In a first aspect, an embodiment of the present application provides a method for preparing a memory, comprising:
[0005] providing a substrate;
[0006] forming an initial electrode layer on one side of the substrate;
[0007] Performing a first treatment on the initial electrode layer to form a concavo-convex structure on the surface of the initial electrode layer;
[0008] The initial electrode layer is subjected to a second treatment to remove the tips of the convex parts of the concavo-convex structure;
[0009] treating the initial electrode layer for a third time to form a first electrode layer;
[0010] forming a dielectric layer on the periphery of the first electrode layer, wherein the dielectric layer at least partially surrounds the first electrode layer in a plane perpendicular to the substrate;
[0011] A second electrode layer is formed on a side of the dielectric layer away from the first electrode layer. In a plane perpendicular to the substrate, the second electrode layer at least partially surrounds the dielectric layer.
[0012] In some optional embodiments of the present application, the initial electrode layer is subjected to a second treatment, including:
[0013] The initial electrode layer after the first treatment is placed in a plasma environment with a reactive gas, and the tip of the convex part of the concave-convex structure is treated by radio frequency to remove the tip; wherein:
[0014] The processing time is greater than or equal to 1s and less than or equal to 100s;
[0015] The reaction gas includes hydrogen with a volume flow rate greater than or equal to 100 standard milliliters per minute and less than or equal to 4000 standard milliliters per minute, and argon with a volume flow rate greater than or equal to 50 standard milliliters per minute and less than or equal to 1000 standard milliliters per minute;
[0016] The radio frequency power is greater than or equal to 100 watts and less than or equal to 3000 watts, and the radio frequency is greater than or equal to 100 kHz and less than or equal to 21.72 MHz.
[0017] In some optional embodiments of the present application, an initial electrode layer is formed on one side of the substrate, comprising:
[0018] forming a sacrificial layer and a silicon layer alternately in sequence on one side of the substrate;
[0019] Forming a support structure penetrating the silicon layer and the sacrificial layer on one side of the substrate, wherein the sidewalls of the support structure are in contact with the silicon layer and the sacrificial layer respectively;
[0020] Etching the silicon layer so that each silicon layer forms a plurality of strip structures, the strip structures extending along a first direction parallel to the substrate, the plurality of strip structures in the same silicon layer are sequentially arranged at intervals along a second direction parallel to the substrate, and the first direction and the second direction are arranged at an angle;
[0021] The sacrificial layer is removed and the strip-shaped structure forms an initial electrode layer.
[0022] In some optional embodiments of the present application, the initial electrode layer is subjected to a first treatment, comprising:
[0023] Using an alkaline solution to treat an initial electrode layer of a material including single crystal silicon to form a concave-convex structure on the surface of the initial electrode layer, the treatment time being greater than or equal to 1 second and less than or equal to 100 seconds; or,
[0024] An initial electrode layer made of polysilicon is treated with an acidic solution to form a concave-convex structure on the surface of the initial electrode layer. The treatment time is greater than or equal to 1 second and less than or equal to 100 seconds.
[0025] In some optional embodiments of the present application, the initial electrode layer is subjected to a third treatment, including:
[0026] Depositing metal materials on the peripheries of the plurality of initial electrode layers that have been processed for the second time to form a plurality of metal film layers corresponding to the plurality of initial electrode layers, wherein the metal film layers cover the surfaces of the corresponding initial electrode layers;
[0027] The metal film layer and the initial electrode layer are subjected to rapid thermal annealing treatment, and the plurality of metal film layers respectively form metal silicide with the corresponding initial electrode layers to form a plurality of first electrode layers.
[0028] In some optional embodiments of the present application, a dielectric layer is formed on the periphery of the first electrode layer, including:
[0029] A high dielectric constant material is deposited on the surface of each first electrode layer to form a plurality of dielectric layers corresponding to the plurality of first electrode layers.
[0030] In some optional embodiments of the present application, a second electrode layer is formed on a side of the dielectric layer away from the first electrode layer, comprising:
[0031] Conductive materials are deposited on the periphery of each dielectric layer to form a plurality of inner electrode layers corresponding to the plurality of dielectric layers one by one, wherein the inner electrode layers cover the surface of the corresponding dielectric layer away from the first electrode layer;
[0032] An outer electrode layer is deposited on the periphery of the plurality of inner electrode layers, the outer electrode layer covers the substrate and the plurality of inner electrode layers, and the outer electrode layer and the plurality of inner electrode layers form a second electrode layer.
[0033] In a second aspect, an embodiment of the present application provides a memory, including:
[0034] substrate;
[0035] A first electrode layer is arranged on one side of the substrate, the material of the first electrode layer includes a metal compound, the surface of the first electrode layer has a concavo-convex structure, and the top surface of the convex part of the concavo-convex structure away from the substrate is flat or smooth;
[0036] A dielectric layer is disposed at the periphery of the first electrode layer, and in a plane perpendicular to the substrate, the dielectric layer at least partially surrounds the first electrode layer;
[0037] The second electrode layer is arranged on a side of the dielectric layer away from the first electrode layer. In a plane perpendicular to the substrate, the second electrode layer at least partially surrounds the dielectric layer.
[0038] In some optional embodiments of the present application, the material of the first electrode layer includes metal silicide.
[0039] In some optional embodiments of the present application, the concave-convex structure is evenly distributed on the surface of the first electrode layer.
[0040] In some optional embodiments of the present application, a ratio of a surface area of the first electrode layer on a side away from the substrate to an area of an orthographic projection of the first electrode layer on the substrate is greater than or equal to 1.5.
[0041] In some optional embodiments of the present application, the memory includes a plurality of first electrode layers, the first electrode layers extend along a first direction parallel to the substrate, and the plurality of first electrode layers are arranged in an array in a plane perpendicular to the first direction.
[0042] In some optional embodiments of the present application, the memory includes a plurality of dielectric layers corresponding one-to-one to the plurality of first electrode layers;
[0043] The second electrode layer includes a plurality of inner electrode layers corresponding to the plurality of dielectric layers one by one, the inner electrode layers are arranged at the periphery of the corresponding dielectric layers, and in a plane perpendicular to the first direction, the inner electrode layers at least partially surround the dielectric layers;
[0044] The second electrode layer further includes an outer electrode layer, which is arranged at the periphery of the inner electrode layer, and the plurality of inner electrode layers are connected together through the outer electrode layer.
[0045] In some optional embodiments of the present application, the surface where the outer electrode layer contacts the inner electrode layer includes a concave-convex structure.
[0046] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising the above-mentioned memory.
[0047] The beneficial technical effects brought about by the technical solution provided by the embodiment of the present application include:
[0048] In an embodiment of the present application, after the initial electrode layer is formed, the initial electrode layer is subjected to a first treatment to form a concave-convex structure on the surface of the initial electrode layer, thereby increasing the surface area of the initial electrode layer; thereafter, the initial electrode layer subjected to the first treatment is subjected to a second treatment to remove the tips of the convex portions of the concave-convex structure, thereby making the top surface of the convex portions of the concave-convex structure away from the substrate flat or smooth. Such treatment can, on the one hand, further increase the surface area of the initial electrode layer, and on the other hand, avoid subsequent discharge at the capacitor tip.
[0049] In the embodiment of the present application, the initial electrode layer after the second treatment is treated for the third time to form a first electrode layer; a dielectric layer is formed on the periphery of the first electrode layer; a second electrode layer is formed on the side of the dielectric layer away from the first electrode layer; the first electrode layer, the dielectric layer and the second electrode layer are arranged in sequence, in a plane perpendicular to the substrate, the dielectric layer at least partially surrounds the first electrode layer, and the second electrode layer at least partially surrounds the dielectric layer. The first electrode layer and the second electrode layer are two electrodes of the capacitor, respectively, and the dielectric layer is the insulating medium of the capacitor. Since the surface of the first electrode layer has a concave-convex structure, the surface area of the first electrode layer is large, so that the capacitance of the formed capacitor is large, which can meet the capacitor design requirements, and can reduce the area of the capacitor area, so that a single layer in the 3D stacked structure can accommodate more transistors and capacitor pairs, and the same integration level can be achieved with fewer stacked layers, meeting the integration level requirements. In addition, since the tip of the convex portion of the concave-convex structure has been removed, the top surface of the convex portion away from the substrate is flat or smooth, so discharge at the capacitor tip can be avoided.
[0050] The embodiments of the present application change the surface morphology of the capacitor plate through surface treatment, increase the area of the capacitor plate, and improve the capacitance of the capacitor. The area of the single-layer capacitor region can be reduced to accommodate more transistors and capacitor pairs in a single layer in the 3D stacked structure; achieve the same integration level while using fewer stacked layers; and achieve higher integration level under the same technical conditions.
[0051] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0052] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:
[0053] Figure 1 A schematic diagram of a process for preparing a memory provided in an embodiment of the present application;
[0054] Figure 2 A schematic diagram of a top view structure of a memory provided in an embodiment of the present application;
[0055] Figure 3 A method for preparing a memory provided in an embodiment of the present application forms a sacrificial layer and a silicon layer along the Figure 2 A schematic cross-sectional structure diagram along the aa direction;
[0056] Figure 4 A method for preparing a memory provided in an embodiment of the present application forms a support structure along the Figure 2 A schematic cross-sectional structure diagram along the bb direction;
[0057] Figure 5 A method for preparing a memory provided in an embodiment of the present application forms a strip structure along the Figure 2 A schematic cross-sectional structure diagram along the aa direction;
[0058] Figure 6 A method for preparing a memory provided in an embodiment of the present application includes removing a sacrificial layer along the Figure 2 A schematic cross-sectional structure diagram along the aa direction;
[0059] Figure 7 A method for preparing a memory provided in an embodiment of the present application includes removing a sacrificial layer along the Figure 2 A schematic cross-sectional structure diagram along the bb direction;
[0060] Figure 8 A method for preparing a memory provided in an embodiment of the present application forms a concave-convex structure along the Figure 2 A schematic cross-sectional structure diagram along the aa direction;
[0061] Fig. 9 for Figure 8 A partial enlarged view of the middle A;
[0062] Fig.10 A method for preparing a memory provided in an embodiment of the present application includes removing the tip of the convex portion of the concave-convex structure along the Figure 2 A schematic cross-sectional structure diagram along the aa direction;
[0063] Fig.11 for Fig.10 A partial enlarged view of point B in the middle;
[0064] Fig.12 and Fig.13 A schematic structural diagram of different examples of a method for preparing a memory provided by an embodiment of the present application, in which the tip of the convex part of the concave-convex structure is removed and the convex part is removed;
[0065] Fig.14 A method for preparing a memory provided in an embodiment of the present application forms a metal film layer along the Figure 2 A schematic cross-sectional structure diagram along the aa direction;
[0066] Fig.15 A method for preparing a memory provided in an embodiment of the present application includes performing a rapid thermal annealing process to form a first electrode layer along the Figure 2 A schematic cross-sectional structure diagram along the aa direction;
[0067] Fig.16 A method for preparing a memory provided in an embodiment of the present application includes forming a dielectric layer along the Figure 2 A schematic cross-sectional structure diagram along the aa direction;
[0068] Fig.17 A method for preparing a memory provided in an embodiment of the present application forms an inner electrode layer along the Figure 2 A schematic cross-sectional structure diagram along the aa direction;
[0069] Fig.18 A method for preparing a memory provided in an embodiment of the present application forms an outer electrode layer along the Figure 2 Schematic diagram of the cross-sectional structure along the aa direction.
[0070] Reference numerals:
[0071] 100-memory; 10-substrate; 20-first electrode layer; 21-initial electrode layer; 22-concave-convex structure; 23-convex part; 231-tip; 24-metal film layer; 25-sacrificial layer; 26-silicon layer; 261-strip structure; 27-support structure; 30-dielectric layer; 40-second electrode layer; 41-inner electrode layer; 42-outer electrode layer. DETAILED DESCRIPTION
[0072] The embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.
[0073] Those skilled in the art will appreciate that, unless expressly stated otherwise, the singular forms "a", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the technical field. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" may be implemented as "A", or as "B", or as "A and B".
[0074] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.
[0075] The following is an explanation of the relevant technologies:
[0076] As the demand for device density and integration of various memory devices continues to increase, three-dimensional (3D) memory devices have emerged. Three-dimensional memory devices can store and transfer data in three-dimensional space, which can greatly improve the storage capacity of memory devices, reduce storage costs, improve the integration and storage density of memory devices, and help to achieve miniaturization of memory devices.
[0077] With the rise of integrated circuit 3D DRAM (Dynamic Random Access Memory) and other 3D devices, capacitors and transistors are often stacked to improve integration. Currently, the size of the capacitor is generally designed according to design rules, and the number of layers of capacitor placement is designed to meet the requirements of integration.
[0078] Capacitors are generally stacked in horizontal strips. Some use epitaxy to form single crystal silicon, and then form the lower electrode of the capacitor by forming metal silicide. Some use horizontal strip metal (such as tungsten) to directly form the lower electrode, and then form the upper electrode according to the design rules. However, since the area of the lower electrode and the upper electrode of the capacitor per unit area is small, the capacitance is small. In order to meet the design requirements of the capacitor size, the area of the capacitor area needs to be increased. However, this will make it difficult to meet the integration requirements.
[0079] The memory and its preparation method, and the electronic device provided in this application are intended to solve the above technical problems in the prior art.
[0080] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above technical problems with specific embodiments. It should be noted that the following implementations can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different implementations will not be described repeatedly.
[0081] The present application embodiment provides a method for preparing a memory, and the flowchart of the method for preparing the memory is as follows: Figure 1 As shown, the method includes:
[0082] S101, providing a substrate;
[0083] S102, forming an initial electrode layer on one side of the substrate;
[0084] S103, performing a first treatment on the initial electrode layer to form a concave-convex structure on the surface of the initial electrode layer;
[0085] S104, performing a second treatment on the initial electrode layer to remove the tips of the convex parts of the concavo-convex structure;
[0086] S105, performing a third treatment on the initial electrode layer to form a first electrode layer;
[0087] S106, forming a dielectric layer on the periphery of the first electrode layer, wherein the dielectric layer at least partially surrounds the first electrode layer in a plane perpendicular to the substrate;
[0088] S107 . Form a second electrode layer on a side of the dielectric layer away from the first electrode layer. In a plane perpendicular to the substrate, the second electrode layer at least partially surrounds the dielectric layer.
[0089] In the embodiment of the present application, the memory 100 can be manufactured by the memory manufacturing method.
[0090] Figures 3 to 18 A schematic diagram of the structure of a memory manufacturing method in different processes provided in an embodiment of the present application.
[0091] In the present application embodiment, Fig.18 As shown, the first electrode layer 20 , the dielectric layer 30 and the second electrode layer 40 are all formed on one side of the substrate 10 , and the substrate 10 supports the first electrode layer 20 , the dielectric layer 30 and the second electrode layer 40 .
[0092] In the present application embodiment, Figures 8 to 13As shown, after the initial electrode layer 21 is formed, the initial electrode layer 21 is processed for the first time to form a concave-convex structure 22 on the surface of the initial electrode layer 21, thereby increasing the surface area of the initial electrode layer 21; then, the initial electrode layer 21 that has been processed for the first time is processed for the second time to remove the tip 231 of the convex portion 23 of the concave-convex structure 22, thereby making the top surface of the convex portion 23 of the concave-convex structure 22 away from the substrate 10 flat or smooth. Such processing can, on the one hand, further increase the surface area of the initial electrode layer 21, and on the other hand, avoid subsequent capacitor tip discharge.
[0093] In the present application embodiment, Figures 14 to 18 As shown, the initial electrode layer 21 that has been processed for the second time is processed for the third time to form the first electrode layer 20; a dielectric layer 30 is formed on the periphery of the first electrode layer 20; a second electrode layer 40 is formed on the side of the dielectric layer 30 away from the first electrode layer 20; the first electrode layer 20, the dielectric layer 30 and the second electrode layer 40 are arranged in sequence, and in a plane perpendicular to the substrate 10, the dielectric layer 30 at least partially surrounds the first electrode layer 20, and the second electrode layer 40 at least partially surrounds the dielectric layer 30. The first electrode layer 20 and the second electrode layer 40 are two electrodes of the capacitor respectively, and the dielectric layer 30 is the insulating medium of the capacitor. Since the surface of the first electrode layer 20 has a concave-convex structure 22, the surface area of the first electrode layer 20 is large, so that the capacitance of the formed capacitor is large, which can meet the capacitor design requirements, and can reduce the area of the capacitor region, so that a single layer in the 3D stacked structure can accommodate more transistors and capacitor pairs, and fewer stacked layers are used under the same integration, so as to meet the integration requirements. In addition, since the tip 231 of the convex portion 23 of the concave-convex structure 22 has been removed (such as Fig.10 and Fig.11 As shown in FIG. 1 , the top surface of the protrusion 23 away from the substrate 10 is flat or smooth, so discharge at the capacitor tip can be avoided.
[0094] The embodiments of the present application change the surface morphology of the capacitor plate through surface treatment, increase the area of the capacitor plate, and improve the capacitance of the capacitor. The area of the single-layer capacitor region can be reduced to accommodate more transistors and capacitor pairs in a single layer in the 3D stacked structure; achieve the same integration level while using fewer stacked layers; and achieve higher integration level under the same technical conditions.
[0095] It should be noted that, in the embodiment of the present application, the top surface of the protrusion 23 away from the substrate 10 is flat or smooth, which means that: there is no sharp structure on the top surface of the protrusion 23 away from the substrate 10; or the top surface of the protrusion 23 away from the substrate 10 is parallel to the substrate 10; or the top surface of the protrusion 23 away from the substrate 10 has an angle with the substrate 10, and the angle is 0-30°; or the top surface of the protrusion 23 away from the substrate 10 is a curved surface, etc.
[0096] In some optional embodiments of the present application, such as Figures 3 to 7 As shown, an initial electrode layer 21 is formed on one side of the substrate 10, including:
[0097] like Figure 3 As shown, a sacrificial layer 25 and a silicon layer 26 are alternately formed on one side of the substrate 10. Optionally, the material of the sacrificial layer 25 can be SiGe x .
[0098] Then, if Figure 4 As shown, a support structure 27 penetrating the silicon layer 26 and the sacrificial layer 25 is formed on one side of the substrate 10 , and sidewalls of the support structure 27 are in contact with the silicon layer 26 and the sacrificial layer 25 , respectively.
[0099] In some optional embodiments of the present application, a support structure 27 penetrating the silicon layer 26 and the sacrificial layer 25 is formed on one side of the substrate 10, including: forming a transistor or a partial structure of a transistor on one side of the substrate 10 as a support structure 27, the transistor or the partial structure of the transistor penetrating the silicon layer 26 and the sacrificial layer 25, and the side walls of the transistor or the partial structure of the transistor are in contact with the silicon layer 26 and the sacrificial layer 25, respectively.
[0100] Then, if Figure 5 As shown, the silicon layer 26 is etched so that each silicon layer 26 forms a plurality of strip structures 261, the strip structures 261 extend along a first direction parallel to the substrate 10, and the plurality of strip structures 261 of the same silicon layer 26 are sequentially arranged at intervals along a second direction parallel to the substrate 10, and the first direction and the second direction are arranged at an angle. Optionally, in the embodiment of the present application, the first direction and the second direction are perpendicular.
[0101] Then, if Figure 6 and Figure 7 As shown, the sacrificial layer 25 is removed, and the strip-shaped structure 261 forms the initial electrode layer 21. The material of the initial electrode layer 21 is silicon.
[0102] In the embodiment of the present application, after the sacrificial layers 25 and the silicon layers 26 are alternately formed on one side of the substrate 10, a support structure 27 is then formed on one side of the substrate 10, the support structure 27 penetrates the multi-layer sacrificial layers 25 and the multi-layer silicon layers 26, and the sidewalls of the support structure 27 are respectively in contact with the multi-layer sacrificial layers 25 and the multi-layer silicon layers 26, and the support structure 27 can support the multi-layer silicon layers 26; then, the multi-layer silicon layers 26 are etched so that each layer of the silicon layers 26 can form a plurality of strip structures 261, each strip structure 261 extends along a first direction parallel to the substrate 10, and the plurality of strip structures 261 of the same silicon layer 26 (i.e., formed by etching the same layer of the silicon layer 26) extend along a first direction parallel to the substrate 10. The second direction of the bottom 10 is arranged in sequence at intervals, and the multi-layer strip structures 261 formed by etching the multi-layer silicon layer 26 (each layer has a plurality of strip structures 261) are arranged in an array in a plane perpendicular to the first direction; then the sacrificial layer 25 is removed, and the supporting structure 27 supports the multi-layer strip structures 261, and one strip structure 261 forms an initial electrode layer 21, and each initial electrode layer 21 extends along the first direction parallel to the substrate 10, and the multi-layer strip structures 261 formed by etching the multi-layer silicon layer 26 form a multi-layer initial electrode layer 21 (each layer has a plurality of initial electrode layers 21), and the multi-layer initial electrode layer 21 is arranged in an array in a plane perpendicular to the first direction.
[0103] In some optional embodiments of the present application, such as Figure 8 and Fig. 9 As shown, the initial electrode layer 21 is subjected to a first treatment, including:
[0104] An initial electrode layer 21 made of single crystal silicon is treated with an alkaline solution to form a concavo-convex structure 22 on the surface of the initial electrode layer 21 . The treatment time is greater than or equal to 1 s and less than or equal to 100 s.
[0105] In an embodiment of the present application, an initial electrode layer 21 in strip form and made of single crystal silicon is surface treated and cleaned using an alkaline solution. The anisotropy of single crystal silicon during corrosion in an alkaline solution is utilized to form a concave-convex structure 22 on the surface of the initial electrode layer 21, so that the initial electrode layer 21 has a rough surface, thereby increasing the surface area of the initial electrode layer 21.
[0106] If the first processing time is less than 1s, the processing time is short, the concave-convex structure 22 formed on the surface of the initial electrode layer 21 is not obvious, and the increase in the surface area of the initial electrode layer 21 is limited; if the first processing time is greater than 100s, the processing time is long, which can easily lead to excessive thinning of the thickness of the initial electrode layer 21, and it can also easily lead to excessive depth of the concave-convex structure 22 formed on the surface of the initial electrode layer 21, which increases the difficulty of subsequent deposition to form the dielectric layer 30.
[0107] In the embodiment of the present application, the time of the first treatment is greater than or equal to 1s and less than or equal to 100s, and a suitable concave-convex structure 22 can be formed on the surface of the initial electrode layer 21, which is neither too obvious nor too deep, and can effectively increase the surface area of the initial electrode layer 21 without causing too much impact on the thickness of the initial electrode layer 21.
[0108] In some optional embodiments of the present application, the alkaline solution includes but is not limited to 0-50% by mass of NaOH (sodium hydroxide), 0-50% by mass of KOH (potassium hydroxide), TMAH (tetramethylammonium hydroxide), etc.
[0109] In some other optional embodiments of the present application, Figure 8 and Fig. 9 As shown, the initial electrode layer 21 is subjected to a first treatment, including:
[0110] The initial electrode layer 21 made of polycrystalline silicon is treated with an acidic solution to form a concavo-convex structure 22 on the surface of the initial electrode layer 21 . The treatment time is greater than or equal to 1 s and less than or equal to 100 s.
[0111] In the embodiment of the present application, an acidic solution is used to perform surface treatment and cleaning on a strip-shaped initial electrode layer 21 made of polycrystalline silicon to form a concave-convex structure 22 on the surface of the initial electrode layer 21 , so that the initial electrode layer 21 has a rough surface, thereby increasing the surface area of the initial electrode layer 21 .
[0112] If the first processing time is less than 1s, the processing time is short, the concave-convex structure 22 formed on the surface of the initial electrode layer 21 is not obvious, and the increase in the surface area of the initial electrode layer 21 is limited; if the first processing time is greater than 100s, the processing time is long, which can easily lead to excessive thinning of the thickness of the initial electrode layer 21, and it can also easily lead to excessive depth of the concave-convex structure 22 formed on the surface of the initial electrode layer 21, which increases the difficulty of subsequent deposition to form the dielectric layer 30.
[0113] In the embodiment of the present application, the time of the first treatment is greater than or equal to 1s and less than or equal to 100s, and a suitable concave-convex structure 22 can be formed on the surface of the initial electrode layer 21, which is neither too obvious nor too deep, and can effectively increase the surface area of the initial electrode layer 21 without causing too much impact on the thickness of the initial electrode layer 21.
[0114] In some optional embodiments of the present application, the acidic solution includes but is not limited to HF (hydrogen fluoride) and HNO3 (nitric acid), or HF and H2SO4 (sulfuric acid), etc.
[0115] In the embodiment of the present application, by performing surface wet etching treatment on the initial electrode layer 21 (different chemical treatment and cleaning methods are used for single crystal silicon and polycrystalline silicon, alkaline solutions are used for chemical treatment and cleaning of single crystal silicon, and acidic solutions are used for chemical treatment and cleaning of polycrystalline silicon), a concave-convex structure 22 can be formed on the surface of the initial electrode layer 21, so that the initial electrode layer 21 has a rough surface, thereby increasing the surface area of the initial electrode layer 21.
[0116] In some optional embodiments of the present application, such as Figures 8 to 13 As shown, the initial electrode layer 21 is subjected to a second treatment, including:
[0117] The initial electrode layer 21 that has undergone the first treatment is placed in a plasma environment with a reactive gas, and the tips 231 of the convex portions 23 of the concave-convex structure 22 are treated by radio frequency to remove the tips 231 .
[0118] Wherein: the processing time is greater than or equal to 1s and less than or equal to 100s; the reaction gas includes hydrogen with a volume flow rate greater than or equal to 100 standard milliliters per minute and less than or equal to 4000 standard milliliters per minute, and argon with a volume flow rate greater than or equal to 50 standard milliliters per minute and less than or equal to 1000 standard milliliters per minute; the radio frequency power is greater than or equal to 100 watts and less than or equal to 3000 watts, and the radio frequency frequency is greater than or equal to 100 kilohertz and less than or equal to 21.72 MHz.
[0119] In the embodiment of the present application, a concave-convex structure 22 is formed on the surface of the initial electrode layer 21 through a first treatment, the initial electrode layer 21 that has undergone the first treatment is placed in a plasma environment having a reactive gas, and the tip 231 of the convex portion 23 of the concave-convex structure 22 is removed by radio frequency, so that the top surface of the convex portion 23 of the concave-convex structure 22 that is away from the substrate 10 is flat or smooth. Such treatment can, on the one hand, further increase the surface area of the initial electrode layer 21, and on the other hand, avoid subsequent capacitor tip discharge.
[0120] In an optional embodiment of the present application, through the first treatment, the convex portion 23 of the concave-convex structure 22 formed on the surface of the initial electrode layer 21 is similar to a quadrangular pyramid structure (such as Fig. 9 As shown), the tip is flattened by introducing a reactive gas into a plasma environment and introducing radio frequency (the structural schematic diagram of the convex portion after the tip is flattened is as shown in Fig.11 As shown), the end of the convex portion 23 after processing is approximately flat, and the convex portion 23 is approximately a quadrangular pyramid structure (as shown Fig.11At this time, the surface area of the initial electrode layer 21 is calculated within a unit area of a plane parallel to the substrate 10, and the surface area of the initial electrode layer 21 after the second treatment is 1.732. Therefore, removing the tip 231 of the convex portion 23 can increase the surface area of the initial electrode layer 21 by at least 50%.
[0121] In the embodiment of the present application, a specific reaction gas is introduced and radio frequency is introduced to treat the tip 231 of the convex portion 23 of the concave-convex structure 22 of the initial electrode layer 21 in a plasma environment, which can not only further increase the surface area of the initial electrode layer 21, but also avoid subsequent capacitor tip discharge.
[0122] In some other optional embodiments of the present application, Fig.12 As shown, the top surface of the protrusion 23 away from the substrate 10 may also be a curved surface, such as Fig.13 As shown, the convex portion 23 may also be a triangular prism structure. Of course, the convex portion 23 may also be a triangular pyramid, a pentagonal pyramid, a hexagonal pyramid, a quadrangular prism, a pentagonal prism, a hexagonal prism, etc.
[0123] In some optional embodiments of the present application, such as Fig.14 As shown, the initial electrode layer 21 is subjected to a third treatment, including:
[0124] Metal materials are deposited on the peripheries of the plurality of initial electrode layers 21 that have undergone the second processing to form a plurality of metal film layers 24 corresponding to the plurality of initial electrode layers 21 . The metal film layers 24 cover the surfaces of the corresponding initial electrode layers 21 .
[0125] In the embodiment of the present application, each initial electrode layer 21 extends along a first direction parallel to the substrate 10, and multiple layers (each layer has multiple initial electrode layers 21) of initial electrode layers 21 are arranged in an array in a plane perpendicular to the first direction. Multiple metal film layers 24 correspond to the multiple initial electrode layers 21 one by one, and the metal film layers 24 cover the surfaces of the corresponding initial electrode layers 21, so the multiple metal film layers 24 are arranged in an array in a plane perpendicular to the first direction.
[0126] Optionally, the metal film layer 24 may be formed by depositing metal material using an ALD (Atomic Layer Deposition) method.
[0127] Optionally, the material of the metal film layer 24 includes but is not limited to cobalt, titanium, nickel, etc.
[0128] In some optional embodiments of the present application, such as Fig.15 As shown, the initial electrode layer 21 is subjected to a third treatment, further comprising:
[0129] The metal film layers 24 and the initial electrode layers 21 are subjected to a rapid thermal annealing process, and the plurality of metal film layers 24 respectively form metal silicides with the corresponding initial electrode layers 21 to form a plurality of first electrode layers 20 .
[0130] In the embodiment of the present application, a rapid thermal annealing process is performed so that each metal film layer 24 forms a metal silicide with the corresponding initial electrode layer 21 , and multiple metal film layers 24 and the corresponding initial electrode layers 21 form multiple metal silicides, and the multiple metal silicides serve as multiple first electrode layers 20 .
[0131] In the embodiment of the present application, each initial electrode layer 21 extends along a first direction parallel to the substrate 10, and multiple layers (each layer has multiple initial electrode layers 21) of initial electrode layers 21 are arranged in an array in a plane perpendicular to the first direction. Multiple metal film layers 24 correspond one-to-one to the multiple initial electrode layers 21, and the metal film layers 24 cover the surfaces of the corresponding initial electrode layers 21. Therefore, the multiple first electrode layers 20 formed by rapid thermal annealing treatment all extend along the first direction and are arranged in an array in a plane perpendicular to the first direction.
[0132] In the embodiment of the present application, the surface of the initial electrode layer 21 has a concave-convex structure 22, and the top surface of the convex portion 23 of the concave-convex structure 22 away from the substrate 10 is flat or smooth, so that the surface of the initial electrode layer 21 is rough. In the subsequent metal silicide formation process, this rough morphology is retained to form a first electrode layer 20 with a rough surface (the surface of the first electrode layer 20 has a concave-convex structure 22, and the top surface of the convex portion 23 of the concave-convex structure 22 away from the substrate 10 is flat or smooth), thereby achieving the purpose of increasing the area of the capacitor plate, reducing the area of the capacitor region, achieving higher integration, and avoiding capacitor tip discharge.
[0133] In some optional embodiments of the present application, such as Fig.16 As shown, a dielectric layer 30 is formed on the periphery of the first electrode layer 20, including:
[0134] A high dielectric constant material is deposited on the surface of each first electrode layer 20 to form a plurality of dielectric layers 30 corresponding to the plurality of first electrode layers 20. The use of a high dielectric constant material to form the dielectric layer 30 can increase the capacitance of the capacitor.
[0135] In the embodiment of the present application, each first electrode layer 20 extends along the first direction, and the multiple first electrode layers 20 are arranged in an array in a plane perpendicular to the first direction. The multiple dielectric layers 30 correspond to the multiple first electrode layers 20 one by one, and the dielectric layers 30 cover the surfaces of the corresponding first electrode layers 20. Therefore, each dielectric layer 30 extends along the first direction, and the multiple dielectric layers 30 are arranged in an array in a plane perpendicular to the first direction.
[0136] Optionally, the dielectric layer 30 may be formed by depositing a high dielectric constant material using an ALD method.
[0137] Optionally, in the embodiment of the present application, the high dielectric constant material generally refers to a material with a dielectric constant greater than 3.9, such as hafnium oxide (HfO2), zirconium oxide, aluminum oxide, etc.
[0138] In some optional embodiments of the present application, such as Fig.17 and Fig.18 As shown, a second electrode layer 40 is formed on a side of the dielectric layer 30 away from the first electrode layer 20, including:
[0139] like Fig.17 As shown, conductive material is deposited on the periphery of each dielectric layer 30 to form multiple internal electrode layers 41 corresponding to the multiple dielectric layers 30, and the internal electrode layer 41 covers the surface of the corresponding dielectric layer 30 away from the first electrode layer 20. Optionally, the conductive material can be deposited by ALD method to form the internal electrode layer 41. The conductive material includes but is not limited to titanium or titanium nitride.
[0140] Then, if Fig.18 As shown, an outer electrode layer 42 is deposited on the periphery of the plurality of inner electrode layers 41, and the outer electrode layer 42 covers the substrate 10 and the plurality of inner electrode layers 41, and the outer electrode layer 42 and the plurality of inner electrode layers 41 form a second electrode layer 40. Optionally, the outer electrode layer 42 can be formed by LPCVD (Low Pressure Chemical Vapor Deposition). The material of the outer electrode layer 42 includes but is not limited to SiGe x .
[0141] In the embodiment of the present application, the dielectric layer 30 covers the surface of the first electrode layer 20, the inner electrode layer 41 covers the surface of the corresponding dielectric layer 30, the dielectric layer 30 is the insulating medium of the capacitor, and the outer electrode layer 42 covers the inner electrode layer 41. By arranging the inner electrode layer 41 between the dielectric layer 30 and the outer electrode layer 42, the contact resistance can be reduced and the device performance can be improved.
[0142] In the embodiment of the present application, each dielectric layer 30 extends along the first direction, and the multiple dielectric layers 30 are arranged in an array in a plane perpendicular to the first direction. The multiple internal electrode layers 41 correspond to the multiple dielectric layers 30 one by one, and the internal electrode layers 41 cover the surface of the corresponding dielectric layer 30. Therefore, each internal electrode layer 41 extends along the first direction, and the multiple internal electrode layers 41 are arranged in an array in a plane perpendicular to the first direction; the external electrode layer 42 is formed on the periphery of the multiple internal electrode layers 41 and covers the multiple internal electrode layers 41. The external electrode layer 42 and the multiple internal electrode layers 41 form a second electrode layer 40, and the multiple first electrode layers 20 share one external electrode layer 42.
[0143] Of course, in some other optional embodiments of the present application, according to actual needs, after forming a plurality of internal electrode layers 41, forming the second electrode layer 40 further includes:
[0144] The outer electrode layer 42 is deposited on the periphery of each inner electrode layer 41 to form a plurality of outer electrode layers 42 corresponding to the inner electrode layers 41 . The outer electrode layer 42 covers the surface of the corresponding inner electrode layer 41 away from the dielectric layer 30 .
[0145] At this time, each inner electrode layer 41 extends along the first direction, and multiple inner electrode layers 41 are arranged in an array in a plane perpendicular to the first direction, and the outer electrode layer 42 covers the surface of the corresponding inner electrode layer 41. Therefore, each outer electrode layer 42 extends along the first direction, and multiple outer electrode layers 42 are arranged in an array in a plane perpendicular to the first direction.
[0146] The method for preparing the memory in the embodiment of the present application increases the plate area and improves the capacitor capacitance by changing the surface morphology of the capacitor plate.
[0147] The method for preparing the memory in the embodiment of the present application belongs to the field of semiconductor device preparation and process integration technology, and can be applied to the technology for preparing horizontally stacked capacitors commonly used in 3D DRAM.
[0148] Based on the same inventive concept, the embodiment of the present application provides a memory, the structural diagram of the memory 100 is as shown in FIG. Figure 2 and Fig.18 As shown, the memory 100 includes: a substrate 10 , a first electrode layer 20 , a dielectric layer 30 and a second electrode layer 40 .
[0149] The first electrode layer 20 is arranged on one side of the substrate 10, and the material of the first electrode layer 20 includes a metal compound. The surface of the first electrode layer 20 has a concave-convex structure 22, and the top surface of the convex portion 23 of the concave-convex structure 22 away from the substrate 10 is flat or smooth; the dielectric layer 30 is arranged on the periphery of the first electrode layer 20, and in a plane perpendicular to the substrate 10, the dielectric layer 30 at least partially surrounds the first electrode layer 20; the second electrode layer 40 is arranged on a side of the dielectric layer 30 away from the first electrode layer 20, and in a plane perpendicular to the substrate 10, the second electrode layer 40 at least partially surrounds the dielectric layer 30.
[0150] In the embodiment of the present application, the first electrode layer 20 , the dielectric layer 30 , and the second electrode layer 40 are all disposed on one side of the substrate 10 , and the substrate 10 supports the first electrode layer 20 , the dielectric layer 30 , and the second electrode layer 40 .
[0151] In the embodiment of the present application, the surface of the first electrode layer 20 has a concave-convex structure 22, and the top surface of the convex portion 23 of the concave-convex structure 22 away from the substrate 10 is flat or smooth, which not only increases the surface area of the first electrode layer 20, but also avoids discharge at the capacitor tip.
[0152] In the embodiment of the present application, the first electrode layer 20, the dielectric layer 30 and the second electrode layer 40 are arranged in sequence, in a plane perpendicular to the substrate 10, the dielectric layer 30 at least partially surrounds the first electrode layer 20, the second electrode layer 40 at least partially surrounds the dielectric layer 30, the first electrode layer 20 and the second electrode layer 40 are respectively two electrodes of the capacitor, and the dielectric layer 30 is the insulating medium of the capacitor. Since the surface of the first electrode layer 20 has a concave-convex structure 22, the surface area of the first electrode layer 20 is large, so that the capacitance of the formed capacitor is large, which can meet the capacitor design requirements, and can reduce the area of the capacitor region, so that a single layer in the 3D stacked structure can accommodate more transistors and capacitor pairs, and the same integration level can be achieved with fewer stacked layers, meeting the integration level requirements. In addition, since the top surface of the convex portion 23 of the concave-convex structure 22 away from the substrate 10 is flat or smooth, it is possible to avoid discharge at the tip of the capacitor.
[0153] The embodiments of the present application can reduce the area of the single-layer capacitor region by changing the surface morphology of the capacitor plate, increasing the area of the capacitor plate, and improving the capacitance of the capacitor, so as to accommodate more transistors and capacitor pairs in a single layer in the 3D stacked structure; achieve the same integration level while using fewer stacked layers; and achieve higher integration level under the same technical conditions.
[0154] Optionally, the material of the substrate 10 includes but is not limited to silicon.
[0155] Optionally, the material of the first electrode layer 20 includes but is not limited to metal silicide.
[0156] In some optional embodiments of the present application, such as Fig.18 As shown, the concavo-convex structures 22 are evenly distributed on the surface of the first electrode layer 20, so that the surface area of each part of the first electrode layer 20 is increased, and the degree of increase is close or the same, thereby uniformly increasing the capacitance of the capacitor. Optionally, Fig.18 The enlarged view of the convex portion 23 of the concavo-convex structure 22 can be as follows: Fig.11 The end of the convex portion 23 shown in the figure is approximately a plane, and can also be as follows Fig.12 The top of the pyramid is shown as an arc-shaped schematic diagram, or it can also be as follows Fig.13 The schematic diagram of the triangular prism structure shown may also be a schematic diagram of a triangular pyramid, a pentagonal pyramid, a hexagonal pyramid, a quadrangular prism, a pentagonal prism, a hexagonal prism, or the like.
[0157] In some optional embodiments of the present application, a ratio of a surface area of the first electrode layer 20 on a side away from the substrate 10 to an area of an orthographic projection of the first electrode layer 20 on the substrate 10 is greater than or equal to 1.5.
[0158] If the ratio of the surface area of the first electrode layer 20 to the area of the orthographic projection of the first electrode layer 20 on the substrate 10 is less than 1.5 and greater than 1, although the surface area of the first electrode layer 20 is still increased per unit area in the plane parallel to the substrate 10, the increase in the surface area of the first electrode layer 20 is limited, and the improvement in the capacitance of the capacitor is limited.
[0159] In the embodiment of the present application, the ratio of the surface area of the first electrode layer 20 to the area of the orthographic projection of the first electrode layer 20 on the substrate 10 is greater than or equal to 1.5, which can effectively increase the surface area of the first electrode layer 20, thereby significantly improving the capacitance of the capacitor.
[0160] In an optional embodiment of the present application, the ratio of the surface area of the first electrode layer 20 to the area of the orthographic projection of the first electrode layer 20 on the substrate 10 is equal to 1.5, that is, the surface area of the capacitor plate increases by 50%, and the capacitance of the capacitor increases by 50%. Then the area required for the capacitor region is equivalent to 2 / 3 of the area required for a traditional capacitor (such as a traditional capacitor with a flat surface plate). Together with transistors and other peripheral circuits, it is estimated that a single layer in the 3D stacked structure can save a total of 1 / 4 of the area, and the number of transistors and capacitor pairs accommodated in a single layer can be increased by 33%; or under the same integration level, the number of stacked layers is reduced by 25% (for example, the original 3D stacked structure required 4 layers, but now only 3 layers are needed).
[0161] In some optional embodiments of the present application, such as Fig.18 As shown, the memory 100 includes a plurality of first electrode layers 20 , which extend along a first direction parallel to the substrate 10 , and are arranged in an array in a plane perpendicular to the first direction.
[0162] In some optional embodiments of the present application, such as Fig.18 As shown, the memory 100 includes a plurality of dielectric layers 30 corresponding one-to-one to the plurality of first electrode layers 20 .
[0163] Optionally, the dielectric layer 30 is made of a high dielectric constant material, which can increase the capacitance of the capacitor.
[0164] In the embodiment of the present application, each dielectric layer 30 extends along the first direction, and the plurality of dielectric layers 30 are arranged in an array in a plane perpendicular to the first direction.
[0165] In some optional embodiments of the present application, such as Fig.18As shown, the second electrode layer 40 includes a plurality of inner electrode layers 41 corresponding one to one with the plurality of dielectric layers 30, and the inner electrode layers 41 are arranged at the periphery of the corresponding dielectric layers 30, and in a plane perpendicular to the first direction, the inner electrode layers 41 at least partially surround the dielectric layers 30; the second electrode layer 40 also includes an outer electrode layer 42, and the outer electrode layer 42 is arranged at the periphery of the inner electrode layer 41, and the plurality of inner electrode layers 41 are connected together through the outer electrode layer 42.
[0166] In the embodiment of the present application, in a plane perpendicular to the substrate 10, the dielectric layer 30 at least partially surrounds the first electrode layer 20, and in a plane perpendicular to the first direction, the inner electrode layer 41 at least partially surrounds the dielectric layer 30, the dielectric layer 30 is an insulating medium of the capacitor, and the outer electrode layer 42 is arranged on the periphery of the inner electrode layer 41. By arranging the inner electrode layer 41 between the dielectric layer 30 and the outer electrode layer 42, the contact resistance can be reduced and the device performance can be improved.
[0167] In the embodiment of the present application, each internal electrode layer 41 extends along the first direction, and the multiple internal electrode layers 41 are arranged in an array in a plane perpendicular to the first direction.
[0168] In the embodiment of the present application, the external electrode layer 42 is formed on the periphery of the multiple internal electrode layers 41 and covers the substrate 10 and the multiple internal electrode layers 41. The external electrode layer 42 and the multiple internal electrode layers 41 form the second electrode layer 40, and the multiple first electrode layers 20 share one external electrode layer 42.
[0169] In some optional embodiments of the present application, such as Fig.18 As shown, the surface of the outer electrode layer 42 in contact with the inner electrode layer 41 includes a concave-convex structure. The surface of the outer electrode layer 42 in contact with the inner electrode layer 41 is adapted to the outer surface of the inner electrode layer 41, and the outer electrode layer 42 and the inner electrode layer 41 are more closely fitted. The surface area of the surface of the outer electrode layer 42 in contact with the inner electrode layer 41 is larger, so that the capacitance of the formed capacitor is larger, which can meet the capacitor design requirements, reduce the capacitor area, and realize that a single layer in the 3D stacked structure accommodates more transistors and capacitor pairs, and realizes the same integration using fewer stacked layers to meet the integration requirements.
[0170] The memory of the embodiment of the present application increases the plate area and improves the capacitor capacitance by changing the surface morphology of the capacitor plate.
[0171] The memory of the embodiment of the present application can be applied to 3D DRAM.
[0172] In some optional embodiments of the present application, the memory 100 can be formed into an array structure and / or a 3D stacked structure, which can improve the storage capacity of the memory, reduce storage costs, improve integration and storage density, and help achieve miniaturization.
[0173] In some optional implementations of the present application, the memory may be a random access memory, specifically a static random access memory or a dynamic random access memory, and of course, may also be a flash memory storage, etc.
[0174] Based on the same inventive concept, an embodiment of the present application provides an electronic device, which includes the above-mentioned memory 100.
[0175] It should be noted that, since the electronic device of the embodiment of the present application includes the memory of the embodiment of the present application, the electronic device of the embodiment of the present application also has the above-mentioned beneficial effects of the memory of the embodiment of the present application, which will not be repeated here.
[0176] In some optional embodiments of the present application, the electronic device includes a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a mobile power supply, etc. Among them, the storage device may include a memory in a computer, etc., which is not limited here.
[0177] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:
[0178] In an embodiment of the present application, after the initial electrode layer is formed, the initial electrode layer is subjected to a first treatment to form a concave-convex structure on the surface of the initial electrode layer, thereby increasing the surface area of the initial electrode layer; thereafter, the initial electrode layer subjected to the first treatment is subjected to a second treatment to remove the tips of the convex portions of the concave-convex structure, thereby making the top surface of the convex portions of the concave-convex structure away from the substrate flat or smooth. Such treatment can, on the one hand, further increase the surface area of the initial electrode layer, and on the other hand, avoid subsequent discharge at the capacitor tip.
[0179] In the embodiment of the present application, the initial electrode layer after the second treatment is treated for the third time to form a first electrode layer; a dielectric layer is formed on the periphery of the first electrode layer; a second electrode layer is formed on the side of the dielectric layer away from the first electrode layer; the first electrode layer, the dielectric layer and the second electrode layer are arranged in sequence, in a plane perpendicular to the substrate, the dielectric layer at least partially surrounds the first electrode layer, the second electrode layer at least partially surrounds the dielectric layer, the first electrode layer and the second electrode layer are two electrodes of the capacitor respectively, and the dielectric layer is the insulating medium of the capacitor. Since the surface of the first electrode layer has a concave-convex structure, the surface area of the first electrode layer is large, so that the capacitance of the formed capacitor is large, which can meet the capacitor design requirements, and can reduce the area of the capacitor region, so that a single layer in the 3D stacked structure can accommodate more transistors and capacitor pairs, and the same integration level can be achieved with fewer stacked layers, meeting the integration level requirements. In addition, since the tip of the convex portion of the concave-convex structure has been removed, the top surface of the convex portion away from the substrate is flat or smooth, so it is possible to avoid discharge at the tip of the capacitor.
[0180] The embodiments of the present application change the surface morphology of the capacitor plate through surface treatment, increase the area of the capacitor plate, and improve the capacitance of the capacitor. The area of the single-layer capacitor region can be reduced to accommodate more transistors and capacitor pairs in a single layer in the 3D stacked structure; achieve the same integration level while using fewer stacked layers; and achieve higher integration level under the same technical conditions.
[0181] Those skilled in the art will appreciate that the various operations, methods, steps, measures, and schemes in the processes discussed in this application may be alternated, altered, combined, or deleted. Further, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted. Further, the steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted.
[0182] In the description of this application, the words "center", "upper", "lower", "front", "back",
[0183]
[0184] The directions or positional relationships indicated are based on the exemplary directions or positional relationships shown in the drawings, and are intended to facilitate or simplify the description of the embodiments of the present application, rather than to indicate or imply that the devices or components referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present application.
[0185] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.
[0186] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0187] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.
[0188] It should be understood that, although the various steps in the flowchart of the accompanying drawings are displayed in sequence according to the indication of the arrows, the order of implementation of these steps is not limited to the order indicated by the arrows. Unless there is a clear description herein, in some implementation scenarios of the embodiments of the present application, the steps in each process can be performed in other orders according to demand. Moreover, some or all of the steps in each flow chart may include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages may be executed at the same time, or may be executed at different times in different scenarios at the execution time, and the execution order of these sub-steps or stages may be flexibly configured according to demand, and the embodiments of the present application do not limit this.
[0189] The above is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the scheme of the present application, other similar implementation methods based on the technical ideas of the present application are also within the protection scope of the embodiments of the present application.
Claims
1. A method for preparing a memory, characterized in that: include: providing a substrate; forming an initial electrode layer on one side of the substrate; Performing a first treatment on the initial electrode layer to form a concave-convex structure on the surface of the initial electrode layer; Performing a second treatment on the initial electrode layer to remove the tips of the convex parts of the concavo-convex structure; Processing the initial electrode layer for a third time to form a first electrode layer; forming a dielectric layer on the periphery of the first electrode layer, wherein in a plane perpendicular to the substrate, the dielectric layer at least partially surrounds the first electrode layer; A second electrode layer is formed on a side of the dielectric layer away from the first electrode layer. In a plane perpendicular to the substrate, the second electrode layer at least partially surrounds the dielectric layer.
2. The method for preparing a memory according to claim 1, characterized in that: The initial electrode layer is subjected to a second treatment, comprising: The initial electrode layer after the first treatment is placed in a plasma environment with a reactive gas, and the tip of the convex part of the concave-convex structure is treated by radio frequency to remove the tip; wherein: The processing time is greater than or equal to 1s and less than or equal to 100s; The reaction gas includes hydrogen with a volume flow rate greater than or equal to 100 standard milliliters per minute and less than or equal to 4000 standard milliliters per minute, and argon with a volume flow rate greater than or equal to 50 standard milliliters per minute and less than or equal to 1000 standard milliliters per minute; The radio frequency power is greater than or equal to 100 watts and less than or equal to 3000 watts, and the radio frequency is greater than or equal to 100 kHz and less than or equal to 21.72 MHz.
3. The method for preparing a memory according to claim 1 or 2, characterized in that: An initial electrode layer is formed on one side of the substrate, comprising: forming a sacrificial layer and a silicon layer alternately in sequence on one side of the substrate; Forming a support structure penetrating the silicon layer and the sacrificial layer on one side of the substrate, wherein sidewalls of the support structure are in contact with the silicon layer and the sacrificial layer respectively; Etching the silicon layer so that each of the silicon layers forms a plurality of strip structures, wherein the strip structures extend along a first direction parallel to the substrate, and the plurality of strip structures of the same silicon layer are sequentially arranged at intervals along a second direction parallel to the substrate, and the first direction and the second direction are arranged at an angle; The sacrificial layer is removed, and the strip-shaped structure forms an initial electrode layer.
4. The method for preparing a memory according to claim 3, characterized in that: The initial electrode layer is subjected to a first treatment, comprising: The initial electrode layer, whose material includes single crystal silicon, is treated with an alkaline solution to form a concavo-convex structure on the surface of the initial electrode layer, wherein the treatment time is greater than or equal to 1 second and less than or equal to 100 seconds; or The initial electrode layer, whose material includes polycrystalline silicon, is treated with an acidic solution to form a concave-convex structure on the surface of the initial electrode layer, and the treatment time is greater than or equal to 1 second and less than or equal to 100 seconds.
5. The method for preparing a memory according to claim 3, characterized in that: The initial electrode layer is subjected to a third treatment, comprising: Depositing metal materials on the peripheries of the plurality of initial electrode layers that have undergone the second treatment to form a plurality of metal film layers corresponding to the plurality of initial electrode layers, wherein the metal film layers cover the surfaces of the corresponding initial electrode layers; The metal film layer and the initial electrode layer are subjected to a rapid thermal annealing process, and a plurality of the metal film layers respectively form metal silicides with the corresponding initial electrode layers to form a plurality of first electrode layers.
6. The method for preparing a memory according to claim 5, characterized in that: A dielectric layer is formed on the periphery of the first electrode layer, comprising: A high dielectric constant material is deposited on the surface of each of the first electrode layers to form a plurality of dielectric layers corresponding to the plurality of the first electrode layers.
7. The method for preparing a memory according to claim 6, characterized in that: A second electrode layer is formed on a side of the dielectric layer away from the first electrode layer, comprising: Conductive materials are deposited on the periphery of each dielectric layer to form a plurality of inner electrode layers corresponding to the plurality of dielectric layers one by one, wherein the inner electrode layers cover the surface of the corresponding dielectric layer away from the first electrode layer; An outer electrode layer is deposited on the periphery of the plurality of inner electrode layers, the outer electrode layer covers the substrate and the plurality of inner electrode layers, and the outer electrode layer and the plurality of inner electrode layers form a second electrode layer.
8. A memory, characterized in that: include: substrate; A first electrode layer is arranged on one side of the substrate, the material of the first electrode layer includes a metal compound, the surface of the first electrode layer has a concave-convex structure, and the top surface of the convex part of the concave-convex structure away from the substrate is flat or smooth; a dielectric layer, disposed at the periphery of the first electrode layer, wherein in a plane perpendicular to the substrate, the dielectric layer at least partially surrounds the first electrode layer; The second electrode layer is arranged on a side of the dielectric layer away from the first electrode layer. In a plane perpendicular to the substrate, the second electrode layer at least partially surrounds the dielectric layer.
9. The memory according to claim 8, characterized in that: The material of the first electrode layer includes metal silicide.
10. The memory according to claim 8, characterized in that: The concave-convex structure is evenly distributed on the surface of the first electrode layer.
11. The memory according to claim 8, characterized in that: A ratio of a surface area of the first electrode layer at a side away from the substrate to an area of an orthographic projection of the first electrode layer on the substrate is greater than or equal to 1.
5.
12. The memory according to claim 8, characterized in that: The memory includes a plurality of first electrode layers, wherein the first electrode layers extend along a first direction parallel to the substrate, and the plurality of first electrode layers are arranged in an array in a plane perpendicular to the first direction.
13. The memory according to claim 12, characterized in that: The memory includes a plurality of dielectric layers corresponding one-to-one to the plurality of the first electrode layers; The second electrode layer includes a plurality of inner electrode layers corresponding to the plurality of dielectric layers one by one, the inner electrode layers are arranged at the periphery of the corresponding dielectric layers, and in a plane perpendicular to the first direction, the inner electrode layers at least partially surround the dielectric layers; The second electrode layer further includes an outer electrode layer, which is disposed at the periphery of the inner electrode layer, and a plurality of the inner electrode layers are connected together through the outer electrode layer.
14. The memory according to claim 13, characterized in that: A surface of the outer electrode layer contacting the inner electrode layer comprises a concavo-convex structure.
15. An electronic device, characterized in that: A memory comprising the memory according to any one of claims 8 to 14.