Chip preparation method

Abstract

The invention discloses a preparation method of a chip, which is suitable for the technical field of semiconductors, and the preparation method comprises the steps: pasting a wafer on a cutting adhesive tape, the cutting adhesive tape comprises a first surface close to one side of the wafer and a barrier layer arranged on the first surface, and the barrier layer extends into the cutting adhesive tape from the first surface, the surface, close to one side of the wafer, of the barrier layer is flush with the first surface, the wafer comprises a cutting channel, and the orthographic projection of the cutting channel on the first surface is located in the area range where the barrier layer is located. And cutting the cutting channels of the wafer so as to cut the wafer into a plurality of chips. According to the technical scheme, the chip preparation precision is improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a method for preparing a chip. Background Art

[0002] In the process of cutting wafers to form chips, it is necessary to stick a cutting tape on the back of the wafer to fix the wafer.

[0003] However, during the wafer cutting process, the cutting tape is easily cut by mistake, causing problems such as bubble defects in the cutting tape, affecting the chip preparation accuracy and affecting the subsequent chip bonding. Summary of the invention

[0004] The present application provides a chip preparation method, aiming to improve the chip preparation accuracy.

[0005] To achieve the above objectives, the embodiments of the present application provide the following technical solutions: The present application provides a method for preparing a chip, the method comprising: pasting a wafer onto a dicing tape, the dicing tape comprising a first surface close to one side of the wafer, and a barrier layer disposed on the first surface, the barrier layer extending from the first surface into the dicing tape, and a surface of the barrier layer close to one side of the wafer being flush with the first surface, the wafer comprising a dicing path, and the orthographic projection of the dicing path on the first surface being located within the region where the barrier layer is located. The dicing path of the wafer is cut to cut the wafer into a plurality of chips.

[0006] The chip preparation method provided in the present application is to stick a wafer to a dicing tape, and then cut the dicing path of the wafer to cut the wafer into multiple chips. A barrier layer is provided on the first surface of the dicing tape, and the surface of the barrier layer close to the wafer is flush with the first surface to ensure the close fit between the wafer and the dicing tape, which is conducive to fixing the wafer. In addition, the orthographic projection of the dicing path on the first surface is located within the area where the barrier layer is located, so as to realize the protection of the dicing tape by the barrier layer during the cutting process, and prevent the dicing tape located below the dicing path from being cut and causing bubble defects, thereby improving the preparation accuracy of the chip, and then improving the reliability of subsequent chip bonding.

[0007] In some embodiments, a plasma etching process is used to cut the cutting paths of the wafer, and the material of the barrier layer includes a conductive material.

[0008] In some embodiments, the material of the barrier layer includes at least one of copper, iron, or chromium.

[0009] In some embodiments, the width of the barrier layer is greater than the width of the scribe line.

[0010] In some embodiments, along the width direction of the scribe line, boundaries of the barrier layer on two opposite sides respectively exceed boundaries of the scribe line on two opposite sides.

[0011] In some embodiments, the ratio of the distance that the boundary of the barrier layer exceeds the boundary of the scribe line to the width of the scribe line is in a range of 0.05-0.1.

[0012] In some embodiments, the orthographic projection shape of the scribe line of the wafer on the first surface is a mesh shape, and the orthographic projection shape of the blocking layer on the first surface is a mesh shape.

[0013] In some embodiments, the preparation method further comprises: pasting the frame onto the dicing tape, the frame being arranged around the wafer, and a gap region being provided between the frame and the wafer, and the barrier layer of the dicing tape being further provided in the gap region.

[0014] In some embodiments, the orthographic projection of the blocking layer on the first surface is in the shape of a mesh. The mesh-shaped blocking layer includes a first blocking line extending along a first direction and a second blocking line extending along a second direction, the first direction and the second direction intersect and are parallel to the first surface respectively. The first blocking line and the second blocking line both extend to the gap area. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 A flow chart of a method for preparing a chip provided in an embodiment of the present application; Figure 2~Figure 5 for Figure 1 A diagram of each step of the preparation method; Figure 6 for Figure 5 A local enlarged view of the wafer at position M; Figure 7 A schematic diagram of the structure of the cutting tape provided in an embodiment of the present application; Figure 8 A schematic diagram of the structure of a wafer, a frame and a dicing tape provided in an embodiment of the present application. DETAILED DESCRIPTION

[0016] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0017] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0018] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0019] When describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connection" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0020] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0021] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0022] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0023] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0024] In the traditional chip packaging process, it is necessary to stick a dicing tape on the back of the wafer and then cut the wafer into chips along the dicing lines. Common cutting methods include plasma cutting, laser cutting and mechanical cutting.

[0025] Plasma cutting is similar to plasma etching, which uses high-temperature plasma to etch the chips apart, thereby achieving the purpose of cutting wafers. When plasma etches the wafers apart, the silicon near the cutting tape around the cutting path may be over-etched by the plasma, resulting in a bottom notching morphology defect.

[0026] Laser cutting, also known as laser cutting, is a non-contact processing method that uses high-temperature, high-power lasers to achieve laser ablation cutting. The high-power laser used in laser ablation cutting generates high heat during operation, which will affect the structure of the cutting tape used to fix the wafer at the bottom of the wafer, causing the tape to degenerate.

[0027] Mechanical dicing is a method of cutting the chips on a wafer using a blade, which is a contact separation process. However, mechanical dicing can easily cut the dicing tape by mistake, causing bubbles to form on the dicing tape.

[0028] Since the wafer is already thinned at this time, the thickness, roughness and other parameters of silicon have been thinned very accurately to ensure the completion effect of the subsequent chip to wafer hybrid bonding process (Die to Wafer Hybrid Bonding). The deformation of the dicing tape causes the chip to move slightly, the lateral cutting and etching of the silicon bottom will change the etching morphology behind the silicon, and the tape reacts with plasma to produce contaminants and impurities, which will affect the chip preparation accuracy, and thus affect the bonding accuracy of the subsequent chip to wafer hybrid bonding.

[0029] In order to solve the above problems, an embodiment of the present application provides a method for preparing a chip, which is used to prepare a chip with high cleanliness and high accuracy. Figure 1 A flow chart of a method for preparing a chip provided in an embodiment of the present application; Figure 2~Figure 5 for Figure 1 The steps of the preparation method are shown in FIG. Figure 1 As shown, the preparation method includes the following steps S1 to S2: Step S1: Figure 2As shown, the wafer 1 is aligned and pasted on the dicing tape 2, and the dicing tape 2 includes a first surface 21 close to the side of the wafer 1, and a barrier layer 3 arranged on the first surface 21. The barrier layer 3 extends from the first surface 21 into the dicing tape 2, and the surface of the barrier layer 3 close to the side of the wafer 1 is flush with the first surface 21, that is, along the direction Z, the upper surface of the barrier layer 3 is not higher or lower than the first surface 21, so as to ensure the close fit between the wafer 1 and the dicing tape 2, which is conducive to fixing the wafer 1 and protecting the dicing tape 2.

[0030] The wafer includes a dicing path 10, which is used as a region for dicing the wafer 1. In the process of aligning and pasting the wafer 1 onto the dicing tape 2, the dicing path 10 needs to be aligned with the barrier layer 3 on the dicing tape 2. The orthographic projection of the dicing path 10 on the first surface 21 is located within the region where the barrier layer 3 is located. It can be understood that along the direction X, the width of the barrier layer 3 is greater than or equal to the width of the dicing path 2, so that the barrier layer 3 protects the dicing tape 2 during the dicing process. In addition, a mask layer 4 is formed on the side of the wafer 1 away from the dicing tape 2.

[0031] Step S2: Figure 3~Figure 5 As shown, the dicing lanes 10 of the wafer 1 are cut to cut the wafer 1 into a plurality of chips.

[0032] For example, the wafer 1 may be cut by a plasma etching process, such as Figure 3 As shown, on the side of the mask layer 4 away from the wafer 1, a photoresist layer 5 having a first opening 51 is formed by exposure and development. Along the direction Z, the first opening 51 is located directly above the cutting street 10. Figure 4 As shown, the mask layer 4 and the wafer 1 are plasma etched along the first opening 51 until the silicon at the bottom of the wafer is etched, and a second opening 11 is formed in the wafer 1. Figure 5 As shown, the process parameters of the plasma etching are changed, and the silicon at the bottom of the wafer 1 is continuously etched through the mask layer 4 until the wafer 1 is completely cut to form a plurality of chips.

[0033] The chip preparation method provided in the present application is to stick the wafer 1 to the dicing tape 2, and then cut the cutting path 10 of the wafer 1 to cut the wafer 1 into multiple chips. The first surface 21 of the dicing tape 2 is provided with a barrier layer 3, and the surface of the barrier layer 3 close to the side of the wafer 1 is flush with the first surface 21 to ensure the close fit between the wafer 1 and the dicing tape 2, which is conducive to fixing the wafer 1. In addition, the orthographic projection of the dicing path 10 on the first surface 21 is located within the area where the barrier layer 3 is located, so as to prevent the dicing tape 2 located below the dicing path 10 from being cut and causing bubble defects, thereby improving the chip preparation accuracy and further improving the reliability of subsequent chip bonding.

[0034] In the above embodiment, Figure 2~Figure 5 As shown, a plasma etching process is used to cut the cutting path 10 of the wafer 1, and the material of the barrier layer 3 includes a conductive material. Exemplarily, the material of the barrier layer 3 includes at least one of copper (Cu) with relatively stable chemical properties, iron (Fe) or chromium (Cr) with high conductive hardness, and the conductive material does not include aluminum (Al), tungsten (W) and other metals with relatively soft texture and high activity.

[0035] In the above steps, the barrier layer 3 remains grounded. After the silicon at the bottom of the wafer 1 is etched by plasma, the plasma contacts the barrier layer 3 set on the dicing tape 2. The plasma will not contact the dicing tape 2, thereby preventing the dicing tape 2 from being cut, thereby causing bubble defects and chemical property changes. At the same time, since the plasma is guided along the barrier layer 3 of the grounded metal material, the silicon outside the cutting path 10 in the wafer 1 will not be over-etched, that is, no lateral etching will occur, thereby improving the reliability of the internal structure of the wafer 1.

[0036] In some embodiments, a laser cutting process may be used to cut the cutting path 10 of the wafer 1. Optionally, in this case, the material of the barrier layer 3 is a heat-resistant material. Alternatively, a mechanical cutting process may be used to cut the cutting path 10 of the wafer 1. Optionally, in this case, the material of the barrier layer 3 is a material with higher strength. The barrier layer 3 provided in the above embodiments can protect the cutting tape 2 and prevent the cutting tape 2 located below the cutting path 10 from generating bubble defects.

[0037] Figure 6 for Figure 5 A local enlarged view of the wafer at position M.

[0038] In some embodiments, Figure 6 As shown, along the direction X, the width d1 of the barrier layer 3 is greater than the width d of the cutting street 10. For example, the left side boundary of the barrier layer 3 may exceed the left side boundary of the cutting street 10, and the right side boundary of the barrier layer 3 may be flush with the right side boundary of the cutting street 10, or the right side boundary of the barrier layer 3 may exceed the right side boundary of the cutting street 10, and the left side boundary of the barrier layer 3 may be flush with the left side boundary of the cutting street 10, or both side boundaries of the barrier layer 3 may exceed both side boundaries of the cutting street 10.

[0039] The embodiment provided in the present application is described by taking the two side boundaries of the barrier layer 3 as an example where both side boundaries of the cutting path 10 exceed the two side boundaries of the cutting path 10, that is, the projection of the cutting path 10 on the first surface 21 is completely located on the inner side of the barrier layer 3 to ensure the process window during plasma etching.

[0040] In some embodiments, Figure 6As shown, along the direction X, the distance d2 of the boundary of the barrier layer 3 beyond the boundary of the cutting path 10 is in the range of 0.05 to 0.1 with respect to the width d of the cutting path 10. For example, the range of d2:d can be 0.05, 0.0625, 0.075, 0.0875 or 0.1. The ratio of the widths of the above two is set in the range of 0.05 to 0.1, which can ensure that when the wafer 1 is subjected to a plasma etching process, the plasma does not contact the cutting tape 2 at all, thereby further achieving the purpose of protecting the cutting tape 2.

[0041] Figure 7 A schematic diagram of the structure of the cutting tape provided in an embodiment of the present application.

[0042] In some embodiments, Figure 7 As shown, the shape of the orthographic projection of the cutting road 10 of the wafer 1 on the first surface 21 is a mesh, and the shape of the orthographic projection of the blocking layer 3 on the first surface 21 is a mesh. It can be understood that the morphology of the blocking layer 3 is consistent with the morphology of the cutting road 10, and the cutting road 10 is aligned with the blocking layer 3 to achieve comprehensive protection of the cutting tape 2 located under the cutting road 10.

[0043] Figure 8 A schematic diagram of the structure of a wafer, a frame and a dicing tape provided in an embodiment of the present application.

[0044] In some embodiments, Figure 8 As shown, the preparation method further includes pasting the frame 6 onto the dicing tape 2 to fix the wafer 1. The frame 6 is arranged around the wafer 1 to protect the wafer 1 and avoid possible external damage to the wafer 1, and there is a gap area between the frame 6 and the wafer 1, and the barrier layer 3 of the dicing tape 2 is also arranged in the gap area. When the cutting path 10 of the wafer 1 is etched by a plasma etching process, the gap area will also be etched by the plasma. Since the barrier layer 3 is also arranged in the dicing tape 2 in the gap area, the plasma can be guided away by grounding the barrier layer 3 to ensure that the dicing tape 2 is not damaged. In addition, it is ensured that the inner side of the edge of the wafer 1 is not over-etched, thereby improving the preparation accuracy of the chip.

[0045] In some embodiments, Figure 7As shown, the shape of the orthographic projection of the blocking layer 3 on the first surface 21 is a mesh. The mesh blocking layer 3 includes a first blocking line 31 extending along a first direction X, and a second blocking line 32 extending along a second direction Y. The first direction X and the second direction Y intersect and are parallel to the first surface 21, respectively. The embodiment provided in the present application is described by taking the first direction X and the second direction Y as an example of being perpendicular. The first blocking line 31 and the second blocking line 32 both extend to the gap area. It can be understood that along the first direction X, the first blocking line 31 penetrates the cutting tape 2, and along the second direction Y, the second blocking line 32 also penetrates the cutting tape 2. The mesh blocking layer 3 can be well aligned with the cutting path 10 to improve the process accuracy.

[0046] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for preparing a chip, characterized in that: include: The wafer is attached to a dicing tape, wherein the dicing tape comprises a first surface close to one side of the wafer, and a barrier layer disposed on the first surface, wherein the barrier layer extends from the first surface into the dicing tape, and a surface of the barrier layer close to one side of the wafer is flush with the first surface; the wafer comprises a dicing line, and an orthographic projection of the dicing line on the first surface is located within the region where the barrier layer is located; The dicing lanes of the wafer are cut to cut the wafer into a plurality of chips.

2. The preparation method according to claim 1, characterized in that: Using a plasma etching process to cut the cutting path of the wafer; The material of the barrier layer includes a conductive material.

3. The preparation method according to claim 2, characterized in that: The material of the barrier layer includes at least one of copper, iron or chromium.

4. The preparation method according to claim 1, characterized in that: The width of the barrier layer is greater than the width of the scribe line.

5. The preparation method according to claim 4, characterized in that: Along the width direction of the cutting street, the boundaries of the barrier layer on two opposite sides respectively exceed the boundaries of the cutting street on two opposite sides.

6. The preparation method according to claim 5, characterized in that: The ratio of the distance that the boundary of the barrier layer exceeds the boundary of the cutting street to the width of the cutting street is in the range of 0.05 to 0.

1.

7. The preparation method according to claim 1, characterized in that: The orthographic projection shape of the dicing road of the wafer on the first surface is a mesh shape, and the orthographic projection shape of the blocking layer on the first surface is a mesh shape.

8. The preparation method according to claim 1, characterized in that: The preparation method further comprises: Adhere a frame to the dicing tape, wherein the frame is disposed around the wafer with a gap area between the frame and the wafer; The barrier layer of the dicing tape is also arranged in the gap area.

9. The preparation method according to claim 8, characterized in that: The shape of the orthographic projection of the barrier layer on the first surface is a mesh; The mesh-shaped blocking layer includes first blocking lines extending along a first direction and second blocking lines extending along a second direction, wherein the first direction and the second direction intersect and are parallel to the first surface respectively; The first blocking line and the second blocking line both extend to the gap region.

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