Clock taming and keeping method and system and electronic equipment

Abstract

The invention provides a clock taming and maintaining method and system and electronic equipment, and the method comprises the steps: controlling a voltage control oscillator to generate at least one reference clock through a digital-to-analog converter, and generating each target clock and a local clock according to the demands of the reference clock and each target clock; acquiring a reference signal for clock taming, and performing clock taming on each target clock based on the reference signal and the local clock to obtain a taming result; and acquiring a control value of the digital-to-analog converter and a current temperature value of the voltage-controlled oscillator, calculating a clock taming fitting curve based on the control value and the current temperature value, and performing clock holding based on the clock taming fitting curve. Therefore, the clock taming and maintaining cost can be reduced, the clock maintaining algorithm is simplified, and the clock taming efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of information technology, and in particular to a clock taming and maintaining method, system and electronic equipment. Background Art

[0002] With the rapid development of information technology, in applications that require satellite GNSS synchronized clocks, the clock system can be quickly tamed through the GNSS effective second pulse, and the clock can be used to maintain system operations. When the GNSS second pulse is invalid or the error is too large, the clock frequency can be maintained to ensure the system clock accuracy. The existing clock taming technology is generally implemented by combining high-precision, high-stability, precision oscillators with complex clock taming circuits and algorithms. The steps generally include: receiving GNSS signals through a GNSS receiver and obtaining the reference signal and time position of the second pulse through decoding (transmitted through the serial port UART); sending the reference signal and UART to the CPT atomic clock, and the atomic clock performs jitter processing on the reference signal to eliminate the reference signal jitter caused by atmospheric transmission or GNSS receiver decoding; inputting the reference signal output by the CPT atomic clock and the reference signal generated by the clock output by the local high-precision crystal oscillator into a dedicated delay measurement circuit, and the delay measurement circuit outputs the time deviation of the reference signal; the logic device calculates the control data of the digital-to-analog converter according to the time deviation of the delay circuit, the parameters of the digital-to-analog converter, and the parameters of the high-precision crystal oscillator and realizes the control of the digital-to-analog converter; the high-precision crystal oscillator completes the frequency adjustment according to the voltage of the digital-to-analog converter to achieve the synchronization of the local frequency with the GNSS clock. However, this technology requires a large number of devices to cooperate, which requires a high cost, and requires complex algorithms and a long time to achieve clock taming and maintenance. Summary of the invention

[0003] The purpose of the present application is to provide a clock taming and maintaining method, system and electronic device, which can reduce the cost of clock taming and maintaining, simplify the clock maintaining algorithm, and improve the efficiency of clock taming.

[0004] To achieve the above objectives:

[0005] In a first aspect, an embodiment of the present invention provides a clock taming and maintaining method, the method comprising:

[0006] Controlling a voltage-controlled oscillator through a digital-to-analog converter to generate at least one reference clock, and generating each target clock and a local clock according to the reference clock and each target clock requirement;

[0007] Acquire a reference signal for clock taming, perform clock taming on each target clock based on the reference signal and the local clock, and obtain a taming result;

[0008] A control value of the digital-to-analog converter and a current temperature value of the voltage-controlled oscillator are obtained, a clock taming fitting curve is calculated based on the control value and the current temperature value, and clock maintenance is performed based on the clock taming fitting curve.

[0009] In one embodiment, the reference signal for clock taming is an external input signal;

[0010] Before performing clock training based on the reference signal and the local clock, the method further includes:

[0011] Obtaining the reference signal frequency and the local clock frequency, and comparing whether there is an error between the reference signal frequency and the local clock frequency;

[0012] If yes, clock taming is performed.

[0013] In one implementation, performing clock training based on the reference signal and the local clock to obtain a training result includes:

[0014] Perform error scheduling based on the frequency error and obtain the period error;

[0015] The frequency of the digital-to-analog converter is adjusted based on the period error and a voltage-controlled oscillator to achieve clock training.

[0016] In one implementation, performing error scheduling based on the frequency error and obtaining the period error includes:

[0017] After locking the reference signal state, enabling jumping to the error initial state of the frequency error;

[0018] Determining whether the period error of the initial error state is greater than a first preset error period;

[0019] If yes, it will jump to the error coarse adjustment state and output the error cycle in real time;

[0020] If not, it jumps to the error fine-tuning state and outputs the error cycle in real time.

[0021] In one embodiment, after jumping to the error coarse adjustment state, the method further includes:

[0022] Determine whether the period error is less than a second preset error period, and if so, jump to the error fine adjustment state;

[0023] Otherwise keep the current state.

[0024] In one embodiment, after jumping to the error fine tuning state, the method further includes:

[0025] When it is determined that the error period is 0, the system jumps to the stable judgment state, and adds 1 to the stable count. After the stable count value reaches a preset threshold value, it is determined that the system enters the stable state.

[0026] In one embodiment, the adjusting the frequency of the digital-to-analog converter based on the period error to complete clock taming includes:

[0027] The frequency of the digital-to-analog converter is adjusted according to the following formula:

[0028] V dac =V dac_b +1*(-1) k *50 j ;

[0029] Where V dac_b is the frequency value of the last digital-to-analog converter, K is the positive and negative sign of the periodic error, K is 1 when the periodic error is positive, and K is 0 when the periodic error is negative, j is the coarse and fine adjustment step selection, in the coarse adjustment state, j=1, the adjustment step is ±50, in the fine adjustment state, j=0, the adjustment step is ±1.

[0030] In one embodiment, the calculating of the clock taming fitting curve based on the control value of the digital-to-analog converter and the current temperature value of the voltage-controlled oscillator, and performing clock maintenance based on the clock taming fitting curve include:

[0031] When the state jumps to the stable judgment state, starting the clock holding operation;

[0032] reading the control value of the digital-to-analog converter and the temperature value of the voltage-controlled oscillator in a period of seconds;

[0033] Performing digital-to-analog converter control value fitting according to the control value and the temperature value with a preset temperature value as a resolution, and generating a fitting table;

[0034] The reference signal is continuously detected, and when the reference signal is unlocked or abnormal, the clock is held, a corresponding control value is read from the fitting table according to the temperature value, and the digital-to-analog converter is controlled based on the control value.

[0035] In a second aspect, the present invention provides a clock taming and maintaining system, comprising:

[0036] A reference module, configured to generate at least one reference clock by controlling a voltage-controlled oscillator through a digital-to-analog converter, and generate each target clock and a local clock according to the reference clock and each target clock requirement;

[0037] A training module, which obtains a reference signal for clock training, performs clock training based on the reference signal and the local clock, and obtains a training result;

[0038] The holding module is used to obtain the control value of the digital-to-analog converter and the current temperature value of the voltage-controlled oscillator, calculate a clock taming fitting curve based on the control value and the current temperature value, and perform clock holding based on the clock taming fitting curve.

[0039] In a third aspect, the present invention provides an electronic device, comprising: a processor; a memory for storing instructions executable by the processor; wherein the processor is configured to execute the instructions to implement a clock taming and maintenance method as described in any one of the first aspects.

[0040] The clock taming and holding method, system and electronic device provided by the present invention are based on the characteristics of voltage-controlled oscillators and programmable logic devices (such as FPGAs), adopt relatively simple circuits, make full use of the functions and characteristics of programmable logic devices, and implement functions such as frequency error measurement, frequency control and taming algorithms in programmable logic devices, thereby reducing hardware costs, circuit complexity and power consumption. The present invention combines reference signal jitter processing and taming algorithms, both of which are implemented in programmable logic devices, and is based on fast-response digital-to-analog converters and voltage-controlled oscillators. Compared with the prior art, it can achieve rapid frequency adjustment, thereby reducing the taming time of the entire system. The clock holding of the present invention uses a programmable logic device to implement an algorithm, and implements frequency control based on a digital-to-analog converter and a voltage-controlled oscillator. Compared with the prior art, its implementation method is simple and can be activated immediately after an external reference signal is abnormal, overcoming the problem that the traditional clock holding system requires long-term stable follow-up to work. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 A flowchart of a clock taming and maintaining method provided by an embodiment of the present invention;

[0043] Figure 2 A schematic diagram of modules of a clock taming and maintaining system provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0044] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0045] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0046] See also Figure 1 , is a flowchart of a clock taming and maintaining method provided in an embodiment of the present application. The clock taming and maintaining method can be executed by a clock taming and maintaining system provided in an embodiment of the present application. The system can be implemented in software and / or hardware, such as a server, a computer, a processor and other electronic devices. In this embodiment, the execution subject of the clock taming and maintaining method is a processor of a vehicle terminal as an example. The clock taming and maintaining method provided in this embodiment includes:

[0047] Step S1, controlling a voltage-controlled oscillator through a digital-to-analog converter to generate at least one reference clock, and generating each target clock and a local clock according to the reference clock and each target clock requirement.

[0048] For the sake of simplicity, DAC is used to represent a digital-to-analog converter and VCO is used to represent a voltage-controlled oscillator in the following text.

[0049] Before step S1, the DAC is configured by a programmable logic device according to an initial DAC control value or a result of last clock taming in combination with the current system state.

[0050] Understandably, the DAC can control the output frequency of the VCO very precisely, because it can produce a corresponding analog voltage by changing a tiny digital input, thereby achieving fine frequency adjustment. Since both the DAC and the VCO are electronic components, they respond very quickly and can quickly adapt to the needs of frequency adjustment, which is very important for application scenarios that require fast clock taming.

[0051] Step S2, obtaining a reference signal for clock training, and performing clock training on each target clock based on the reference signal and the local clock to obtain a training result.

[0052] In one embodiment, the reference signal used for clock training is an external input signal; before performing clock training based on the reference signal and the local clock, the method further includes: obtaining the reference signal frequency and the local clock frequency, and comparing whether there is an error between the reference signal frequency and the local clock frequency; if so, performing clock training.

[0053] Here, in addition to determining whether there is an error between the reference signal frequency and the local clock frequency, it is also necessary to determine the validity of the reference signal, and the determination process includes: selecting the corresponding local clock data and reference signal according to the configuration information and the local clock information; parsing the local clock data, if the local clock information is parsed to indicate that the reference signal is valid, then determining the validity of the reference signal frequency, otherwise continue to wait, and issue an alarm when the waiting time exceeds the preset time; determining the validity of the reference signal according to the local clock, if the reference signal is valid and the accuracy of the reference signal is within the valid range, then the reference signal is considered valid, and clock training can be performed according to the reference signal, if the reference signal is invalid or the accuracy is too poor, then wait, and issue an alarm after the waiting time expires.

[0054] In one embodiment, clock training is performed based on the reference signal and the local clock to obtain a training result, including: error scheduling based on the frequency error and obtaining a period error; and the frequency of the digital-to-analog converter is adjusted based on the period error and a voltage-controlled oscillator to complete clock training.

[0055] In this embodiment, the programmable logic device receives an external reference signal and completes a clock taming algorithm in combination with a local clock. The reference signal may come from an input such as a GNSS receiver, 1588v2, or syncE.

[0056] In one implementation, performing error scheduling based on the frequency error and obtaining the period error includes:

[0057] After locking the reference signal state, enabling jumping to the error initial state of the frequency error;

[0058] Determining whether the period error of the initial error state is greater than a first preset error period;

[0059] If yes, it will jump to the error coarse adjustment state and output the error cycle in real time;

[0060] If not, it jumps to the error fine-tuning state and outputs the error cycle in real time.

[0061] Further, after jumping to the error coarse adjustment state, the method further includes:

[0062] Determine whether the period error is less than a second preset error period, and if so, jump to the error fine adjustment state;

[0063] Otherwise keep the current state.

[0064] Furthermore, after jumping to the error fine adjustment state, the method further includes:

[0065] When it is determined that the error period is 0, the system jumps to the stable judgment state, and adds 1 to the stable count. After the stable count value reaches a preset threshold value, it is determined that the system enters the stable state.

[0066] In this embodiment, the first preset error period is 2000 nanoseconds, and the second preset error period is 1000 nanoseconds.

[0067] Specifically, the above process can be described as:

[0068] Check whether the reference signal is valid. If it is valid, start clock taming. Perform clock frequency statistics and count clock cycles within 1S. For example, if the local reference clock is 400MHz, the cycle count within 1S should be 400000000. If the cycle count is not 400000000, there is a frequency error in the local clock and clock taming is required. Perform frequency adjustment state scheduling according to the frequency error (cycle error). The specific state machine steps are as follows:

[0069] (1) Initial state: Waiting for clock taming to enable jumping to the error classification state;

[0070] (2) Error classification state: judge the periodic error. If the periodic error is greater than ±2000ns, it will jump to the error coarse adjustment state, otherwise it will jump to the error fine adjustment state;

[0071] (3) Error coarse adjustment state: judge the period error. If the period error is less than ±1000ns, jump to the error fine adjustment state, otherwise keep it;

[0072] (4) Error fine-tuning state: judge the periodic error. If the periodic error is 0, it will jump to the stable judgment state, otherwise it will remain;

[0073] (5) Stable judgment state: judge the period error. If the period error is 0, the stable count is increased by 1. When the stable count is greater than or equal to N (this value can be dynamically configured, the smaller the value, the shorter the taming time), jump to the stable state; if the period error is greater than ±5ns, jump to the error fine adjustment state;

[0074] (6) Stable state: If the period error is greater than ±5ns, it jumps to the error fine-tuning state, otherwise it remains.

[0075] In one embodiment, the adjusting the frequency of the digital-to-analog converter based on the period error to complete clock taming includes:

[0076] The frequency of the digital-to-analog converter is adjusted according to the following formula:

[0077] V dac =V dac_b +1*(-1) k *50 j ;

[0078] Where V dac_b is the frequency value of the last digital-to-analog converter, K is the positive and negative sign of the periodic error, K is 1 when the periodic error is positive, and K is 0 when the periodic error is negative, j is the coarse and fine adjustment step selection, in the coarse adjustment state, j=1, the adjustment step is ±50, in the fine adjustment state, j=0, the adjustment step is ±1.

[0079] Step S3, obtaining the control value of the digital-to-analog converter and the current temperature value of the voltage-controlled oscillator, calculating a clock taming fitting curve based on the control value and the current temperature value, and performing clock maintenance based on the clock taming fitting curve.

[0080] In one embodiment, step S3 includes: when the jump to the stable judgment state is performed, the clock holding operation is started; the control value of the digital-to-analog converter and the temperature value of the voltage-controlled oscillator are read in seconds; the control value of the digital-to-analog converter is fitted according to the control value and the temperature value with a preset temperature value as the resolution, and a fitting table is generated; the reference signal is continuously detected, and the clock holding is entered when the reference signal is unlocked or abnormal, the corresponding control value is read from the fitting table according to the temperature value, and the digital-to-analog converter is controlled based on the control value.

[0081] The clock taming and maintaining method provided by the present invention realizes high-precision clock taming through low-cost VCO and ADC. By adopting low-cost VCO and low-cost high-precision ADC, in combination with logic devices and clock taming algorithms, clock taming can be realized under extremely low hardware cost conditions. By externally inputting a reference signal, clock taming can be realized quickly, and the shortest taming time can reach 5 seconds. Based on temperature sensors and programmable logic devices, the clock accuracy can be maintained under different temperature conditions, which can greatly simplify the clock maintaining algorithm, reduce circuit complexity, and save costs.

[0082] Based on the same concept of the above embodiments, the embodiment of the present invention provides a clock taming and maintaining system, such as Figure 2 As shown, the clock taming and maintaining system includes:

[0083] A reference module, configured to generate at least one reference clock by controlling a voltage-controlled oscillator through a digital-to-analog converter, and generate each target clock and a local clock according to the reference clock and each target clock requirement;

[0084] A training module, which obtains a reference signal for clock training, performs clock training based on the reference signal and the local clock, and obtains a training result;

[0085] The holding module is used to obtain the control value of the digital-to-analog converter and the current temperature value of the voltage-controlled oscillator, calculate a clock taming fitting curve based on the control value and the current temperature value, and perform clock holding based on the clock taming fitting curve.

[0086] For the specific definition of the clock taming and maintenance system, please refer to the definition of the clock taming and maintenance method above, which will not be repeated here. Each module in the above clock taming and maintenance system can be implemented in whole or in part by software, hardware and a combination thereof. The above modules can be embedded in or independent of the processor of the electronic device in the form of hardware, or can be stored in the memory of the electronic device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0087] Based on the same inventive concept as the aforementioned embodiments, the present invention also provides an electronic device, comprising: a processor; a memory for storing instructions executable by the processor; wherein the processor is configured to execute the instructions to implement a clock taming and maintenance method as described in any one of the aforementioned embodiments.

[0088] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0089] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the attached claims.

Claims

1. A clock taming and maintaining method, characterized in that: include: Controlling a voltage-controlled oscillator through a digital-to-analog converter to generate at least one reference clock, and generating each target clock and a local clock according to the reference clock and each target clock requirement; Acquire a reference signal for clock taming, perform clock taming on each target clock based on the reference signal and the local clock, and obtain a taming result; A control value of the digital-to-analog converter and a current temperature value of the voltage-controlled oscillator are obtained, a clock taming fitting curve is calculated based on the control value and the current temperature value, and clock maintenance is performed based on the clock taming fitting curve.

2. The method according to claim 1, characterized in that The reference signal for clock taming is an external input signal; Before performing clock training based on the reference signal and the local clock, the method further includes: Obtaining the reference signal frequency and the local clock frequency, and comparing whether there is an error between the reference signal frequency and the local clock frequency; If yes, clock taming is performed.

3. The method according to claim 1 or 2, characterized in that: The performing clock training based on the reference signal and the local clock to obtain a training result includes: Perform error scheduling based on the frequency error and obtain the period error; The frequency of the digital-to-analog converter is adjusted based on the period error and a voltage-controlled oscillator to achieve clock training.

4. The method according to claim 3, characterized in that The error scheduling is performed based on the frequency error, and the period error is obtained, including: After locking the reference signal state, enabling jumping to the error initial state of the frequency error; Determining whether the period error of the initial error state is greater than a first preset error period; If yes, it will jump to the error coarse adjustment state and output the error cycle in real time; If not, it jumps to the error fine-tuning state and outputs the error cycle in real time.

5. The method according to claim 4, characterized in that After jumping to the error coarse adjustment state, the method further includes: Determine whether the period error is less than a second preset error period, and if so, jump to the error fine adjustment state; Otherwise keep the current state.

6. The method according to claim 5, characterized in that After jumping to the error fine adjustment state, the method further includes: When it is determined that the error period is 0, the system jumps to the stable judgment state, and adds 1 to the stable count. After the stable count value reaches a preset threshold value, it is determined that the system enters the stable state.

7. The method according to any one of claims 4 to 6, characterized in that: The step of adjusting the frequency of the digital-to-analog converter based on the period error to complete clock taming includes: The frequency of the digital-to-analog converter is adjusted according to the following formula: V dac =V dac_b +1*(-1) k *50 j ; Where V dac_b is the frequency value of the last digital-to-analog converter, K is the positive and negative sign of the periodic error, K is 1 when the periodic error is positive, and K is 0 when the periodic error is negative, j is the coarse and fine adjustment step selection, in the coarse adjustment state, j=1, the adjustment step is ±50, in the fine adjustment state, j=0, the adjustment step is ±1.

8. The method according to claim 6, characterized in that The step of calculating a clock taming fitting curve based on the control value of the digital-to-analog converter and the current temperature value of the voltage-controlled oscillator, and performing clock maintenance based on the clock taming fitting curve includes: When the state jumps to the stable judgment state, starting the clock holding operation; reading the control value of the digital-to-analog converter and the temperature value of the voltage-controlled oscillator in a period of seconds; Performing digital-to-analog converter control value fitting according to the control value and the temperature value with a preset temperature value as a resolution, and generating a fitting table; The reference signal is continuously detected, and when the reference signal is unlocked or abnormal, the clock is held, a corresponding control value is read from the fitting table according to the temperature value, and the digital-to-analog converter is controlled based on the control value.

9. A clock taming and maintaining system, characterized in that: include: A reference module, configured to generate at least one reference clock by controlling a voltage-controlled oscillator through a digital-to-analog converter, and generate each target clock and a local clock according to the reference clock and each target clock requirement; A training module, which obtains a reference signal for clock training, performs clock training based on the reference signal and the local clock, and obtains a training result; The holding module is used to obtain the control value of the digital-to-analog converter and the current temperature value of the voltage-controlled oscillator, calculate a clock taming fitting curve based on the control value and the current temperature value, and perform clock holding based on the clock taming fitting curve.

10. An electronic device, characterized in that: include: processor; a memory for storing instructions executable by the processor; The processor is configured to execute the instructions to implement the clock taming and maintaining method as described in any one of claims 1-8.

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