Thin film resistance device and preparation method thereof

Abstract

The invention discloses a thin film resistor device and a preparation method thereof. The preparation method comprises the following steps: forming a second insulating layer on a first metal interconnection layer and an exposed first insulating layer; forming a thin-film resistor structure in a partial region of the upper surface of the second insulating layer; forming a third insulating layer on the thin-film resistor structure and the exposed upper surface of the second insulating layer; forming a first contact hole extending from the upper surface of the third insulating layer to the first metal interconnection layer, and filling the first contact hole with first contact metal; forming a second metal interconnection layer on the upper surface of the third insulating layer; forming a fourth insulating layer on the second metal interconnection layer and the exposed third insulating layer; and forming a second contact hole extending from the upper surface of the fourth insulating layer to the second metal interconnection layer and a third contact hole extending from the upper surface of the fourth insulating layer to the thin-film resistor structure, and filling second contact metal and third contact metal in the second contact hole and the third contact hole respectively. According to the thin film resistor device and the preparation method thereof, the stability of the device can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of thin film resistors, and in particular to a thin film resistor device and a method for preparing the same. Background Art

[0002] Thin film resistors such as chrome silicon thin film resistors are widely used in hybrid integrated circuits due to their excellent properties such as high resistivity, low temperature coefficient of resistance, high stability, no parasitic effects and easy film formation.

[0003] For the thin film resistor device in the related art, its thin film resistor structure is usually located in the insulating layer between two adjacent metal interconnection layers. The preparation method of the thin film resistor device in the related art usually includes the following steps: firstly forming a second insulating layer covering the first metal interconnection layer located on the first insulating layer and planarizing it, then forming a thin film resistor structure on the second insulating layer, then forming a third insulating layer covering the thin film resistor structure and planarizing it, then forming a first contact hole extending from the upper surface of the third insulating layer to the first metal interconnection layer and a second contact hole extending from the upper surface of the third insulating layer to the thin film resistor structure, and filling contact metal therein, then forming a second metal interconnection layer on the third insulating layer, the first part of the second metal interconnection layer is conductively connected to the first metal interconnection layer through the contact metal, and the second part of the second metal interconnection layer is conductively connected to the thin film resistor structure through the contact metal.

[0004] The problems existing in the preparation method of thin film resistor devices in the related art are: 1) The thickness of the third insulating layer is usually thin, and the third insulating layer is easily over-grinded and damaged to the thin film resistor structure when it is flattened; 2) When etching to form the first contact hole and the second contact hole, since the depth of the second contact hole is too small and the depth is significantly smaller than that of the first contact hole, the thin film resistor structure is easily over-etched, causing damage to the thin film resistor structure.

[0005] Therefore, improvements are needed to at least partially solve the above problems. Summary of the invention

[0006] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0007] In order to at least partially solve the above problems, according to a first aspect of the present invention, a method for preparing a thin film resistor device is provided, comprising:

[0008] Providing a semiconductor structure, wherein the semiconductor structure comprises a first insulating layer and a first metal interconnection layer located on the first insulating layer;

[0009] forming a second insulating layer on the first metal interconnection layer and on the exposed first insulating layer, and planarizing an upper surface of the second insulating layer;

[0010] forming a thin film resistor structure in a partial area of ​​the upper surface of the second insulating layer;

[0011] forming a third insulating layer on the thin film resistor structure and the exposed upper surface of the second insulating layer;

[0012] forming a first contact hole extending from the upper surface of the third insulating layer to the first metal interconnection layer, and filling the first contact hole with a first contact metal;

[0013] forming a second metal interconnection layer on the upper surface of the third insulating layer, wherein the second metal interconnection layer is conductively connected to the first metal interconnection layer through the first contact metal;

[0014] forming a fourth insulating layer on the second metal interconnection layer and the exposed third insulating layer, and planarizing an upper surface of the fourth insulating layer;

[0015] Forming a second contact hole extending from the upper surface of the fourth insulating layer to the second metal interconnection layer and a third contact hole extending from the upper surface of the fourth insulating layer to the thin film resistor structure, and filling the second contact hole and the third contact hole with a second contact metal and a third contact metal respectively;

[0016] A third metal interconnection layer is formed on the upper surface of the fourth insulating layer, wherein a first portion of the third metal interconnection layer is conductively connected to the second metal interconnection layer through the second contact metal, and a second portion of the third metal interconnection layer is conductively connected to the thin film resistor structure through the third contact metal.

[0017] Exemplarily, a diameter of the second contact hole is larger than a diameter of the third contact hole.

[0018] Exemplarily, the thin film resistor structure includes a resistor layer, a first contact pad and a second contact pad, the resistor layer is located on the upper surface of the second insulating layer, and the first contact pad and the second contact pad are both located on the upper surface of the resistor layer and are spaced apart;

[0019] There are two third contact holes, and the two third contact holes extend to the first contact pad and the second contact pad respectively.

[0020] Exemplarily, the first contact pad and the second contact pad each include a conductive layer and an anti-reflective coating layer stacked in layers;

[0021] The third contact hole extends to the conductive layer, and the bottom of the third contact metal contacts the conductive layer.

[0022] Exemplarily, the material of the resistor layer includes at least one of chromium silicon, nickel silicon, titanium nitride, titanium tungsten, titanium nitride and titanium nitride silicon;

[0023] The conductive layer is a titanium nitride layer.

[0024] Exemplarily, a distance between an upper surface of the first metal interconnection layer and an upper surface of the planarized second insulating layer is 550 nm-650 nm.

[0025] Exemplarily, the third insulating layer formed on the thin film resistor structure and the exposed upper surface of the second insulating layer has a thickness of 200 nm-300 nm.

[0026] Exemplarily, a distance between an upper surface of the second metal interconnection layer and an upper surface of the planarized fourth insulating layer is 700 nm-800 nm.

[0027] Exemplarily, the semiconductor structure also includes a substrate, a plurality of fourth contact holes are provided in the first insulating layer between the first metal interconnection layer and the substrate, the fourth contact holes are filled with a fourth contact metal, and the first metal interconnection layer is conductively connected to the substrate through the fourth contact metal.

[0028] According to a second aspect of the present invention, a thin film resistor device is provided. The thin film resistor device is manufactured by the manufacturing method described above.

[0029] According to the thin film resistor device and its preparation method of the present invention, on the one hand, after forming the third insulating layer, it is not directly flattened, but a first contact hole extending from the upper surface of the third insulating layer to the first metal interconnection layer is formed, and the first contact metal is filled in the first contact hole, thereby effectively avoiding the flattening damage to the thin film resistor structure; on the other hand, after forming the fourth insulating layer, a second contact hole extending from the upper surface of the fourth insulating layer to the second metal interconnection layer and a third contact hole extending from the upper surface of the fourth insulating layer to the thin film resistor structure are formed, and the second contact hole and the third contact hole are filled with the second contact metal and the third contact metal respectively, and the depth of the third contact hole is greater than the distance between the second metal interconnection layer and the third metal interconnection layer, thereby, when etching to form the third contact hole, the thin film resistor structure is not easy to be over-etched, and the thin film resistor structure is not easy to be damaged. Furthermore, the thin film resistor device formed by the preparation method of the present application can have higher performance stability and higher product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The following drawings of the present application are hereby used as part of the present application for understanding the present application. The drawings show the embodiments of the present application and their descriptions, and are used to explain the device and principle of the present application. In the drawings,

[0031] Figures 1A-1F It is a cross-sectional schematic diagram of each step of a method for preparing a thin film resistor device in the related art;

[0032] Figure 2 is a schematic flow chart of a method for preparing a thin film resistor device according to an embodiment of the present application;

[0033] Figures 3A-3K The diagram is a cross-sectional view of each step of a method for preparing a thin film resistor device according to an embodiment of the present application.

[0034] Description of reference numerals:

[0035] 100 - semiconductor structure, 101 - first insulating layer, 102 - first metal interconnection layer, 110 - second insulating layer, 120 - thin film resistor structure, 130 - third insulating layer, 131 - first contact hole, 132 - second contact hole, 140 - contact metal, 150 - contact metal, 160 - second metal interconnection layer;

[0036] 200-semiconductor structure, 201-first insulating layer, 202-first metal interconnection layer, 203-substrate, 204-fourth contact metal, 210-second insulating layer, 220-thin film resistor structure, 221-resistor layer, 222-first contact pad, 223-second contact pad, 2201-resistor material layer, 2202-conductive layer, 2203-anti-reflective coating, 230-third insulating layer, 231-first contact hole, 240-first contact metal, 250-second metal interconnection layer, 260-fourth insulating layer, 261-second contact hole, 262-third contact hole, 270-second contact metal, 280-third contact metal, 290-third metal interconnection layer. DETAILED DESCRIPTION

[0037] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present application. However, it is apparent to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features well known in the art are not described.

[0038] It should be understood that the present application can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present application to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0039] It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0040] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures.

[0041] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0042] Embodiments of the invention are described herein with reference to cross-sectional views as schematic diagrams of ideal embodiments (and intermediate structures) of the present application. Thus, variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the present application should not be limited to the specific shapes shown herein, but include shape deviations due to, for example, manufacturing. Therefore, what is shown in the figures is schematic in nature, and their shapes are not intended to display the actual shape of the device and are not intended to limit the scope of the present application.

[0043] See attached Figures 1A-1F The following is an exemplary description of a method for preparing a thin film resistor device in the related art.

[0044] First, see the attached Figure 1A , a semiconductor structure 100 is provided, which includes a first insulating layer 101 and a first metal interconnection layer 102 located on the first insulating layer 101.

[0045] Then, see Appendix Figure 1B A second insulating layer 110 is formed on the first metal interconnection layer 102 and the exposed first insulating layer 101, and the second insulating layer 110 is planarized, so that the second insulating layer 110 covers the first metal interconnection layer 102 located on the first insulating layer 101. The distance between the upper surface of the planarized second insulating layer 110 and the upper surface of the first metal interconnection layer 102 is generally 300nm-350nm.

[0046] Then, see Appendix Figure 1C A thin film resistor structure 120 is formed on a partial area of ​​the second insulating layer 110 .

[0047] Then, see Appendix Figure 1D , a third insulating layer 130 is formed on the thin film resistor structure 120 and the exposed second insulating layer 110, and the third insulating layer 110 is planarized, and the third insulating layer 110 covers the thin film resistor structure 120. The distance between the upper surface of the planarized third insulating layer 110 and the upper surface of the thin film resistor structure 120 is generally 350nm-400nm.

[0048] Then, see Appendix Figure 1E A first contact hole 131 extending from the upper surface of the third insulating layer 130 to the first metal interconnection layer 102 and a second contact hole 132 extending from the upper surface of the third insulating layer 130 to the thin film resistor structure 120 are formed by an etching process, and a contact metal 140 and a contact metal 150 are filled in the first contact hole 131 and the second contact hole 132, respectively. The contact metal 140 and the contact metal 150 are used to realize the electrical extraction of the first metal interconnection layer and the thin film resistor structure 120, respectively.

[0049] Finally, see Appendix Figure 1F A second metal interconnection layer 160 is formed on the third insulating layer 130 , a first portion of the second metal interconnection layer 160 is conductively connected to the first metal interconnection layer 102 via the contact metal 140 , and a second portion of the second metal interconnection layer 160 is conductively connected to the thin film resistor structure 120 via the contact metal 150 .

[0050] The problems existing in the preparation method of the thin film resistor device in the related art are: 1) Since the spacing between two adjacent metal interconnection layers is usually 750nm-850nm, the thin film resistor structure and the third insulating layer 130 are located between the two adjacent metal interconnection layers. Therefore, the thickness of the third insulating layer 130 is usually thin, and it is easy to over-grind and damage the thin film resistor structure 120 when the third insulating layer 130 is planarized; 2) When etching to form the first contact hole 131 and the second contact hole 132, since the depth of the second contact hole 132 is relatively small and the depth is significantly smaller than that of the first contact hole 131, the thin film resistor structure 120 is easily over-etched, causing damage to the thin film resistor structure 120 and affecting the device performance.

[0051] See attached Figure 2 The following is an exemplary description of a method for preparing a thin film resistor device according to an embodiment of the present application. The method for preparing a thin film resistor device comprises the following steps:

[0052] S10: providing a semiconductor structure, wherein the semiconductor structure comprises a first insulating layer and a first metal interconnection layer located on the first insulating layer.

[0053] S20: forming a second insulating layer on the first metal interconnection layer and the exposed first insulating layer, and planarizing an upper surface of the second insulating layer.

[0054] S30: forming a thin film resistor structure in a partial area of ​​the upper surface of the second insulating layer.

[0055] S40: forming a third insulating layer on the thin film resistor structure and the exposed upper surface of the second insulating layer.

[0056] S50: forming a first contact hole extending from the upper surface of the third insulating layer to the first metal interconnection layer, and filling the first contact hole with a first contact metal.

[0057] S60: forming a second metal interconnection layer on the upper surface of the third insulating layer, wherein the second metal interconnection layer is conductively connected to the first metal interconnection layer through the first contact metal.

[0058] S70: forming a fourth insulating layer on the second metal interconnection layer and the exposed third insulating layer, and planarizing an upper surface of the fourth insulating layer.

[0059] S80: forming a second contact hole extending from the upper surface of the fourth insulating layer to the second metal interconnection layer and a third contact hole extending from the upper surface of the fourth insulating layer to the thin film resistor structure, and filling the second contact hole and the third contact hole with a second contact metal and a third contact metal, respectively.

[0060] S90: forming a third metal interconnection layer on the upper surface of the fourth insulating layer, wherein a first portion of the third metal interconnection layer is conductively connected to the second metal interconnection layer through the second contact metal, and a second portion of the third metal interconnection layer is conductively connected to the thin film resistor structure through the third contact metal.

[0061] According to the thin film resistor device and its preparation method of the present application, on the one hand, after forming the third insulating layer, it is not directly flattened, but a first contact hole extending from the upper surface of the third insulating layer to the first metal interconnection layer is formed, and the first contact metal is filled in the first contact hole, thereby effectively avoiding the flattening damage to the thin film resistor structure; on the other hand, after forming the fourth insulating layer, a second contact hole extending from the upper surface of the fourth insulating layer to the second metal interconnection layer and a third contact hole extending from the upper surface of the fourth insulating layer to the thin film resistor structure are formed, and the second contact hole and the third contact hole are filled with the second contact metal and the third contact metal respectively, and the depth of the third contact hole is greater than the distance between the second metal interconnection layer and the third metal interconnection layer, thereby, when etching to form the third contact hole, the thin film resistor structure is not easy to be over-etched, and it is not easy to cause damage to the thin film resistor structure. Furthermore, the thin film resistor device prepared by the preparation method of the present application can have higher performance stability and higher product yield.

[0062] See attached Figures 3A-3K The above steps S10-S90 are described in detail.

[0063] In step S10, see the attached Figure 3A , providing a semiconductor structure 200. The semiconductor structure 200 includes a substrate 203, a first insulating layer 201, a fourth contact metal 204 and a first metal interconnection layer 202. The substrate 203 may be any suitable semiconductor substrate, such as a silicon substrate, and may also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, and also include a multilayer structure composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or may also be double-side polished silicon wafers (Double Side Polished Wafers, DSP), or may also be ceramic substrates such as alumina, quartz or glass substrates, etc.

[0064] The first insulating layer 201 is located on the substrate 203. Exemplarily, the first insulating layer 201 can be formed on the substrate 203 by a CVD (Chemical Vapor Deposition) process or a thermal oxidation process, and the first insulating layer 201 is also an ILD (Interlayer Dielectric) layer. Exemplarily, the first insulating layer 201 can be a silicon dioxide layer. After the first insulating layer 201 is formed, it can be planarized by a CMP (Chemical Mechanical Polishing) process for subsequent steps.

[0065] A plurality of fourth contact holes are provided in the first insulating layer 201, and the fourth contact holes are filled with fourth contact metal 204, and the bottom of the fourth contact metal 204 is in contact with the substrate 203. Exemplarily, a patterned mask layer can be formed on the upper surface of the first insulating layer 201, and then the first insulating layer 201 is etched using the mask layer as a mask to form fourth contact holes penetrating the first insulating layer 201, and then the fourth contact metal 204 is deposited in the fourth contact holes by a CVD process or PVD (Physical Vapor Deposition), and then the fourth contact metal 204 higher than the first insulating layer 201 is polished by a CMP process to make the upper surface of the fourth contact metal 204 flush with the upper surface of the first insulating layer 201. Exemplarily, the fourth contact metal 204 can be tungsten.

[0066] The first metal interconnection layer 202 is located on the first insulating layer 201. Exemplarily, first, a metal layer is formed on the first insulating layer 201. Then, a mask layer is formed on the metal layer, and the mask layer is patterned, and then the metal layer is etched by an etching process using the patterned mask layer as a mask to form the first metal interconnection layer 202. The material of the first metal interconnection layer 202 may include aluminum or copper. In some embodiments, the first metal interconnection layer 202 includes a titanium layer, a titanium nitride layer, an aluminum layer, a titanium nitride layer, and a titanium layer stacked from bottom to top. In some embodiments, the first metal interconnection layer 202 may also include an anti-reflective coating 2203. The first metal interconnection layer 202 is conductively connected to the substrate 203 through the fourth contact metal 204.

[0067] In some other embodiments, the semiconductor structure 200 may be other structural forms known to those skilled in the art, including a first insulating layer 201 and a first metal interconnection layer 202 located on the first insulating layer 201 , which is not specifically limited in the present application.

[0068] In step S20, see the attached Figure 3B, a second insulating layer 210 is formed on the first metal interconnect layer 202 and the exposed first insulating layer 201 (i.e., on the first insulating layer 201 not covered by the first metal interconnect layer 202) by a deposition process such as a CVD process, and the upper surface of the second insulating layer 210 is planarized by a planarization process such as a CMP (Chemical Mechanical Polishing) process. Exemplarily, the distance between the upper surface of the first metal interconnect layer 202 and the upper surface of the planarized second insulating layer 210 is 550nm-650nm. Controlling the distance within the above range can avoid over-grinding in the planarization process and damage to the first metal interconnect layer 202.

[0069] In step S30, first, see the attached Figure 3C , a resistor material layer 2201, a conductive layer 2202 and an anti-reflective coating 2203 are formed layer by layer on the second insulating layer 210. The material of the resistor material layer 2201 includes at least one of chromium silicon, nickel silicon, titanium nitride, titanium tungsten, tantalum nitride and tantalum silicon nitride, and the resistor material layer 2201 can be formed on the second insulating layer 210 by a process such as sputtering coating. The material of the conductive layer 2202 can be titanium nitride, and the conductive layer 2202 can be formed on the resistor material layer 2201 by a process such as ALD (atomic layer deposition) or CVD. In some embodiments, the material of the conductive layer 2202 can also be a metal, such as tungsten. The anti-reflective coating 2203 can be a dielectric anti-reflective coating 2203 (DARC), and the anti-reflective coating 2203 can be formed on the conductive layer 2202 by a process such as spin coating. The material of the anti-reflective coating 2203 can be SiON (silicon oxynitride), SiOCH, etc.

[0070] Then, see Appendix Figure 3D , patterning the anti-reflective coating 2203, and then etching the conductive layer 2202 by dry or wet etching process with the patterned anti-reflective coating 2203 as a mask, so as to form a first contact pad 222 and a second contact pad 223 spaced apart on the resistor material layer 2201, wherein the first contact pad 222 and the second contact pad 223 both include a conductive layer 2202 and an anti-reflective coating 2203 arranged in a stacked manner. Exemplarily, a photoresist may be uniformly coated on the anti-reflective coating 2203, and then exposed by an exposure device (e.g., a photolithography machine), and then the exposed area or the non-exposed area may be selectively removed by a developer, and then the anti-reflective coating 2203 may be etched by, for example, a dry etching process with the photoresist as a mask, so as to achieve patterning of the anti-reflective coating 2203.

[0071] Then, see Appendix Figure 3E, patterning the resistor material layer 2201 to form a resistor layer 221 (the resistor layer 221 is the resistor material layer 2201 after patterning), that is, removing the resistor material layer 2201 layer in unnecessary areas. Exemplarily, a photoresist can be coated on the first contact pad 222, the second contact pad 223 and the exposed resistor material layer 2201, and then exposed by an exposure device (such as a photolithography machine), and then selectively remove the exposed area or the non-exposed area with a developer, and then use the photoresist as a mask to etch the resistor material layer 2201 by a process such as dry etching to form the resistor layer 221, and finally, remove the photoresist. The resistor layer 221 is located on the upper surface of the second insulating layer 210, and the first contact pad 222 and the second contact pad 223 are both located on the side of the resistor layer 221 away from the second insulating layer 210, and are spaced apart. The first contact pad 222 and the second contact pad 223 (ie, the conductive layer 2202 in the first contact pad 222 and the conductive layer 2202 in the second contact pad 223) are conductively connected via the resistor layer 221. The resistor layer 221, the first contact pad 222 and the second contact pad 223 together form a thin film resistor structure 220.

[0072] In some other embodiments, the first contact pad 222 and the second contact pad 223 may only include a conductive layer 2202 (but not an anti-reflective coating 2203). Accordingly, the resistor material layer 2201 and the conductive layer 2202 may be formed layer by layer on the second insulating layer 210, and then a patterned mask layer may be formed on the conductive layer 2202. The conductive layer 2202 may then be etched using the mask layer as a mask to form the first contact pad 222 and the second contact pad 223 that are spaced apart. The mask layer may then be removed, and then the resistor material layer 2201 may be patterned to form a resistor layer 221.

[0073] In step S40, see the attached Figure 3F A third insulating layer 230 is formed on the thin film resistor structure 220 and the exposed upper surface of the second insulating layer 210 (i.e., on the second insulating layer 210 not covered by the thin film resistor structure 220) by a deposition process such as a CVD process. Exemplarily, the third insulating layer 230 may be a silicon dioxide layer. Exemplarily, the thickness of the third insulating layer 230 is 200 nm-300 nm.

[0074] In step S50, see the attached Figure 3GFirst, a patterned mask layer is formed on the third insulating layer 230 to define the position of the first contact hole 231, and then the third insulating layer 230 and the second insulating layer 210 are etched by a dry etching process, such as to form a first contact hole 231 extending from the upper surface of the third insulating layer 230 to the first metal interconnection layer 202, and the bottom of the first contact hole 231 exposes the first metal interconnection layer 202. Then, the mask layer is removed, and a first contact metal 240 is deposited in the first contact hole 231 by a CVD process, such as to deposit the first contact metal 240. The bottom of the first contact metal 240 contacts the first metal interconnection layer 202. Finally, the first contact metal 240 above the upper surface of the third insulating layer 230 can be removed by a CMP process, so that the upper surface of the first contact metal 240 is flush with the upper surface of the third insulating layer 230. It should be noted that filling the first contact metal 240 in the first contact hole 231 may include the steps of depositing the first contact metal 240 in the first contact hole 231 and removing the first contact metal 240 above the upper surface of the third insulating layer 230. Exemplarily, the material of the first contact metal 240 may be tungsten.

[0075] In step S60, see the attached Figure 3H First, a metal layer is formed on the third insulating layer 230. Then, a mask layer is formed on the metal layer, and the mask layer is patterned. Then, the metal layer is etched by an etching process using the patterned mask layer as a mask to form a second metal interconnection layer 250. The second metal interconnection layer 250 contacts the top of the first contact metal 240 filled in the first through hole and completely covers the top of the contact metal. The second metal interconnection layer 250 is conductively connected to the first metal interconnection layer 202 through the first contact metal 240. Finally, the mask is removed. The material of the second metal interconnection layer 250 may include aluminum or copper. In some embodiments, the second metal interconnection layer 250 includes a titanium layer, a titanium nitride layer, an aluminum layer, a titanium nitride layer, and a titanium layer stacked from bottom to top.

[0076] In step S70, see the attached Fig. 3I , a fourth insulating layer 260 is formed on the second metal interconnect layer 250 and on the exposed third insulating layer 230 (i.e., on the third insulating layer 230 not covered by the second metal interconnect layer 250) by a deposition process such as a CVD process, and the upper surface of the fourth insulating layer 260 is planarized by a planarization process such as a CMP process. Exemplarily, the fourth insulating layer 260 may be a silicon dioxide layer. Exemplarily, the distance between the upper surface of the second metal interconnect layer 250 and the upper surface of the planarized fourth insulating layer 260 is 700nm-800nm.

[0077] In step S80, see the attached Figure 3JFirst, a patterned mask layer is formed on the fourth insulating layer 260 to define the positions of the second contact hole 261 and the third contact hole 262, and then the fourth insulating layer 260 and the third insulating layer 230 are etched by a dry etching process, such as a dry etching process, to form a second contact hole 261 extending from the upper surface of the fourth insulating layer 260 to the second metal interconnection layer 250 and a third contact hole 262 extending from the upper surface of the fourth insulating layer 260 to the thin film resistor structure 220. The bottom of the second contact hole 261 exposes the second metal interconnection layer 250. There are two third contact holes 262, and the two third contact holes 262 extend to the first contact pad 222 and the second contact pad 223 respectively. Specifically, the two third contact holes 262 extend to the conductive layer 2202 in the first contact pad 222 and the conductive layer 2202 in the second contact pad 223, and the bottom of the third contact holes 262 exposes the conductive layer 2202. Then, the mask layer is removed, and the second contact metal 270 and the third contact metal 280 are deposited in the second contact hole 261 and the third contact hole 262 respectively by a CVD process, for example. The bottom of the second contact metal 270 contacts the second metal interconnection layer 250, and the bottoms of the two third contact metals 280 contact the first contact pad 222 and the second contact pad 223, respectively, specifically, contact the conductive layer 2202 in the first contact pad 222 and the conductive layer 2202 in the second contact pad 223, respectively. Finally, the second contact metal 270 and the third contact metal 280 above the upper surface of the fourth insulating layer 260 can be removed by a CMP process, so that the upper surface of the second contact metal 270 and the upper surface of the third contact metal 280 are flush with the upper surface of the fourth insulating layer 260 at the same time. The second contact metal 270 and the third contact metal 280 are used to realize the electrical extraction of the second metal interconnection layer 250 and the thin film resistor structure 220, respectively. Exemplarily, the material of the second contact metal 270 and the third contact metal 280 can be tungsten. It should be noted that filling the second contact metal 270 and the third contact metal 280 in the second contact hole 261 and the third contact hole 262 may include the steps of depositing the contact metal in the second contact hole 261 and the third contact hole 262 and removing the contact metal above the upper surface of the fourth insulating layer 260 .

[0078] Since the depth of the third contact hole 262 is greater than the distance between the second metal interconnection layer 250 and the third metal interconnection layer 290 (the depth of the second contact hole 261 is not too small), and the depth of the second contact hole 261 is relatively close to the depth of the third contact hole 262, when etching to form the third contact hole 262, the etching process is easier to control, and the thin film resistor structure 220 (the conductive layer 2202 and the resistor layer 221) is not easy to be over-etched, and the thin film resistor structure 220 is not easy to be damaged.

[0079] Exemplarily, the aperture of the second contact hole 261 is larger than the aperture of the third contact hole 262. Since the depth of the second contact hole 261 is larger than the depth of the third contact hole 262, by configuring the aperture of the second contact hole 261 to be larger than the aperture of the third contact hole 262, the second contact hole 261 and the third contact hole 262 can be etched to a required depth in as close an etching time as possible, thereby better avoiding over-etching.

[0080] In step S90, see the attached Figure 3K First, a metal layer is formed on the fourth insulating layer 260. Then, a mask layer is formed on the metal layer, and the mask layer is patterned. Then, the metal layer is etched by an etching process using the patterned mask layer as a mask to form a third metal interconnection layer 290. Finally, the mask is removed. The first portion of the third metal interconnection layer 290 contacts the top of the second contact metal 270 filled in the second through hole and completely covers the top of the second contact metal 270; the second portion of the third metal interconnection layer 290 contacts the top of the third contact metal 280 filled in the third through hole and completely covers the top of the third contact metal 280. That is, the first portion of the third metal interconnection layer 290 is conductively connected to the second metal interconnection layer 250 through the second contact metal 270, and the second portion of the third metal interconnection layer 290 is conductively connected to the thin film resistor structure 220 through the third contact metal 280. The material of the third metal interconnection layer 290 may include aluminum or copper. In some embodiments, the third metal interconnection layer 290 includes a titanium layer, a titanium nitride layer, an aluminum layer, a titanium nitride layer, and a titanium layer stacked from bottom to top.

[0081] At this point, the process steps of the method for preparing a thin film resistor device according to an embodiment of the present application have been completed. It can be understood that the method for preparing a thin film resistor device of this embodiment not only includes the above steps, but may also include other necessary steps before, during or after the above steps, which are all included in the scope of the preparation method of this embodiment.

[0082] The present application also provides a thin film resistor device, which is prepared by the above-mentioned preparation method. The thin film resistor device prepared by the above-mentioned preparation method can have higher performance stability and higher product yield.

[0083] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely exemplary and are not intended to limit the scope of the present application to this. Those of ordinary skill in the art may make various changes and modifications therein without departing from the scope and spirit of the present application. All these changes and modifications are intended to be included within the scope of the present application as required by the appended claims.

[0084] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0085] Similarly, it should be understood that in order to streamline the present application and help understand one or more of the various inventive aspects, in the description of the exemplary embodiments of the present application, the various features of the present application are sometimes grouped together into a single embodiment, figure, or description thereof. However, the method of the present application should not be interpreted as reflecting the following intention: the claimed application requires more features than the features clearly stated in each claim. More specifically, as reflected in the corresponding claims, the inventive point is that the corresponding technical problem can be solved with features less than all the features of a single disclosed embodiment. Therefore, the claims following the specific embodiment are hereby explicitly incorporated into the specific embodiment, wherein each claim itself serves as a separate embodiment of the present application.

[0086] It will be understood by those skilled in the art that, except for mutually exclusive features, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this specification may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0087] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0088] It should be noted that the above-mentioned embodiments illustrate rather than limit the invention and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims.

Claims

1. A method for preparing a thin film resistor device, characterized in that: include: Providing a semiconductor structure, wherein the semiconductor structure comprises a first insulating layer and a first metal interconnection layer located on the first insulating layer; forming a second insulating layer on the first metal interconnection layer and on the exposed first insulating layer, and planarizing an upper surface of the second insulating layer; forming a thin film resistor structure in a partial area of ​​the upper surface of the second insulating layer; forming a third insulating layer on the thin film resistor structure and on the exposed upper surface of the second insulating layer; forming a first contact hole extending from the upper surface of the third insulating layer to the first metal interconnection layer, and filling the first contact hole with a first contact metal; forming a second metal interconnection layer on the upper surface of the third insulating layer, wherein the second metal interconnection layer is conductively connected to the first metal interconnection layer through the first contact metal; forming a fourth insulating layer on the second metal interconnection layer and the exposed third insulating layer, and planarizing an upper surface of the fourth insulating layer; Forming a second contact hole extending from the upper surface of the fourth insulating layer to the second metal interconnection layer and a third contact hole extending from the upper surface of the fourth insulating layer to the thin film resistor structure, and filling the second contact hole and the third contact hole with a second contact metal and a third contact metal respectively; A third metal interconnection layer is formed on the upper surface of the fourth insulating layer, wherein a first portion of the third metal interconnection layer is conductively connected to the second metal interconnection layer through the second contact metal, and a second portion of the third metal interconnection layer is conductively connected to the thin film resistor structure through the third contact metal.

2. The preparation method according to claim 1, characterized in that: The diameter of the second contact hole is larger than that of the third contact hole.

3. The preparation method according to claim 1, characterized in that: The thin film resistor structure comprises a resistor layer, a first contact pad and a second contact pad, the resistor layer is located on the upper surface of the second insulating layer, the first contact pad and the second contact pad are both located on the upper surface of the resistor layer and are spaced apart; There are two third contact holes, and the two third contact holes extend to the first contact pad and the second contact pad respectively.

4. The preparation method according to claim 3, characterized in that: The first contact pad and the second contact pad each include a conductive layer and an anti-reflection coating layer that are stacked; The third contact hole extends to the conductive layer, and the bottom of the third contact metal contacts the conductive layer.

5. The preparation method according to claim 4, characterized in that: The material of the resistor layer includes at least one of chrome silicon, nickel silicon, titanium nitride, titanium tungsten, titanium nitride and titanium nitride silicon; The conductive layer is a titanium nitride layer.

6. The preparation method according to claim 1, characterized in that: The distance between the upper surface of the first metal interconnection layer and the upper surface of the planarized second insulating layer is 550nm-650nm.

7. The preparation method according to claim 1, characterized in that: The third insulating layer formed on the thin film resistor structure and the exposed upper surface of the second insulating layer has a thickness of 200 nm to 300 nm.

8. The preparation method according to claim 1, characterized in that: The distance between the upper surface of the second metal interconnection layer and the upper surface of the planarized fourth insulating layer is 700nm-800nm.

9. The preparation method according to claim 1, characterized in that: The semiconductor structure also includes a substrate, a plurality of fourth contact holes are arranged in the first insulating layer between the first metal interconnection layer and the substrate, the fourth contact holes are filled with fourth contact metal, and the first metal interconnection layer is conductively connected to the substrate through the fourth contact metal.

10. A thin film resistor device, characterized in that: The thin film resistor device is prepared by the preparation method according to any one of claims 1 to 9.

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