Ramp generator, analog-to-digital converter, image sensor, electronic device, and vehicle

Abstract

The invention discloses a ramp generator, an analog-to-digital converter and an image sensor, the ramp generator comprises a ramp generation circuit and a correction circuit, and the ramp generation circuit is used for generating a ramp signal; the input end of the correction circuit is connected with the output end of the slope generation circuit, the output end of the correction circuit is connected with the slope signal slope adjusting end of the slope generation circuit, and the correction circuit is used for generating a slope adjusting signal so as to adjust the slope of the slope signal of each slope generation period of the slope generation circuit to be a set value. According to the slope generator, the slope of the slope signal can be dynamically adjusted, the deviation of the slope signal caused by process or environmental factors is reduced, and the precision of the slope signal is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of image sensors, and in particular to a ramp generator, an analog-to-digital converter, an image sensor, an electronic device and a vehicle. Background Art

[0002] The ramp generator is one of the core modules of the analog-to-digital converter. Its speed and accuracy are the key factors that determine the performance of the analog-to-digital converter. For an integral ramp generator, its ramp slope can be expressed as g m1 V b / C,g m1 is the transconductance, V b is the current source control voltage, which is related to the charging current, C is the charging capacitor, and the output slope voltage is significantly affected by the charging current and the integral capacitor. In the actual manufacturing process, due to process deviation, it is easy to cause the slope to deviate from the design value, resulting in reduced accuracy. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the first object of the present invention is to provide a ramp generator, which can dynamically adjust the slope of the ramp signal, reduce the deviation of the ramp signal caused by process or environmental factors, and improve the accuracy of the ramp signal.

[0004] A second objective of the present invention is to provide an analog-to-digital converter.

[0005] A third objective of the present invention is to provide an image sensor.

[0006] A fourth objective of the present invention is to provide an electronic device.

[0007] A fifth object of the present invention is to provide a vehicle.

[0008] In order to achieve the above-mentioned purpose, the ramp generator of the first aspect embodiment of the present invention includes: a ramp generating circuit, which is used to generate a ramp signal; a correction circuit, wherein the input end of the correction circuit is connected to the output end of the ramp generating circuit, and the output end of the correction circuit is connected to the ramp signal slope adjustment end of the ramp generating circuit, and is used to generate a ramp adjustment signal to adjust the slope of the ramp signal of each ramp generating cycle of the ramp generating circuit.

[0009] According to the ramp generator of the embodiment of the present invention, a ramp signal of each ramp generating cycle of the ramp generating circuit is obtained through a correction circuit, and a ramp adjustment signal is generated based on the ramp signal to adjust the slope of the ramp signal of each ramp generating cycle of the ramp generating circuit to a set value, thereby avoiding the slope deviation of the ramp from the set value due to manufacturing process deviation or other factors, that is, the slope of the ramp signal is dynamically adjusted through the correction circuit, thereby improving the accuracy of slope generation.

[0010] In some embodiments, the correction circuit includes: a capacitor unit, which is used for sampling, eliminating amplifier offset and integration; a first operational amplifier, a first input terminal of the first operational amplifier is connected to the capacitor unit, a second input terminal of the first operational amplifier is connected to a reference power supply, and an output terminal of the first operational amplifier is connected to a slope signal slope adjustment terminal of the ramp generating circuit, for outputting the ramp adjustment signal; a first switch unit, the first switch unit is connected to the capacitor unit, the output terminal of the first operational amplifier, the output terminal of the ramp generating circuit and a preset power supply, for switching the circuit connection state of the correction circuit.

[0011] In some embodiments, the capacitor unit includes: a first capacitor, a first end of the first capacitor is selectively connected to the output end of the ramp generating circuit, and the first capacitor is used to collect the ramp signal output by the ramp generating circuit.

[0012] In some embodiments, the capacitor unit also includes: a second capacitor, a first end of the second capacitor is connected to the second end of the first capacitor, the second end of the second capacitor is connected to the first input end of the first operational amplifier, and the second capacitor is used to eliminate the offset error of the first operational amplifier.

[0013] In some embodiments, the capacitor unit also includes: a third capacitor, the first end of the third capacitor is selectively connected to the second end of the first capacitor and the second end of the second capacitor, and the second end of the third capacitor is selectively connected to the reference power supply and the output end of the first operational amplifier to serve as an integrating capacitor.

[0014] In some embodiments, each ramp generation cycle in which the ramp generating circuit generates the ramp signal includes a first ramp reset phase, a first ramp hold phase, a first ramp generation phase, a second ramp reset phase, a second ramp hold phase, a second ramp generation phase, and a ramp signal correction phase in sequence, wherein the ramp generation time of the second ramp generation phase is longer than the ramp generation time of the first ramp generation phase.

[0015] In some embodiments, the first switch unit includes: a first switch, a first end of the first switch is connected to the output end of the ramp generating circuit, a second end of the first switch is connected to the first end of the first capacitor, and the first switch is used to close during the ramp signal correction phase.

[0016] In some embodiments, the first switch unit further includes: a second switch, a first end of the second switch being connected to a second end of the first switch and a first end of the first capacitor, a second end of the second switch being connected to a first preset power supply to input a slope termination voltage, and the second switch being configured to be closed in the first slope reset phase, the first slope hold phase, the first slope generation phase, the second slope reset phase, the second slope hold phase, and the second slope generation phase.

[0017] In some embodiments, the first switch unit further includes: a third switch, a first end of the third switch being connected to the second end of the first capacitor and the first end of the second capacitor, a second end of the third switch being connected to a reference power supply to input a reference voltage, and the third switch being configured to be closed in the first slope reset phase, the first slope holding phase, the first slope generation phase, the second slope reset phase, the second slope holding phase, and the second slope generation phase.

[0018] In some embodiments, the first switch unit further includes: a fourth switch, a first end of the fourth switch connected to the second end of the first capacitor and the first end of the third capacitor, a second end of the fourth switch connected to the first end of the third capacitor, and the fourth switch is used to close during the ramp signal correction phase.

[0019] In some embodiments, the first switch unit further includes: a fifth switch, a first end of the fifth switch connected to the second end of the second capacitor and the first input end of the first operational amplifier, a second end of the fifth switch connected to the first end of the third capacitor, and the local switch is used to be closed in the first slope reset stage, the first slope holding stage, the first slope generation stage, the second slope reset stage, the second slope holding stage and the second slope generation stage.

[0020] In some embodiments, the first switch unit further includes: a sixth switch, a first end of the sixth switch connected to the second end of the third capacitor, a second end of the sixth switch connected to the output end of the first operational amplifier, and the sixth switch is used to be closed in the first slope holding stage, the first slope generating stage, the second slope resetting stage, the second slope holding stage, the second slope generating stage and the slope signal correction stage.

[0021] In some embodiments, the first switch unit further includes: a seventh switch, a first end of the seventh switch being connected to the first end of the fifth switch, the first input end of the first operational amplifier, and the second end of the second capacitor, respectively, a second end of the seventh switch being connected to the second end of the sixth switch and the output end of the first operational amplifier, respectively, and the seventh switch being used to close in the first ramp reset stage.

[0022] In some embodiments, the first switch unit further includes: an eighth switch, a first end of the eighth switch being respectively connected to the second end of the third capacitor and the first end of the sixth switch, a second end of the eighth switch being connected to a reference power supply, and the eighth switch being used to close in the first ramp reset stage.

[0023] In some embodiments, the ramp generating circuit includes: a current source for generating a current signal, a first end of the current source being connected to a power supply, and a control end of the current source being connected to an output end of the correction circuit; a second operational amplifier, a first input end of the second operational amplifier being connected to a second end of the current source, a second input end of the second operational amplifier being connected to a reference power supply to input a reference voltage, an output end of the second operational amplifier being connected to a first end of the first switch, and an output end of the second operational amplifier being suitable for outputting a ramp signal; a fourth capacitor, a first end of the fourth capacitor being connected to a first input end of the second operational amplifier, and a second end of the fourth capacitor being selectively connected to an output end of the second operational amplifier and a preset power supply to serve as an integrating capacitor; a second switch unit, the second switch unit being connected to the current source, the second operational amplifier and the fourth capacitor, respectively, for switching the circuit connection state of the ramp generating circuit.

[0024] In some embodiments, the second switch unit includes: a ninth switch, a first end of the ninth switch is connected to the second end of the current source, a second end of the ninth switch is connected to a reference power supply, and is used to be closed in the first slope reset stage, the first slope holding stage, the second slope reset stage, the second slope holding stage and the ramp signal correction stage; a tenth switch, a first end of the tenth switch is connected to the second end of the current source, a second end of the tenth switch is connected to the first input end of the second operational amplifier, and is used to be closed in the first slope generation stage and the second slope generation stage, respectively.

[0025] In some embodiments, the ninth switch and the tenth switch both enter the second ramp reset phase before the ramp signal is reset to the reset voltage.

[0026] In some embodiments, the ninth switch and the tenth switch both start to enter the ramp signal correction phase before the ramp signal recovers to the ramp termination voltage.

[0027] In some embodiments, the second switch unit further includes: an eleventh switch, a first end of the eleventh switch connected to the first input end of the second operational amplifier, a second end of the eleventh switch connected to the output end of the second operational amplifier, and the eleventh switch is used to be closed in the first ramp reset stage and the second ramp reset stage, respectively.

[0028] In some embodiments, the second switch unit further includes: a twelfth switch, a first end of the twelfth switch connected to the second end of the fourth capacitor, a second end of the twelfth switch connected to the output end of the second operational amplifier, and the twelfth switch is used to be closed in the first ramp reset stage and the second ramp reset stage, respectively.

[0029] In some embodiments, the second switch further includes: a thirteenth switch, a first end of the thirteenth switch is connected to the second end of the fourth capacitor, a second end of the thirteenth switch is connected to a preset power supply to input a ramp starting voltage, and the thirteenth switch is used to be closed in the first ramp reset stage and the second ramp reset stage, respectively.

[0030] In order to achieve the above-mentioned purpose, the analog-to-digital converter of the second aspect of the embodiment of the present invention includes: the ramp generator mentioned above; a comparator circuit, the comparator circuit is connected to the ramp generator, the comparator circuit is used to obtain a sampling signal, and compare the ramp signal of the ramp generator with the sampling signal.

[0031] The analog-to-digital converter of the embodiment of the present invention can obtain a more accurate ramp signal by adopting the ramp generator of the above embodiment, thereby improving the accuracy of analog-to-digital signal conversion.

[0032] In some embodiments, the comparator circuit includes: a first comparator; a fifth capacitor, a first end of the fifth capacitor is connected to the first input end of the first comparator, and a second end of the fifth capacitor is suitable for inputting a sampling signal or a ramp signal; a sixth capacitor, a first end of the sixth capacitor is connected to the second input end of the first comparator, and a second end of the sixth capacitor is suitable for inputting a sampling signal; a third switching unit, the third switching unit is respectively connected to the first comparator, the fifth capacitor and the sixth capacitor, and is used to switch the working state of the comparator circuit and control the sampling signal and the ramp signal to be input into the first comparator in a time-sharing manner.

[0033] In some embodiments, the third switch unit includes: a fourteenth switch, a first end of the fourteenth switch is suitable for inputting a sampling signal, and a second end of the fourteenth switch is connected to the second end of the fifth capacitor; a fifteenth switch, a first end of the fifteenth switch is suitable for inputting the sampling signal, and a second end of the fifteenth switch is connected to the second end of the sixth capacitor; the fourteenth switch and the fifteenth switch are both used to close in the reset mode of the comparator circuit and to open in the working mode of the comparator circuit.

[0034] In some embodiments, the third switch unit also includes: a sixteenth switch, a first end of the sixteenth switch is connected to the ramp generator to input the ramp signal, and a second end of the sixteenth switch is connected to the second end of the fifth capacitor; a seventeenth switch, a first end of the seventeenth switch is suitable for inputting the sampling signal, and a second end of the seventeenth switch is connected to the second end of the sixth capacitor; the sixteenth switch and the seventeenth switch are both used to open in the reset mode of the comparator circuit and to close in the working mode of the comparator circuit.

[0035] In some embodiments, the third switch unit also includes: an eighteenth switch, a first end of the eighteenth switch is connected to the first input end of the first comparator, and a second end of the eighteenth switch is connected to the first power supply end of the first comparator; a nineteenth switch, a first end of the nineteenth switch is connected to the second input end of the first comparator, and a second end of the nineteenth switch is connected to the second power supply end of the first comparator; the eighteenth switch and the nineteenth switch are both used to close in the reset mode of the comparator circuit and to open in the working mode of the comparator circuit.

[0036] In some embodiments, when the ramp signal enters a first ramp holding phase from a first reset phase, the comparator circuit switches from the working mode to a reset mode.

[0037] In some embodiments, when the ramp signal enters the first ramp generation phase, the comparator circuit switches from the reset mode to the working mode.

[0038] In some embodiments, when the ramp signal enters the second reset phase from the first ramp generation phase, the comparator circuit switches from the operating mode to the reset mode; when the ramp signal enters the second hold phase from the second reset phase, the comparator circuit switches from the reset mode to the operating mode.

[0039] In some embodiments, the comparator circuit also includes: a second comparator, a first input terminal of the second comparator is connected to the first power supply terminal of the first comparator, and a second input terminal of the second comparator is connected to the second power supply terminal of the first comparator; a twentieth switch, a first end of the twentieth switch is connected to the second input terminal of the second comparator, and a second end of the twentieth switch is connected to the output terminal of the second comparator.

[0040] In some embodiments, the analog-to-digital converter further includes: a counter, which is connected to the output end of the second comparator and is used to generate a quantized value of the sampling signal according to a comparison result of the comparator circuit.

[0041] In order to achieve the above-mentioned purpose, an image sensor according to an embodiment of the third aspect of the present invention comprises a pixel array and the analog-to-digital converter, wherein the analog-to-digital converter is used to quantize and convert pixel signals of the pixel array.

[0042] The image sensor according to the embodiment of the present invention uses the analog-to-digital converter of the above embodiment to ensure that during the slope generation process, when the manufacturing process, power supply voltage and ambient temperature change, the slope of the ramp voltage remains unchanged, thereby reducing system offset, improving slope accuracy and improving imaging quality.

[0043] In order to achieve the above-mentioned objective, a fourth aspect of the present invention further provides an electronic device, which includes the image sensor of the above embodiment.

[0044] The electronic device according to the embodiment of the present invention can improve the imaging quality and enhance the imaging performance of the device by adopting the image sensor of the above embodiment.

[0045] In order to achieve the above-mentioned objective, a fifth aspect of the present invention further provides a vehicle, which includes the image sensor of the above embodiment.

[0046] The vehicle according to the embodiment of the present invention can improve the imaging quality by adopting the image sensor of the above embodiment, thereby providing more accurate information for the image-based control strategy of the vehicle.

[0047] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0049] Figure 1 is a block diagram of a ramp generator according to one embodiment of the present invention;

[0050] Figure 2 is a circuit diagram of a ramp generator according to one embodiment of the present invention;

[0051] Figure 3 is a control timing diagram of each switch in a ramp generator according to an embodiment of the present invention;

[0052] Figure 4 is a circuit topology diagram of a ramp reset phase of a ramp generator according to an embodiment of the present invention;

[0053] Figure 5 is a circuit topology diagram of a ramp holding phase of a ramp generator according to an embodiment of the present invention;

[0054] Figure 6 is a circuit topology diagram of a ramp generating stage of a ramp generator according to an embodiment of the present invention;

[0055] Figure 7 is a circuit topology diagram of a slope correction stage of a ramp generator according to an embodiment of the present invention;

[0056] Figure 8 is a block diagram of an analog-to-digital converter according to an embodiment of the present invention;

[0057] Fig. 9 is a circuit diagram of a comparator circuit according to an embodiment of the present invention;

[0058] Fig.10 is a circuit topology diagram of a reset mode of a comparator circuit according to an embodiment of the present invention;

[0059] Fig.11 is a circuit topology diagram of an operating mode of a comparator circuit according to an embodiment of the present invention;

[0060] Fig.12 is a control timing diagram of each switch in a comparator circuit according to an embodiment of the present invention;

[0061] Fig.13 is a block diagram of an image sensor according to an embodiment of the present invention;

[0062] Fig.14 is a block diagram of an electronic device according to an embodiment of the present invention;

[0063] Fig.15 is a block diagram of a vehicle according to one embodiment of the present invention.

[0064] Reference numerals:

[0065] Electronic device 1000, vehicle 2000;

[0066] Image sensor 1;

[0067] Analog-to-digital converter 100, pixel array 200;

[0068] Ramp generator 10, comparator circuit 20;

[0069] A slope generating circuit 11, a correction circuit 12;

[0070] A first switch unit 122, a second switch unit 111, a third switch unit 22, a first operational amplifier A2, a first comparator 21, a fifth capacitor C5, a sixth capacitor C6, a current source M1, a second operational amplifier A1, a fourth capacitor C4, and a capacitor unit 121;

[0071] A first capacitor C1, a second capacitor C2, a third capacitor C3, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, a ninth switch S9, a tenth switch S10, an eleventh switch S11, a twelfth switch S12, a thirteenth switch S13, a fourteenth switch S14, a fifteenth switch S15, a sixteenth switch S16, a seventeenth switch S17, an eighteenth switch S18, a nineteenth switch S19, a second comparator 23, and a twentieth switch S20. DETAILED DESCRIPTION

[0072] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0073] The ramp generator according to the first embodiment of the present invention will be described below with reference to the accompanying drawings.

[0074] Figure 1 is a block diagram of a ramp generator according to one embodiment of the present invention. Figure 1 As shown, the ramp generator 10 includes a ramp generating circuit 11 and a correction circuit 12 .

[0075] The ramp generating circuit 11 is used to generate a ramp signal. For example, in some embodiments, the ramp generating circuit may adopt an integral ramp generator structure or other applicable circuit structures.

[0076] The input end of the correction circuit 12 is connected to the output end of the ramp generating circuit 11, and the output end of the correction circuit 12 is connected to the ramp signal slope adjustment end of the ramp generating circuit 11, for generating a ramp adjustment signal to adjust the slope of the ramp signal of each ramp generating cycle of the ramp generating circuit 11 to a set value.

[0077] In the embodiment, the ramp signal slope adjustment terminal can be understood as a control terminal that affects the slope of the ramp signal of the ramp generating circuit 11. For example, for an integral ramp generator, the slope of its ramp signal is related to the charging current and the integral capacitor. The control terminal that controls the charging current can be used as the ramp signal slope adjustment terminal of the ramp generating circuit 11. Alternatively, a corresponding control terminal can be selected for the ramp generating circuit 11 of other circuit structures.

[0078] In an embodiment, the set value may be a design value of the slope of a ramp signal of a ramp generator, or a set value required by other device design. In an actual manufacturing process, the set value of the ramp generator remains consistent.

[0079] Specifically, in each cycle of ramp generation, the correction circuit 12 obtains the ramp signal generated by the ramp generating circuit 11, and generates a ramp adjustment signal based on the ramp signal. The ramp adjustment signal can be a deviation between the ramp signal and a set value, such as a design value, or other numerical values. The ramp adjustment signal is then fed back to the ramp signal slope adjustment end of the ramp generating circuit 11, so that the ramp generating circuit 11 can adjust the slope of its slope signal so that the slope is close to the set value, thereby ensuring that the slope of the ramp signal in each ramp generating cycle can be consistent and close to the set value, thereby improving the accuracy of the ramp generator.

[0080] According to the ramp generator 10 of the embodiment of the present invention, the ramp signal of each ramp generating cycle of the ramp generating circuit is obtained through the correction circuit 12, and a ramp adjustment signal is generated based on the ramp signal, so that the slope of the ramp signal of each ramp generating cycle of the ramp generating circuit 11 is a set value, thereby avoiding the slope deviation of the ramp from the set value due to manufacturing process deviation or other factors. The slope of the ramp signal is dynamically adjusted by the correction circuit 12 to ensure that the slope of the slope signal in each slope cycle is the set value, thereby improving the accuracy of slope generation.

[0081] The correction circuit 12 and the slope generating circuit 11 of the embodiment of the present invention are described below respectively.

[0082] Figure 2 is a circuit diagram of a ramp generator according to one embodiment of the present invention.

[0083] like Figure 2 As shown, the correction circuit 12 includes a capacitor unit 121 , a first operational amplifier A2 and a first switch unit 122 .

[0084] The capacitor unit 121 is used for sampling, eliminating amplifier offset and integration, and realizing different functions of the correction circuit 12. In the embodiment, the sampling, eliminating amplifier offset and integration can be realized by a single capacitor or by a combination of multiple capacitors, which is not specifically limited here.

[0085] The first input terminal of the first operational amplifier A2 is connected to the capacitor unit 121, the second input terminal of the first operational amplifier A2 is connected to the reference power supply to input the reference voltage Vref, and the output terminal of the first operational amplifier A2 is connected to the ramp signal slope adjustment terminal of the ramp generating circuit 11, and is used to output a ramp adjustment signal so that the slope of the ramp signal is a set value, thereby avoiding deviation and improving accuracy.

[0086] The first switch unit 122 is connected to the capacitor unit 121, the output end of the first operational amplifier A2, the output end of the ramp generating circuit 11 and a preset power source for switching the circuit connection state of the correction circuit 12 to cooperate with the ramp generating process.

[0087] From the above, the ramp generator 10 of the embodiment of the present invention generates a ramp adjustment signal based on the capacitor unit 121, the first operational amplifier A2 and the first switch unit 122 through the correction circuit 12, so that the slope of the ramp signal in each cycle is a set value, thereby ensuring that during the ramp generation process, when the manufacturing process, power supply voltage and ambient temperature change, the slope of the ramp signal can remain unchanged, thereby improving the accuracy.

[0088] Further, in an embodiment, Figure 2 As shown, the capacitor unit 121 includes a first capacitor C1, a first end of the first capacitor C1 is selectively connected to the output end of the ramp generating circuit 11, and the first capacitor C1 is used to collect the ramp signal output by the ramp generating circuit 11, that is, to achieve the sampling effect of the ramp signal. Wherein, "selectively" connected can be understood as, in some circuit connection states of the correction circuit 12, the first capacitor C1 can be connected to the output end of the ramp generating circuit 11, and in other circuit connection states, the first capacitor C1 is not connected to the output end of the ramp generating circuit 11.

[0089] like Figure 2 As shown, the capacitor unit 121 also includes a second capacitor C2, a first end of the second capacitor C2 is connected to the second end of the first capacitor C1, and a second end of the second capacitor C2 is connected to the first input end of the first operational amplifier A2. The second capacitor C2 is used to eliminate the offset error of the first operational amplifier A2 and improve the accuracy.

[0090] like Figure 2 As shown, the capacitor unit 121 also includes a third capacitor C3, the first end of the third capacitor C3 is selectively connected to the second end of the first capacitor C1 and the second end of the second capacitor C2, the second end of the third capacitor C3 is selectively connected to the reference power supply and the output end of the first operational amplifier A2, and the third capacitor C3 can be used as an integrating capacitor.

[0091] In some embodiments of the present invention, each ramp generation cycle in which the ramp generation circuit 11 generates a ramp signal can be divided into four stages: reset, hold, ramp generation, and correction according to the change of the ramp voltage. Specifically, in the embodiment, this ramp generation cycle can include seven stages, and the seven stages include a first ramp reset stage, a first ramp hold stage, a first ramp generation stage, a second ramp reset stage, a second ramp hold stage, a second ramp generation stage, and a ramp signal correction stage, wherein the ramp generation time of the second ramp generation stage is longer than the ramp generation time of the first ramp generation stage.

[0092] The last stage of each ramp generation cycle is the voltage correction stage and the ramp signal correction stage. The correction circuit 12 samples the ramp voltage and compares it with the set ramp termination voltage V L This regulation process continues until the ramp voltage V ramp Equal to V L That is, the slope correction is considered to be completed to generate a ramp signal with a fixed slope.

[0093] like Figure 2 As shown, the first switch unit 122 includes a first switch S1, a first end of the first switch S1 is connected to the output end of the ramp generating circuit 11, a second end of the first switch S1 is connected to the first end of the first capacitor C1, and the first switch S1 is used to close in the ramp signal correction stage, and is in an open state in other stages. That is, the first switch S1 is used to control the connection state of the first capacitor C1 and the ramp generating circuit 11.

[0094] The first switch unit 122 further includes a second switch S2, a first end of the second switch S2 is connected to the second end of the first switch S1 and the first end of the first capacitor C1, and a second end of the second switch S2 is connected to the first preset power supply to input the ramp termination voltage V L The second switch S2 is used to be closed in the first slope reset stage, the first slope holding stage, the first slope generating stage, the second slope reset stage, the second slope holding stage and the second slope generating stage, and is in an open state in other stages.

[0095] The first switch unit 122 also includes a third switch S3, a first end of the third switch S3 is connected to the second end of the first capacitor C1 and the first end of the second capacitor C2, a second end of the third switch S3 is connected to a reference power supply to input a reference voltage Vref, and the third switch S3 is used to be closed in the first slope reset stage, the first slope holding stage, the first slope generating stage, the second slope reset stage, the second slope holding stage and the second slope generating stage, and is in an open state in other stages.

[0096] The first switch unit 122 also includes a fourth switch S4, a first end of the fourth switch S4 is connected to the second end of the first capacitor C1 and the first end of the third capacitor C3, a second end of the fourth switch S4 is connected to the first end of the third capacitor C3, and the fourth switch S4 is used to be closed in the ramp signal correction stage and to be in an open state in other stages.

[0097] The first switch unit 122 also includes a fifth switch S5, a first end of the fifth switch S5 is connected to the second end of the second capacitor C2 and the first input end of the first operational amplifier A2, a second end of the fifth switch S5 is connected to the first end of the third capacitor C3, and the fifth switch S5 is used to be closed in the first slope reset stage, the first slope holding stage, the first slope generating stage, the second slope reset stage, the second slope holding stage, and the second slope generating stage, and is in an open state in other stages.

[0098] The first switch unit 122 also includes a sixth switch S6, a first end of the sixth switch S6 is connected to the second end of the third capacitor C3, a second end of the sixth switch S6 is connected to the output end of the first operational amplifier A2, and the sixth switch S6 is used to be closed in the first slope holding stage, the first slope generating stage, the second slope resetting stage, the second slope holding stage, the second slope generating stage and the slope signal correction stage, and is in an open state in other stages.

[0099] The first switch unit 122 also includes a seventh switch S7, a first end of the seventh switch S7 is respectively connected to the first end of the fifth switch S5, the first input end of the first operational amplifier A2, and the second end of the second capacitor C2, a second end of the seventh switch S7 is respectively connected to the second end of the sixth switch S6 and the output end of the first operational amplifier A2, and the seventh switch S7 is used to be closed in the first slope reset stage and to be in an open state in other stages.

[0100] The first switch unit 122 further includes an eighth switch S8, a first end of the eighth switch S8 is respectively connected to the second end of the third capacitor C3 and the first end of the sixth switch S6, a second end of the eighth switch S8 is connected to a reference power supply to input a reference voltage Vref, and the eighth switch S8 is used to close in the first slope reset stage and be in an open state in other stages.

[0101] As described above, when the switches of the first switch unit 122 are in different states, the circuit topology of the correction circuit 12 also changes, thereby adapting to the various slope generation stages of the slope generation circuit 11, and ultimately achieving the purpose of dynamically adjusting the slope of the ramp signal and improving the accuracy.

[0102] like Figure 2 As shown, the ramp generating circuit 11 includes a current source M1 , a second operational amplifier A1 , a fourth capacitor C4 and a second switch unit 111 .

[0103] The first end of the current source M1 is connected to the power supply VDD, and the control end of the current source M1 is connected to the output end of the correction circuit 12 to generate a current signal. Figure 2 As shown, the control end of the current source M1 is connected to the output end of the first operational amplifier A2 to adjust the charging current of the current source M1 through the slope adjustment signal, i.e., the voltage Vfb, so as to adjust the slope of the ramp signal, so that the slope of the ramp signal is maintained at the set value, thereby improving the accuracy.

[0104] Among them, the first input terminal of the second operational amplifier A1 is connected to the second terminal of the current source M1, the second input terminal of the second operational amplifier A1 is connected to the reference power supply to input the reference voltage Vref, the output terminal of the second operational amplifier A1 is connected to the first terminal of the first switch S1, and the output terminal of the second operational amplifier A1 is suitable for outputting a ramp signal.

[0105] The first end of the fourth capacitor C4 is connected to the first input end of the second operational amplifier A1, and the second end of the fourth capacitor C4 is selectively connected to the output end of the second operational amplifier A1, the preset power supply V H connected as an integrating capacitor, where the voltage V H is the ramp start voltage.

[0106] The second switch unit 111 is connected to the current source M1 , the second operational amplifier A1 , and the fourth capacitor C4 , respectively, and is used to switch the circuit connection state of the ramp generating circuit 11 .

[0107] As described above, the ramp generating circuit 11 of the embodiment of the present invention connects the control end of the current source M1 with the output end of the correction circuit 12, and adjusts the charging current of the current source M1 through the slope adjustment signal of the correction circuit 12, so as to achieve the purpose of influencing the slope of the ramp, so that the slope of the ramp signal in each ramp generating cycle can be a set value, eliminating the inconsistent slope caused by the influence of process deviation or ambient temperature, etc., and improving the accuracy.

[0108] The circuit topology of the ramp generating circuit 11 will also change when the state of the switch in the second switch unit 11 is different, and thus, it can be applied to various stages within the ramp generating cycle.

[0109] like Figure 2 As shown, the second switch unit 111 includes a ninth switch S9 and a tenth switch S10.

[0110] Among them, the first end of the ninth switch S9 is connected to the second end of the current source M1, and the second end of the ninth switch S9 is connected to the reference power supply to input the reference voltage Vref, and is used to be closed in the first slope reset stage, the first slope holding stage, the second slope reset stage, the second slope holding stage and the slope signal correction stage, and is in an open state in other stages.

[0111] The first end of the tenth switch S10 is connected to the second end of the current source M1, and the second end of the tenth switch S10 is connected to the first input end of the second operational amplifier A1, and is used to be closed in the first slope generation stage and the second slope generation stage respectively, and is in an open state in other stages.

[0112] In the embodiment, the ninth switch S9 and the tenth switch S10 both start to enter the second ramp reset phase before the ramp signal is reset to the reset voltage, thereby avoiding errors caused by channel charge injection and clock feedthrough.

[0113] In the embodiment, the ninth switch S9 and the tenth switch S10 both start to enter the ramp signal correction phase before the ramp signal recovers to the ramp termination voltage, thereby avoiding errors caused by channel charge injection and clock feedthrough.

[0114] like Figure 2 As shown, the second switch unit 111 further includes an eleventh switch S11, a twelfth switch S12 and a thirteenth switch S13.

[0115] A first end of the eleventh switch S11 is connected to a first input end of the second operational amplifier A1, a second end of the eleventh switch S11 is connected to an output end of the second operational amplifier A1, and the eleventh switch S11 is used to be closed in the first slope reset stage and the second slope reset stage, respectively, and is in an open state in other stages.

[0116] The first end of the twelfth switch S12 is connected to the second end of the fourth capacitor C4, the second end of the twelfth switch S12 is connected to the output end of the second operational amplifier A1, and the twelfth switch S12 is used to be closed in the first slope reset stage and the second slope reset stage respectively, and is in an open state in other stages.

[0117] The first end of the thirteenth switch S13 is connected to the second end of the fourth capacitor C4, and the second end of the thirteenth switch S13 is connected to the preset power supply to input the ramp start voltage V L The thirteenth switch S13 is used to be closed in the first slope reset stage and the second slope reset stage respectively, and is in an open state in other stages.

[0118] As described above, when the switches of the first switch unit 122 in the correction circuit 12 are in different states, the circuit topology of the correction circuit 12 is different, and when the switches of the second switch unit 111 of the slope generating circuit 11 are in different states, the circuit topology of the slope generating circuit 11 also changes, thereby adapting to each slope generating stage of the slope generating cycle.

[0119] Figure 3 FIG. 4 is a control timing diagram of each switch in a ramp generator according to an embodiment of the present invention.

[0120] like Figure 3 As shown, where V ramp is the ramp voltage output by the ramp generator 10. ramp The change of is affected by the state of each switch. Different switch states cause the topology of the circuit to change, thereby changing the output voltage V ramp The amplitude of each ramp generation cycle includes the first ramp reset stage, the first ramp hold stage, the first ramp generation stage, i.e., the short ramp stage, the second ramp reset stage, the second ramp hold stage, the second ramp generation stage, i.e., the long ramp stage, and the ramp signal correction stage. The appropriate timing sequence is adopted to realize the change of the ramp signal in the entire ramp generation cycle.

[0121] Specifically, in different switching states of the correction circuit 12 and the ramp generating circuit 11 , the ramp generator 10 has different circuit topologies at different stages.

[0122] For example, Figure 4 : is a circuit topology of the reset phase of the ramp generator according to an embodiment of the present invention. In the first ramp reset phase or the second ramp reset phase, the ninth switch S9, the eleventh switch S11 and the thirteenth switch S13 of the ramp generating circuit 11 are closed, and the tenth switch S10 and the twelfth switch S12 are opened; the second switch S2, the third switch S3, the fifth switch S5, the seventh switch S7 and the eighth switch S8 of the correction circuit 12 are closed, and the first switch S1, the fourth switch S4 and the sixth switch S6 are opened. At this time, the equivalent schematic diagram of the ramp generator is as follows: Figure 4 The ramp generation circuit 11 and the correction circuit 12 can both be equivalent to a unit gain negative feedback buffer.

[0123] Taking the ramp generating circuit 11 as an example, assuming that the gain of the second operational amplifier A1 is A, we can obtain:

[0124] (V ref -V - )A=V rampⅠ ;

[0125] Depend on Figure 4 From the circuit diagram, we can see that V - =VrampⅠ , so when A is large, V can be obtained ref =V rampⅠ At this time, the charge on the integrating capacitor, i.e., the fourth capacitor C4, can be expressed as:

[0126] Q C4Ⅰ =(B rampⅠ -V H )C 4 =(V ref -V H )C 4 ;

[0127] Similarly, the feedback regulation voltage in the correction circuit 12 is the ramp regulation signal V fb,reset =V ref =V rampⅠ , the charge on the third capacitor C3 can be expressed as:

[0128] Q C3 =(V fb,reset -V ref )C 3 =V ref -V ref )C 3 =0;

[0129] In the correction circuit, the charge of the sampling capacitor, i.e., the first capacitor C1, can be expressed as:

[0130] Q C1 =(V L -V ref )C 1 ;

[0131] The offset elimination capacitor, i.e., the second capacitor C2, is used to eliminate the equivalent offset voltage V inside the operational amplifier of the correction circuit. OS , the charge on it can be expressed as:

[0132] Q C2 =(V ref -V fb,reset +V OS )C 2 .

[0133] In the slope holding stage, which includes the first slope holding stage and the second slope holding stage, the ninth switch S9 and the twelfth switch S12 of the slope generating circuit 11 are closed, and the tenth switch S10, the eleventh switch S11 and the thirteenth switch S13 are opened; the second switch S2, the third switch S3, the fifth switch S5 and the sixth switch S6 of the correction circuit 12 are closed, and the first switch S1, the fourth switch S4, the seventh switch S7 and the eighth switch S8 are opened, and the integral capacitors, i.e., the fourth capacitor C4 and the third capacitor C3, are respectively connected across the two ends of the corresponding operational amplifier. The equivalent schematic diagram of the slope generator 10 is shown in FIG. Figure 5 shown.

[0134] At this time, the charge on the integrating capacitor, i.e., the fourth capacitor C4, can be expressed as:

[0135] Q C4 =(V ref -V rampⅡ )C 4 ;

[0136] According to the law of charge conservation, the output voltage v in the holding phase can be obtained rampⅡ V H , i.e. the ramp start voltage. Similarly, the feedback regulation voltage at this time, i.e. the ramp regulation signal V, can be obtained according to the charge conservation of the third capacitor C3. fb,hold =V ref =V fb,reset .

[0137] In the ramp generation stage, including the first ramp generation stage and the second ramp generation stage, the tenth switch S10 and the twelfth switch S12 of the ramp generation circuit 11 are closed, and the ninth switch S1, the eleventh switch S3 and the thirteenth switch S4 are opened. The switch state in the correction circuit 12 remains unchanged in the first ramp holding stage. At this time, the equivalent schematic diagram of the ramp generator 10 is as follows: Figure 6 shown.

[0138] In the ramp generation phase, the current source M1 begins to pass through the tenth switch S10 at the integration time t ramp The integral capacitor, i.e., the fourth capacitor C4, is charged, and the left plate of the integral capacitor C4 loses electrons. Due to the law of charge conservation, the voltage on the right plate of the integral capacitor C4 decreases, generating a ramp voltage V rampⅢ , this stage outputs the ramp voltage V rampⅢ It is expressed as:

[0139]

[0140] At this time, the charge of the sampling capacitor, i.e., the first capacitor C1, can be expressed as:

[0141] Q C1 =(V L -V ref)C 1 ;

[0142] The charge on the third capacitor C3 can be expressed as:

[0143] Q C3 =(V ref -V fb,gen )C 3 .

[0144] As described above, the difference between the first slope generation stage and the second slope generation stage is that the slope generation time of the second slope generation stage is longer than that of the first slope generation stage, that is, the state of the slope generation stage can be maintained longer by controlling each switch.

[0145] In the ramp signal correction stage, the ninth switch S9 and the twelfth switch S12 of the ramp generating circuit 11 are closed, and the tenth switch S10, the eleventh switch S11 and the thirteenth switch S13 are opened; the first switch S1, the fourth switch S4 and the sixth switch S6 in the correction circuit 12 are closed, and the remaining switches are opened. The equivalent schematic diagram of the ramp generator 10 is shown in FIG. Figure 7 shown.

[0146] At this time, the voltage signal sampled on the left plate of the sampling capacitor, i.e. the first capacitor C1, is V L Switch to V rampⅢ , the charge on the capacitor can be expressed as:

[0147] Q C1 =(V rampⅢ -V ref )C 1 ;

[0148] The charge on the second capacitor, offset cancellation capacitor C2, is:

[0149] Q c2 =(V ref -V - +V OS )C 2 ;

[0150] According to the charge conservation principle in the reset and correction phases, the charge on capacitor C2 in the correction phase should be equal to the charge on C2 in the reset phase. _ =V fb,reset =V ref It can be seen that the offset voltage of the correction circuit has been eliminated after the offset elimination capacitor C2.

[0151] The charge on the third capacitor C3 can be expressed as:

[0152] Q C3 =(Vref -V fb,correct )C 3 ;

[0153] According to the charge conservation on the first capacitor C1 and the third capacitor C3, we can get:

[0154]

[0155] During the slope correction phase, the feedback voltage V generated by the correction circuit fb,correct As the gate voltage of the current source M1 is proportional to the coefficient g m1 Control current I D1 The slope of the ramp signal in the ramp generation phase of the next working process is adjusted according to the change in the ramp signal.

[0156] I D1 =g m1 V fb,correct ;

[0157] After the calibration is completed, the ramp generating circuit 11 is reset again, and the calibration circuit 12 is reset only once during the entire calibration operation, and the ramp output voltage is pulled up to the starting voltage V H , then at time t ramp After the ramp is generated, the correction circuit 11 samples the ramp voltage again and compares it with the set ramp final value voltage V L In comparison, this regulation process continues until V ramp Equal to V L That is, the slope correction is considered to be completed to generate an output slope with a fixed slope. This structure effectively avoids the slope deviation caused by changes in charging current or integration capacitance.

[0158] In summary, the slope generator 10 of the embodiment of the present invention is added with a correction circuit 12, which generates a suitable slope adjustment signal, i.e., a feedback adjustment voltage V through the cooperation of various switches. fb , controls the current source M1 in the ramp generating circuit 11, and the gate voltage of the current source M1 is affected by the feedback regulating voltage V output in the previous working process. fb Control to generate appropriate charging current, ensuring that the slope of the ramp voltage is constant when the manufacturing process, power supply voltage and ambient temperature change during the ramp generation process. It can be adjusted automatically, thereby improving the accuracy of the ramp generating circuit 11.

[0159] Based on the ramp generator of the above embodiment, the analog-to-digital converter according to the second embodiment of the present invention is described below with reference to the accompanying drawings.

[0160] Figure 8 is a block diagram of an analog-to-digital converter according to an embodiment of the present invention, such as Figure 8As shown, the analog-to-digital converter 100 of the embodiment of the present invention includes the ramp generator 10 and the comparator circuit 20 of the above embodiment.

[0161] The circuit structure of the ramp generator 10 can refer to the description of the above embodiment, and will not be repeated here. The ramp generator 10 of the embodiment of the present invention is provided with a ramp generating circuit 11 and a correction circuit 12.

[0162] The comparator circuit 20 is connected to the ramp generator 10. The comparator circuit 20 is used to obtain a sampling signal. The sampling signal can be a pixel signal of a pixel array or other sampling signals such as temperature. Figure 8 As shown in the figure, the pixel signal V pixel For example, the comparator circuit 20 is used to compare the ramp signal of the ramp generator 10 with the sampling signal.

[0163] The analog-to-digital converter 100 of the embodiment of the present invention can obtain a more accurate ramp signal and improve the accuracy of analog-to-digital signal conversion by adopting the ramp generator 10 of the above embodiment.

[0164] Furthermore, if Fig. 9 As shown, the comparator circuit 20 includes a first comparator 21 , a fifth capacitor C5 , a sixth capacitor C6 and a third switch unit 22 .

[0165] Among them, the first end of the fifth capacitor C5 is connected to the first input end of the first comparator 21, and the second end of the fifth capacitor C5 is suitable for inputting a sampling signal or a ramp signal, wherein the sampling signal may include but is not limited to a pixel signal and a temperature signal; the first end of the sixth capacitor C6 is connected to the second input end of the first comparator 21, and the second end of the sixth capacitor C6 is suitable for inputting a sampling signal; the third switch unit 22 is respectively connected to the first comparator 21, the fifth capacitor C5 and the sixth capacitor C6, and is used to switch the working state of the comparator circuit 20 and control the sampling signal and the ramp signal to be input into the first comparator 21 in a time-sharing manner.

[0166] In an embodiment, the third switch unit 22 includes a plurality of switches to switch the working state of the comparator circuit 20 and to realize time-sharing control of the sampling signal and the ramp signal.

[0167] like Fig. 9 As shown, the third switch unit 22 includes a fourteenth switch S14 and a fifteenth switch S15.

[0168] The first end of the fourteenth switch S14 is suitable for inputting a sampling signal, and the second end of the fourteenth switch S14 is connected to the second end of the fifth capacitor C5; the first end of the fifteenth switch S15 is suitable for inputting a sampling signal, and the second end of the fifteenth switch S15 is connected to the second end of the sixth capacitor C6.

[0169] Fig.10 is a circuit diagram of a comparator circuit in a reset mode according to an embodiment of the present invention, Fig.11 FIG. 4 is a circuit diagram of a comparator circuit in working mode according to an embodiment of the present invention.

[0170] like Fig.10 and Fig.11 As shown, the fourteenth switch S14 and the fifteenth switch S15 are both used to be closed in the reset mode of the comparator circuit 20 and to be opened in the working mode of the comparator circuit 20 .

[0171] like Fig. 9 As shown, the third switch unit 22 further includes a sixteenth switch S16 and a seventeenth switch S17.

[0172] Among them, the first end of the sixteenth switch S16 is connected to the ramp generator 10 to input the ramp signal, and the second end of the sixteenth switch S16 is connected to the second end of the fifth capacitor C5; the first end of the seventeenth switch S17 is suitable for inputting the sampling signal, and the second end of the seventeenth switch S17 is connected to the second end of the sixth capacitor C6.

[0173] like Fig.10 and Fig.11 As shown, the sixteenth switch S16 and the seventeenth switch S17 are both used to be opened in the reset mode of the comparator circuit 20 and closed in the working mode of the comparator circuit 20 .

[0174] like Fig. 9 As shown, the third switch unit 22 further includes an eighteenth switch S18 and a nineteenth switch S19.

[0175] Among them, the first end of the eighteenth switch S18 is connected to the first input end of the first comparator 21, and the second end of the eighteenth switch S18 is connected to the first power supply end of the first comparator 21, such as V+; the first end of the nineteenth switch S19 is connected to the second input end of the first comparator 21, and the second end of the nineteenth switch S19 is connected to the second power supply end of the first comparator 21, such as ground or V-.

[0176] like Fig.10 and Fig.11 As shown, the eighteenth switch S18 and the nineteenth switch S19 are both used to close in the reset mode of the comparator circuit 20 and to open in the working mode of the comparator circuit 20. That is, the eighteenth switch S18 and the nineteenth switch S19 are used to realize the automatic reset of the first comparator 21. In the automatic zeroing stage, the capacitors at the input end of the comparator, i.e., the two plates of the fifth capacitor C5 and the sixth capacitor C6, respectively sample the pixel voltage signal V pixel and reset level signal for the comparator.

[0177] As described above, the comparator circuit 20 includes two modes: a reset mode and an operating mode.

[0178] Among them, in reset mode, such as Fig.10 As shown, the sixteenth switch S16 and the seventeenth switch S17 are opened, the fourteenth switch S14 and the fifteenth switch S15 are closed, and the left plates of the sampling capacitors, i.e., the fifth capacitor C5 and the sixth capacitor C6, obtain the sampling signal, such as the sampling pixel signal V pixel ; The eighteenth switch S18 and the nineteenth switch S19 are closed, and the right plates of the fifth capacitor C5 and the sixth capacitor C6 sample the comparator output voltage V out At this time, the ramp voltage signal V ramp In the hold state, the comparator circuit 20 is reset.

[0179] Among them, in working mode, such as Fig.11 As shown, the sixteenth switch S16 and the seventeenth switch S17 are closed, the fourteenth switch S14 and the fifteenth switch S15 are opened, and the ramp signal V ramp The pixel signal V pixel is input to the second input terminal of the first comparator 21, for example, the inverting input terminal. pixel With the ramp signal V ramp When overlapping (ie, the voltages at the two input terminals of the first comparator 21 are equal), the comparator is flipped, and the pixel signal conversion and quantization work is completed.

[0180] Further, in the embodiment of the present invention, the working process of the comparator circuit 20 corresponds to the ramp generator 10, and the timing diagram of the comparator circuit is as follows: Fig.12 shown.

[0181] Among them, the sampled pixel signal V pixel For example, the ramp signal V ramp Generated by the ramp generator 10 of the above embodiment, the pixel signal V pixel The light signal collected by the photodiode is converted by the pixel unit. The control signal PH1 simultaneously controls the conduction and disconnection of the sixteenth switch S16 and the seventeenth switch S17. The fourteenth switch S14 and the fifteenth switch S15 are controlled by the same control signal PH2. The control signals PH1 and PH2 cooperate with each other to realize the pixel signal V pixel and the ramp signal V ramp The eighteenth switch S18 and the nineteenth switch S19 are controlled by the control signal PH2E, and the output signal from the output terminal of the first comparator 21 is collected as a reset signal.

[0182] like Fig.12As shown, when the ramp signal enters the first ramp holding stage from the first reset stage, the comparator circuit 20 switches from the working mode to the reset mode.

[0183] Specifically, when the ramp signal V ramp When entering the hold phase from the reset phase, the ramp signal V ramp From low level to high level, the comparator circuit 20 switches from working mode to reset mode. At this time, the control signals PH2 and PH2E change from low level to high level, and the left plates of the sampling capacitors C5 and C6 sample the pixel signal V pixel , the right plates of the fifth capacitor C5 and the sixth capacitor C6 sample the reset signal, and the positive input terminal and the negative input terminal of the first comparator 21 are reset to a fixed voltage value (common mode voltage).

[0184] like Fig.12 As shown, when the ramp signal enters the first ramp generation phase, the comparator circuit 20 switches from the reset mode to the working mode.

[0185] Specifically, when the ramp voltage V ramp When it starts to decline, the signal PH2E changes from high level to low level, controlling the eighteenth switch S18 and the nineteenth switch S19 to be disconnected; the signal PH2 changes from high level to low level, controlling the fourteenth switch S14 and the fifteenth switch S15 to be disconnected; the signal PH1 changes from low level to high level, controlling the sixteenth switch S16 and the seventeenth switch S17 to be turned on, and the left plate of the sampling capacitor C5 collects the ramp signal V ramp At this time, the topology of the comparator circuit 20 is in the working mode, and the voltage at the non-inverting input terminal of the first comparator 21 changes with the ramp signal V ramp When the ramp signal voltage V ramp The pixel signal voltage V pixel When they are equal, the comparator output voltage changes from high potential to low potential, and the pixel voltage signal conversion quantization is completed.

[0186] Similarly, when the ramp signal enters the second reset phase from the first ramp generation phase, the comparator circuit switches from the working mode to the reset mode; when the ramp signal enters the second holding phase from the second reset phase, the comparator circuit switches from the reset mode to the working mode.

[0187] In some embodiments, Fig. 9 As shown, the comparator circuit 20 further includes a second comparator 23 and a twentieth switch S20.

[0188] Among them, the first input end of the second comparator 23 is connected to the first power supply end of the first comparator 21, and the second input end of the second comparator 22 is connected to the second power supply end of the first comparator 21; the first end of the twentieth switch S20 is connected to the second input end of the second comparator 23, and the second end of the twentieth switch S20 is connected to the output end of the second comparator 23. That is, the comparator circuit 20 can also be implemented by a two-stage comparator circuit.

[0189] like Figure 8 As shown, the analog-to-digital converter 100 further includes a counter 30, which is connected to the output terminal of the second comparator 23 and is used to generate a quantized value of the sampling signal according to the comparison result of the comparator circuit 20, thereby realizing the mode conversion of the sampling signal.

[0190] In summary, the analog-to-digital converter 100 of the embodiment of the present invention, by adopting the ramp generator 10 and the dual automatic zeroing comparator circuit 20 of the first aspect embodiment, can not only ensure that the slope of the ramp voltage remains unchanged when the manufacturing process, power supply voltage and ambient temperature change during the ramp generation process, but also reduce the system offset, eliminate the non-ideality of the circuit and reduce the column fixed pattern noise under bright conditions.

[0191] Based on the analog-to-digital converter of the above embodiment, a third aspect of the present invention provides an image sensor.

[0192] like Fig.13 As shown, the image sensor 1 of the embodiment of the present invention includes a pixel array 200 and an analog-to-digital converter 100 of the above embodiment. The analog-to-digital converter 100 is used to quantize and convert pixel signals of the pixel array 200 to obtain quantized digital signals of the pixel signals.

[0193] The image sensor 1 according to the embodiment of the present invention adopts the analog-to-digital converter 100 of the above embodiment, which can ensure that during the slope generation process, when the manufacturing process, power supply voltage and ambient temperature change, the slope of the ramp voltage remains unchanged, thereby reducing the system offset, improving the slope accuracy and improving the imaging quality.

[0194] Furthermore, by using the comparator circuit of the above embodiment, it is also possible to eliminate the non-ideality of the circuit and reduce the column fixed pattern noise under bright conditions.

[0195] Based on the image sensor of the above embodiment, a fourth aspect of the present invention provides an electronic device.

[0196] Fig.14 is a block diagram of an electronic device according to an embodiment of the present invention, such as Fig.14As shown, the electronic device 1000 of the embodiment of the present invention includes the image sensor 100 of the above embodiment. The specific structure of the image sensor 100 can refer to the description of the above embodiment, which will not be described again.

[0197] In an embodiment, the electronic device 1000 may include but is not limited to a smart phone, a tablet, or a vehicle-mounted image acquisition device and other devices with an image acquisition function.

[0198] The electronic device 1000 according to the embodiment of the present invention can improve the imaging quality and enhance the imaging performance of the device by adopting the image sensor 1 of the above embodiment.

[0199] Based on the image sensor of the above embodiment, a fifth embodiment of the present invention further proposes a vehicle.

[0200] Fig.15 is a block diagram of a vehicle according to an embodiment of the present invention, such as Fig.15 As shown, a vehicle 2000 includes the image sensor 1 of the above embodiment.

[0201] In the embodiment, the image sensor 1 may be an image sensor on a vehicle-mounted camera or a vehicle-mounted tablet, or an image sensor 1 of a vehicle-mounted device having an image acquisition function.

[0202] The vehicle 2000 according to the embodiment of the present invention can improve the imaging quality by adopting the image sensor 1 of the above embodiment, and provide more accurate information for the image-based control strategy of the vehicle.

[0203] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0204] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A ramp generator, characterized in that: include: A ramp generating circuit, used for generating a ramp signal; A correction circuit, wherein the input end of the correction circuit is connected to the output end of the ramp generating circuit, and the output end of the correction circuit is connected to the ramp signal slope adjustment end of the ramp generating circuit, and is used to generate a ramp adjustment signal to adjust the slope of the ramp signal of each ramp generating cycle of the ramp generating circuit.

2. The ramp generator according to claim 1, characterized in that The correction circuit comprises: A capacitor unit, the capacitor unit is used for sampling, eliminating amplifier offset and integration; a first operational amplifier, wherein a first input terminal of the first operational amplifier is connected to the capacitor unit, a second input terminal of the first operational amplifier is connected to a reference power supply, and an output terminal of the first operational amplifier is connected to a ramp signal slope adjustment terminal of the ramp generating circuit, and is used to output the ramp adjustment signal; A first switch unit, the first switch unit is connected to the capacitor unit, the output end of the first operational amplifier, the output end of the ramp generating circuit and a preset power supply, and is used for switching the circuit connection state of the correction circuit.

3. The ramp generator according to claim 2, characterized in that The capacitor unit comprises: A first capacitor, wherein a first end of the first capacitor is selectively connected to an output end of the ramp generating circuit, and the first capacitor is used to collect a ramp signal output by the ramp generating circuit.

4. The ramp generator according to claim 3, characterized in that The capacitor unit also includes: A second capacitor, wherein the first end of the second capacitor is connected to the second end of the first capacitor, the second end of the second capacitor is connected to the first input end of the first operational amplifier, and the second capacitor is used to eliminate the offset error of the first operational amplifier.

5. The ramp generator according to claim 4, characterized in that The capacitor unit also includes: A third capacitor, wherein the first end of the third capacitor is selectively connected to the second end of the first capacitor and the second end of the second capacitor, and the second end of the third capacitor is selectively connected to the reference power supply and the output end of the first operational amplifier to serve as an integrating capacitor.

6. The ramp generator according to claim 5, characterized in that Each ramp generation cycle in which the ramp generating circuit generates the ramp signal includes a first ramp reset phase, a first ramp hold phase, a first ramp generation phase, a second ramp reset phase, a second ramp hold phase, a second ramp generation phase, and a ramp signal correction phase in sequence, wherein the ramp generation time of the second ramp generation phase is longer than the ramp generation time of the first ramp generation phase.

7. The ramp generator according to claim 6, characterized in that The first switch unit comprises: A first switch, wherein a first end of the first switch is connected to an output end of the ramp generating circuit, a second end of the first switch is connected to a first end of the first capacitor, and the first switch is used to be closed during the ramp signal correction phase.

8. The ramp generator according to claim 7, characterized in that The first switch unit further includes: A second switch, wherein a first end of the second switch is connected to a second end of the first switch and a first end of the first capacitor, a second end of the second switch is connected to a first preset power supply to input a slope termination voltage, and the second switch is used to be closed in the first slope resetting stage, the first slope holding stage, the first slope generating stage, the second slope resetting stage, the second slope holding stage and the second slope generating stage.

9. The ramp generator according to claim 8, characterized in that The first switch unit further includes: a third switch, wherein a first end of the third switch is connected to the second end of the first capacitor and the first end of the second capacitor, a second end of the third switch is connected to a reference power supply to input a reference voltage, and the third switch is used to be closed in the first slope resetting stage, the first slope holding stage, the first slope generating stage, the second slope resetting stage, the second slope holding stage and the second slope generating stage.

10. The ramp generator according to claim 9, characterized in that The first switch unit further includes: A fourth switch, wherein a first end of the fourth switch is connected to the second end of the first capacitor and the first end of the third capacitor, a second end of the fourth switch is connected to the first end of the third capacitor, and the fourth switch is used to close during the ramp signal correction phase.

11. The ramp generator according to claim 10, characterized in that: The first switch unit further includes: a fifth switch, wherein a first end of the fifth switch is connected to the second end of the second capacitor and the first input end of the first operational amplifier, a second end of the fifth switch is connected to the first end of the third capacitor, and the local switch is used to be closed in the first slope resetting stage, the first slope holding stage, the first slope generating stage, the second slope resetting stage, the second slope holding stage and the second slope generating stage.

12. The ramp generator according to claim 11, characterized in that The first switch unit further includes: a sixth switch, wherein a first end of the sixth switch is connected to the second end of the third capacitor, a second end of the sixth switch is connected to the output end of the first operational amplifier, and the sixth switch is configured to be closed in the first slope holding stage, the first slope generating stage, the second slope resetting stage, the second slope holding stage, the second slope generating stage, and the slope signal correction stage.

13. The ramp generator according to claim 12, characterized in that: The first switch unit further includes: A seventh switch, wherein a first end of the seventh switch is respectively connected to the first end of the fifth switch, the first input end of the first operational amplifier, and the second end of the second capacitor, a second end of the seventh switch is respectively connected to the second end of the sixth switch and the output end of the first operational amplifier, and the seventh switch is used to close in the first ramp reset stage.

14. The ramp generator according to claim 13, characterized in that The first switch unit further includes: An eighth switch, wherein a first end of the eighth switch is connected to the second end of the third capacitor and a first end of the sixth switch respectively, a second end of the eighth switch is connected to a reference power supply, and the eighth switch is used to close in the first ramp reset stage.

15. The ramp generator according to claim 1 or 14, characterized in that: The ramp generating circuit comprises: A current source, used to generate a current signal, wherein a first end of the current source is connected to a power supply, and a control end of the current source is connected to an output end of the correction circuit; a second operational amplifier, wherein a first input terminal of the second operational amplifier is connected to a second terminal of the current source, a second input terminal of the second operational amplifier is connected to a reference power supply to input a reference voltage, an output terminal of the second operational amplifier is connected to a first terminal of the first switch, and an output terminal of the second operational amplifier is suitable for outputting a ramp signal; a fourth capacitor, wherein a first end of the fourth capacitor is connected to the first input end of the second operational amplifier, and a second end of the fourth capacitor is selectively connected to the output end of the second operational amplifier and a preset power supply to serve as an integrating capacitor; A second switch unit, wherein the second switch unit is connected to the current source, the second operational amplifier and the fourth capacitor respectively, and is used to switch the circuit connection state of the ramp generating circuit.

16. The ramp generator according to claim 15, characterized in that The second switch unit comprises: a ninth switch, wherein a first end of the ninth switch is connected to the second end of the current source, a second end of the ninth switch is connected to a reference power supply, and is configured to be closed in the first slope reset phase, the first slope hold phase, the second slope reset phase, the second slope hold phase, and the slope signal correction phase; A tenth switch, wherein the first end of the tenth switch is connected to the second end of the current source, and the second end of the tenth switch is connected to the first input end of the second operational amplifier, and is configured to be closed in the first ramp generation stage and the second ramp generation stage, respectively.

17. The ramp generator according to claim 16, characterized in that The actions of the ninth switch and the tenth switch when entering the second ramp reset phase are both performed in advance of the time when the ramp signal is reset to the reset voltage.

18. The ramp generator according to claim 16, characterized in that The actions of the ninth switch and the tenth switch when entering the ramp signal correction phase are both performed in advance of the time when the ramp signal recovers to the ramp termination voltage.

19. The ramp generator according to claim 16, characterized in that The second switch unit further includes: An eleventh switch, wherein a first end of the eleventh switch is connected to a first input end of a second operational amplifier, a second end of the eleventh switch is connected to an output end of the second operational amplifier, and the eleventh switch is used to be closed in the first ramp reset stage and the second ramp reset stage, respectively.

20. The ramp generator according to claim 19, characterized in that The second switch unit further includes: A twelfth switch, wherein the first end of the twelfth switch is connected to the second end of the fourth capacitor, the second end of the twelfth switch is connected to the output end of the second operational amplifier, and the twelfth switch is used to be closed in the first ramp reset stage and the second ramp reset stage respectively.

21. The ramp generator according to claim 20, characterized in that The second switch unit further includes: A thirteenth switch, wherein the first end of the thirteenth switch is connected to the second end of the fourth capacitor, the second end of the thirteenth switch is connected to a preset power supply to input a ramp starting voltage, and the thirteenth switch is used to be closed in the first ramp reset stage and the second ramp reset stage respectively.

22. An analog-to-digital converter, characterized in that: include: The ramp generator according to any one of claims 1 to 21; A comparator circuit is connected to the ramp generator, and is used to obtain a sampling signal and compare the ramp signal of the ramp generator with the sampling signal.

23. The analog-to-digital converter according to claim 22, characterized in that The comparator circuit comprises: a first comparator; a fifth capacitor, wherein a first end of the fifth capacitor is connected to the first input end of the first comparator, and a second end of the fifth capacitor is suitable for inputting a sampling signal or a ramp signal; a sixth capacitor, wherein a first end of the sixth capacitor is connected to the second input end of the first comparator, and a second end of the sixth capacitor is suitable for inputting a sampling signal; A third switch unit, wherein the third switch unit is connected to the first comparator, the fifth capacitor and the sixth capacitor respectively, and is used to switch the working state of the comparator circuit and control the sampling signal and the ramp signal to be input into the first comparator in a time-sharing manner.

24. The analog-to-digital converter according to claim 23, characterized in that The third switch unit comprises: a fourteenth switch, wherein a first end of the fourteenth switch is adapted to input a sampling signal, and a second end of the fourteenth switch is connected to a second end of the fifth capacitor; a fifteenth switch, wherein a first end of the fifteenth switch is adapted to input the sampling signal, and a second end of the fifteenth switch is connected to a second end of the sixth capacitor; The fourteenth switch and the fifteenth switch are both used to close in the reset mode of the comparator circuit and to open in the operation mode of the comparator circuit.

25. The analog-to-digital converter according to claim 24, characterized in that The third switch unit further includes: a sixteenth switch, a first end of the sixteenth switch being connected to the ramp generator to input a ramp signal, and a second end of the sixteenth switch being connected to the second end of the fifth capacitor; a seventeenth switch, wherein a first end of the seventeenth switch is adapted to input the sampling signal, and a second end of the seventeenth switch is connected to a second end of the sixth capacitor; The sixteenth switch and the seventeenth switch are both used to be opened in the reset mode of the comparator circuit and closed in the operation mode of the comparator circuit.

26. The analog-to-digital converter according to claim 25, characterized in that The third switch unit further includes: an eighteenth switch, a first end of the eighteenth switch being connected to the first input end of the first comparator, and a second end of the eighteenth switch being connected to the first power supply end of the first comparator; a nineteenth switch, wherein a first end of the nineteenth switch is connected to the second input end of the first comparator, and a second end of the nineteenth switch is connected to the second power supply end of the first comparator; The eighteenth switch and the nineteenth switch are both used to close in the reset mode of the comparator circuit and to open in the operation mode of the comparator circuit.

27. The analog-to-digital converter according to claim 26, characterized in that When the ramp signal enters the first ramp holding phase from the first reset phase, the comparator circuit switches from the working mode to the reset mode. When the ramp signal enters the first ramp generation phase, the comparator circuit switches from the reset mode to the working mode.

28. The analog-to-digital converter according to claim 27, characterized in that When the ramp signal enters a second reset phase from the first ramp generation phase, the comparator circuit switches from the working mode to the reset mode; When the ramp signal enters the second holding phase from the second reset phase, the comparator circuit switches from the reset mode to the working mode.

29. The analog-to-digital converter according to claim 26, characterized in that The comparator circuit further comprises: A second comparator, wherein a first input terminal of the second comparator is connected to a first power supply terminal of the first comparator, and a second input terminal of the second comparator is connected to a second power supply terminal of the first comparator; A twentieth switch, wherein a first end of the twentieth switch is connected to the second input end of the second comparator, and a second end of the twentieth switch is connected to the output end of the second comparator.

30. The analog-to-digital converter according to claim 29, characterized in that The analog-to-digital converter further comprises: A counter is connected to the output end of the second comparator and is used to generate a quantized value of the sampling signal according to a comparison result of the comparator circuit.

31. An image sensor, characterized in that: It comprises a pixel array and the analog-to-digital converter according to any one of claims 22 to 30, wherein the analog-to-digital converter is used to quantize and convert pixel signals of the pixel array.

32. An electronic device, characterized in that: Comprising the image sensor of claim 31.

33. A vehicle, characterized in that: Comprising the image sensor of claim 31.

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