Display panel

Abstract

The display panel includes: at least one opening; a display area surrounding the at least one opening, wherein the display area includes a plurality of display elements; a first non-display area disposed between the at least one opening and the display area, wherein the first non-display area includes a groove; a thin film encapsulation layer covering the plurality of display elements; the planarization layer is arranged above the groove, and a first end of the planarization layer is overlapped with the thin film packaging layer; the first insulating layer is arranged above the thin film packaging layer; a second insulating layer disposed over the planarization layer, wherein the second insulating layer includes a first via; and a capping layer overlapping the first end of the planarization layer and partially overlapping the first insulating layer and the second insulating layer, where the first via is disposed over the planarization layer.

Description

[0001] This invention application is a divisional application of the invention application with an application date of March 4, 2020, application number 202010142438.9 and invention name “Display Device”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the priority of Korean Patent Application No. 10-2019-0025385 filed on March 5, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0004] One or more embodiments relate to a display panel including a first region and / or an opening and a display device including the display panel. Background Art

[0005] As display devices become thinner and lighter, their use in various applications is increasing.

[0006] Despite ongoing efforts to increase the display area of ​​display devices and reduce non-display areas, various functions associated with display devices have been added to devices utilizing the display devices. Some of these functions require components that are typically disposed in the non-display area. However, as the size of the display area increases and the size of the non-display area decreases, there may not be enough space in the non-display area to dispose these components. As a result, a display device is being developed that includes an opening in the display area for placing such components. Summary of the invention

[0007] Generally, a display device including an opening may have problems such as lifting or peeling of a film around the opening due to the structure of the opening and components around the opening. One or more embodiments are directed to a display panel including an opening having improved quality that can prevent or reduce such problems.

[0008] According to an embodiment, a display device includes: a first region including at least one opening; a second region arranged around the first region; and a third region arranged between the first region and the second region. The second region includes a plurality of display elements, and the third region includes a groove. The display device further includes: a thin film encapsulation layer covering the plurality of display elements and including an inorganic encapsulation layer and an organic encapsulation layer; a planarization layer arranged above the groove; a first insulating layer arranged above the thin film encapsulation layer; a second insulating layer arranged above the planarization layer, and a covering layer overlapping a first end of the planarization layer and partially overlapping the first insulating layer and the second insulating layer. The first end of the planarization layer overlaps the thin film encapsulation layer, and the second insulating layer includes a first through hole.

[0009] In an embodiment, the planarization layer includes an organic insulating material.

[0010] In an embodiment, the cover layer comprises an electrically conductive material.

[0011] In an embodiment, the cover layer comprises a second through hole.

[0012] In an embodiment, the first through hole and the second through hole at least partially overlap each other.

[0013] In an embodiment, the first through hole and the second through hole have substantially the same size.

[0014] In an embodiment, the first insulating layer includes an inorganic insulating material.

[0015] In an embodiment, the second insulating layer includes an inorganic insulating material.

[0016] In an embodiment, a width of a first portion of the capping layer not covering the planarization layer is smaller than a width of a second portion of the capping layer covering the planarization layer.

[0017] In an embodiment, the inorganic encapsulation layer of the thin film encapsulation layer covers the groove, and the first insulating layer covers the inorganic encapsulation layer.

[0018] In an embodiment, the display device further includes a first partition wall disposed in the third region. The first partition wall includes a plurality of insulating layers, and the planarization layer is disposed over the first partition wall.

[0019] According to an embodiment, a display device includes: a first region including at least one opening; a second region arranged around the first region; and a third region arranged between the first region and the second region. The second region includes a plurality of display elements. The display device further includes: a thin film encapsulation layer covering the plurality of display elements; a planarization layer arranged in the third region; a first insulating layer arranged above the thin film encapsulation layer; a second insulating layer arranged above the planarization layer; and an input sensing layer arranged above the plurality of display elements. A first end of the planarization layer overlaps the thin film encapsulation layer, and the second insulating layer includes a first through hole.

[0020] In an embodiment, the input sensing layer includes: a first conductive layer including a first connection electrode; a second conductive layer including a first sensing electrode, a second sensing electrode, and a second connection electrode; and an interlayer insulating layer disposed between the first conductive layer and the second conductive layer.

[0021] In an embodiment, the display device further includes a covering layer overlapping the first end of the planarization layer and partially overlapping the first insulating layer and the second insulating layer. The covering layer is on the same layer as the first conductive layer or the second conductive layer.

[0022] In an embodiment, the cover layer comprises the same material as the first conductive layer or the second conductive layer.

[0023] In an embodiment, the display device further includes a third insulating layer covering the cover layer. The third insulating layer is formed integrally with the interlayer insulating layer.

[0024] In an embodiment, the cover layer comprises a second through hole.

[0025] In an embodiment, the first through hole and the second through hole at least partially overlap each other.

[0026] In an embodiment, the third region includes a groove, and the planarization layer is disposed over the groove.

[0027] In an embodiment, the planarization layer includes an organic insulating material.

[0028] In an embodiment, the thin film encapsulation layer includes at least one inorganic encapsulation layer and at least one organic encapsulation layer, and at least one inorganic encapsulation layer of the thin film encapsulation layer covers the groove.

[0029] In an embodiment, the first insulating layer includes an inorganic insulating material.

[0030] In an embodiment, the second insulating layer includes an inorganic insulating material. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other features will become apparent by describing in detail one or more embodiments thereof with reference to the accompanying drawings, in which:

[0032] Figure 1 is a schematic perspective view of a display device according to an embodiment;

[0033] Figure 2 According to the embodiment, the image is taken along line II-II′. Figure 1 A schematic cross-sectional view of a display device;

[0034] Figure 3 is a schematic plan view of a display panel according to an embodiment;

[0035] Figure 4 is an equivalent circuit diagram schematically showing a pixel of a display panel according to an embodiment;

[0036] Figure 5 is a plan view of a portion of a display panel according to an embodiment, and shows a signal line in a third area;

[0037] Figure 6 is a plan view of a portion of a display panel according to an embodiment, and illustrates a groove in a third region;

[0038] Figure 7According to the embodiment, the Figure 6 A cross-sectional view of a display panel;

[0039] Figure 8 is a schematic plan view of an input sensing layer according to an embodiment;

[0040] Fig. 9A and Fig. 9B is a plan view of each of a first conductive layer and a second conductive layer of an input sensing layer according to an embodiment;

[0041] Fig. 9C According to the embodiment Fig. 9A and Fig. 9B A cross-sectional view of an input sensing layer;

[0042] Fig. 10A and Fig. 10B is a plan view of each of a first conductive layer and a second conductive layer of an input sensing layer according to an embodiment;

[0043] Fig. 10C According to the embodiment Fig. 10A and Fig. 10B A cross-sectional view of an input sensing layer;

[0044] Fig.11A and Fig. 11B is a plan view of each of a first conductive layer and a second conductive layer of an input sensing layer according to an embodiment;

[0045] Fig. 11C According to the embodiment Fig.11A and Fig. 11B A cross-sectional view of an input sensing layer;

[0046] Fig.12 is a cross-sectional view of a display device according to an embodiment;

[0047] Fig.13 According to the embodiment Fig.12 a cross-sectional view of part XIII;

[0048] Fig.14 is a cross-sectional view of a display device according to an embodiment, and shows Fig.12 Part XIV;

[0049] Fig.15 and Fig.16 is a cross-sectional view of a display device according to an embodiment and shows the periphery of a cover layer;

[0050] Fig.17 is a cross-sectional view of a display device according to an embodiment;

[0051] Fig.18is a plan view of a first area and its periphery in a display device according to an embodiment; and

[0052] FIG. 19A to FIG. 19D are schematic plan views of various arrangements of through holes formed in a second insulating layer and a cover layer in a display device according to an embodiment. DETAILED DESCRIPTION

[0053] Exemplary embodiments will be described more fully hereinafter with reference to the accompanying drawings.Throughout the drawings, like reference numerals may refer to like elements.

[0054] It will be understood that the terms "first", "second", "third", etc. are used herein to distinguish one element from another element, and the elements are not limited by these terms. Therefore, the "first" element in an embodiment may be described as the "second" element in another embodiment.

[0055] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0056] It will be understood that when a component such as a film, region, layer, or element is referred to as being "on," "connected to," "coupled to," or "adjacent to" another component, it can be directly on, connected to, coupled to, or adjacent to the other component, or there may be intervening components. It will also be understood that when a component is referred to as being "between" two components, it can be the only component between the two components, or there may be one or more intervening components. It will also be understood that when a component is referred to as "covering" another component, it can be the only component that covers the other component, or one or more intervening components may also cover the other component. Other words used to describe the relationship between elements should be interpreted in a similar manner.

[0057] When the embodiment can be implemented differently, a certain process order can be performed differently from the described order. For example, two processes described in succession can be performed substantially at the same time, or in the reverse order of the described order.

[0058] When a layer, region or component is “connected”, the layer, region or component may not only be “directly connected” but also be “indirectly connected” via another layer, region or component. For example, when a layer, region or component is electrically connected, the layer, region or component may not only be directly electrically connected but also be indirectly electrically connected via another layer, region or component.

[0059] When two or more elements or values ​​are described as being substantially the same or approximately equal to each other, it is understood that the elements or values ​​are the same as each other, indistinguishable from each other, or distinguishable from each other but functionally identical to each other, as would be understood by one of ordinary skill in the art. For example, when two or more elements or values ​​are substantially the same or approximately equal to each other but not identical to each other, it is understood that the two or more elements or values ​​are approximately the same or equal to each other within a measurement error, as would be understood by one of ordinary skill in the art.

[0060] Figure 1 is a schematic perspective view of a display device 1 according to the embodiment.

[0061] Reference Figure 1 The display device 1 includes a first area OA (opening area) and a second area DA (display area). The second area DA at least partially surrounds the first area OA.

[0062] The display device 1 may provide an image by using light emitted from a plurality of pixels disposed in the second area DA. The first area OA may be completely surrounded by the second area DA. The first area OA may be a region in which the component 20 (refer to Figure 2 ) area.

[0063] The third area MA (middle area) may be disposed between the first area OA and the second area DA, and the second area DA may be surrounded by the fourth area PA (peripheral area).

[0064] The third area MA and the fourth area PA may be non-display areas in which pixels are not disposed. The third area MA may be completely surrounded by the second area DA, and the second area DA may be completely surrounded by the fourth area PA.

[0065] Although the display device 1 is described herein as an organic light emitting display device, the embodiment is not limited thereto. For example, according to the embodiment, the display device 1 may be a liquid crystal display device, an inorganic light emitting display device, or a quantum dot light emitting display device.

[0066] although Figure 1 One substantially circular first area OA is shown, but the number and shape of the first areas OA are not limited thereto. For example, according to one or more embodiments, the number of first areas OA may be two or more, and each first area OA may be changed differently to have, for example, a circular shape, an elliptical shape, a polygonal shape such as a triangular shape or a quadrilateral shape, a star shape, a diamond shape, or an atypical shape in a plane (or in a direction perpendicular to the main surface of the substrate).

[0067] The display device 1 may be implemented in various electronic devices, such as, for example, a mobile phone, a notebook computer, or a smart watch.

[0068] Figure 2 According to the embodiment, it is taken along line II-II' Figure 1 Schematic cross-sectional view of a display device 1.

[0069] Reference Figure 2 The display device 1 may include a display panel 10 , an input sensing layer 40 , an optical function layer 50 and a window 60 .

[0070] The display panel 10 can display an image. The display panel 10 includes pixels arranged in the second area DA (display area). The pixels may include a display element and a pixel circuit connected thereto. The display element may include, for example, an organic light emitting diode. Alternatively, the display element may include an inorganic light emitting diode, a quantum dot light emitting diode, etc.

[0071] The input sensing layer 40 obtains coordinate information according to an external input such as, for example, a touch event. The input sensing layer 40 may include a sensing electrode or a touch electrode and a trace connected to the sensing electrode or the touch electrode. The input sensing layer 40 may be provided on the display panel 10. The input sensing layer 40 may sense an external input using, for example, a mutual capacitance method and / or a self capacitance method.

[0072] The input sensing layer 40 may be directly disposed on the display panel 10. The input sensing layer 40 may be formed together with the display panel 10 in the same process, or may be formed by a separate process and combined with the display panel 10 via an adhesive layer such as, for example, an optically clear adhesive (OCA). For example, after the manufacturing process of the display panel 10 is completed, the input sensing layer 40 may be formed by continuously performing a direct deposition process and / or an additional patterning process on the display panel 10. In this case, there may be no adhesive layer between the input sensing layer 40 and the display panel 10.

[0073] although Figure 2 The input sensing layer 40 disposed between the display panel 10 and the optical function layer 50 is shown, but the embodiment is not limited thereto. For example, in an embodiment, the input sensing layer 40 may be disposed on the optical function layer 50.

[0074] The optical function layer 50 may include an anti-reflection layer. The anti-reflection layer may reduce reflectivity of incident light (external light) moving toward the display panel 10 from the outside through the window 60.

[0075] The anti-reflection layer may include a retarder and a polarizer. The retarder may be a film type or a liquid crystal coating type, and may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may be a film type or a liquid crystal coating type. The film type may include a stretchable synthetic resin film, and the liquid crystal coating type may include a predetermined arrangement of liquid crystals.

[0076] The retarder and polarizer may further include a protective film. The retarder and polarizer itself or the protective film may be defined as a base layer of the anti-reflection layer.

[0077] In an embodiment, the anti-reflection layer may include a black matrix and a color filter. The color filter may be set by considering the color of light emitted from each pixel of the display panel 10.

[0078] In an embodiment, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer disposed on different layers from each other. The first reflected light and the second reflected light respectively reflected from the first reflective layer and the second reflective layer may undergo destructive interference, and thus, the reflectivity of the external light may be reduced.

[0079] The optical function layer 50 may include a lens layer. The lens layer may increase the light output efficiency of the light emitted from the display panel 10, or may reduce color deviation. The lens layer may include a layer having a concave lens shape or a convex lens shape and / or may include a plurality of layers having different refractive indices from each other. The optical function layer 50 may include both the anti-reflection layer and the lens layer described above, or may include one of the anti-reflection layer and the lens layer described above.

[0080] The display panel 10, the input sensing layer 40, and the optical function layer 50 may include openings. In this regard, Figure 2 It is shown that the display panel 10 , the input sensing layer 40 , and the optical function layer 50 include first to third openings 10H, 40H, and 50H, respectively, which overlap with each other.

[0081] The first to third openings 10H, 40H, and 50H may correspond to a first area OA (opening area). For example, the first area OA may be formed by the first to third openings 10H, 40H, and 50H. The sizes (or diameters) of the first to third openings 10H, 40H, and 50H may be the same as or different from each other.

[0082] In an embodiment, at least one of the display panel 10, the input sensing layer 40, and / or the optical function layer 50 may not include an opening. For example, one or two components selected from the display panel 10, the input sensing layer 40, and the optical function layer 50 may not include an opening. Therefore, the first area OA may be formed by some but not all of the first to third openings 10H, 40H, and 50H.

[0083] The first area OA may be a component area (eg, a sensor area, a camera area, a speaker area, etc.) in which components 20 such as, for example, a sensor, a camera, a speaker, etc., for adding various functions to the display device 1 are located.

[0084] like Figure 2 As shown by the solid line in , the component 20 may be disposed in the first to third openings 10H, 40H and 50H. Alternatively, as shown by the dotted line, the component 20 may be disposed below the display panel 10 and thus not disposed in any of the first to third openings 10H, 40H and 50H. In this case, one or more of the display panel 10, the input sensing layer 40 and the optical function layer 50 may not include an opening. That is, in this case, at least one of the first to third openings 10H, 40H and 50H may not be included.

[0085] The component 20 may include an electronic component. For example, the component 20 may be an electronic component using light or sound.

[0086] For example, the electronic component may include a sensor using light (e.g., an infrared sensor), a camera receiving light to capture an image, a sensor outputting and sensing light or sound to measure a distance or recognize a fingerprint, etc., a small lamp outputting light, a speaker outputting sound, etc. The electronic component using light may use light in various wavelength ranges, such as visible light, infrared light, ultraviolet light, etc. In some embodiments, the first area OA may be a transmission area capable of transmitting light and / or sound output from the component 20 to the outside or from the outside to the electronic component.

[0087] In an embodiment, when the display device 1 is used to implement, for example, a smart watch or a vehicle dashboard, the component 20 may be a member including a clock hand, a needle indicating predetermined information (e.g., vehicle speed, etc.). When the display device 1 includes a component 20 such as a clock hand or a vehicle dashboard, the component 20 may be exposed to the outside through the window 60, and the window 60 may include an opening corresponding to the first area OA. Alternatively, even when the display device 1 includes a component 20 that does not have a clock hand or a vehicle dashboard (e.g., when the component is a speaker), the window 60 may include an opening corresponding to the first area OA.

[0088] As described above, the component 20 may include component(s) related to the function of the display panel 10 , or may include components such as accessories that increase the aesthetics of the display panel 10 .

[0089] A layer including an adhesive layer such as, for example, OCA may be provided between the window 60 and the optical function layer 50 .

[0090] Figure 3 According to the embodiment Figure 2 Schematic plan view of the display panel 10. Figure 4 is an equivalent circuit diagram schematically showing a pixel P of the display panel 10 according to the embodiment.

[0091] Reference Figure 3, the display panel 10 includes a first area OA (opening area), a second area DA (display area), a third area MA (middle area), and a fourth area PA (peripheral area). Figure 3 There is shown a substrate 100 of the display panel 10. For example, the substrate 100 includes a first area OA, a second area DA, a third area MA, and a fourth area PA.

[0092] The display panel 10 includes a plurality of pixels P disposed in the second area DA. Figure 4 As shown, each pixel P includes a pixel circuit PC and an organic light emitting diode OLED, and the organic light emitting diode OLED is a display element connected to the pixel circuit PC.

[0093] The pixel circuit PC may include a first thin film transistor T1, a second thin film transistor T2, and a storage capacitor Cst. Each pixel P may emit, for example, red light, green light, blue light, or white light through an organic light emitting diode OLED.

[0094] The second thin film transistor T2 as a switching thin film transistor may be connected to the scan line SL and the data line DL, and may transfer a data voltage input from the data line DL to the first thin film transistor T1 according to a switching voltage input from the scan line SL. The storage capacitor Cst may be connected to the second thin film transistor T2 and the driving voltage line PL, and may store a voltage corresponding to a difference between a voltage received from the second thin film transistor T2 and a first power supply voltage ELVDD supplied to the driving voltage line PL.

[0095] The first thin film transistor T1 as a driving thin film transistor can be connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing from the driving voltage line PL through the organic light emitting diode OLED in response to the voltage value stored in the storage capacitor Cst. The driving current can allow the organic light emitting diode OLED to emit light with a predetermined brightness. The opposite electrode (e.g., cathode) of the organic light emitting diode OLED can receive the second power supply voltage ELVSS.

[0096] although Figure 4 The pixel circuit PC shown includes two thin film transistors and one storage capacitor, but the embodiment is not limited thereto. For example, the number of thin film transistors and the number of storage capacitors may be changed differently according to the design of the pixel circuit PC.

[0097] Refer again Figure 3 , the third area MA may surround the first area OA. The third area MA is an area in which a display element such as an organic light emitting diode that emits light is not disposed, and a signal line for supplying a signal to the pixels P disposed around the first area OA may pass through the third area MA.

[0098] A scan driver 1100 for supplying a scan signal to each pixel P, a data driver 1200 for supplying a data signal to each pixel P, a main power line for supplying a first power voltage and a second power voltage, etc. may be disposed in the fourth area PA (peripheral area). Figure 3 The data driver 1200 is disposed adjacent to the side of the substrate 100, but the embodiment is not limited thereto. For example, in an embodiment, the data driver 1200 may be disposed on a flexible printed circuit board (FPCB) electrically connected to a pad disposed on one side of the display panel 10.

[0099] Figure 5 is a plan view of a portion of the display panel according to the embodiment, and shows signal lines in a third area MA (middle area).

[0100] Reference Figure 5 , the pixels P are disposed in the second area DA, and the third area MA (middle area) is disposed between the first area OA and the second area DA. The pixels P adjacent to the first area OA may be spaced apart from each other on a plane relative to the first area OA. The pixels P may be spaced apart vertically relative to the first area OA or may be spaced apart horizontally relative to the first area OA.

[0101] Among the signal lines for supplying signals to the pixels P, the signal lines adjacent to the first area OA may detour the first area OA. Some of the data lines DL passing through the second area DA may extend in the y direction to supply data signals to the pixels P respectively disposed above and below the first area OA with the first area OA located therebetween, and may detour along the edge of the first area OA on the third area MA.

[0102] Some of the scan lines SL passing through the second area DA may extend in the x direction to provide scan signals to pixels P respectively disposed on the left and right sides of the first area OA (with the first area OA located therebetween), and may detour along an edge of the first area OA in the third area MA.

[0103] Figure 6 is a plan view of a portion of a display panel according to an embodiment, and illustrates a groove G in a third area MA.

[0104] Reference Figure 6 , one or more grooves G may be disposed between the first area OA and the second area DA. Figure 6 Three grooves G disposed between the first area OA and the second area DA are shown, but the embodiment is not limited thereto. For example, one, two, or four or more grooves may be disposed in the third area MA according to the embodiment.

[0105] In the plane, the groove G may be disposed in the third area MA (middle area) and may have an annular shape completely surrounding the first area OA. In the plane, the radius of each groove G to the center C of the first area OA may be greater than the radius of the first area OA. The grooves G may be spaced apart from each other.

[0106] Reference Figure 5 and Figure 6 The groove G may be disposed between the first area OA and a detour portion of the data line DL and / or the scan line SL along an edge of the first area OA, and the groove G may be closer to the first area OA than the detour portion of the data line DL and / or the scan line SL along an edge of the first area OA.

[0107] Figure 7 According to the embodiment, the Figure 6 10 is a cross-sectional view of a display panel 10.

[0108] Reference Figure 7 , the pixel circuit PC and the organic light emitting diode OLED electrically connected to the pixel circuit PC may be disposed in the second area DA (display area).

[0109] The pixel circuit PC may be disposed on the substrate 100, and the organic light emitting diode OLED may be disposed on the pixel circuit PC. The pixel circuit PC includes a thin film transistor TFT and a storage capacitor Cst disposed on the substrate 100, and the pixel electrode 221 is electrically connected to the pixel circuit PC.

[0110] The substrate 100 may include, for example, a polymer resin or glass. In an embodiment, the substrate 100 may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide (PI), polycarbonate, cellulose triacetate and / or cellulose acetate propionate, and may have a flexible property.

[0111] In an embodiment, the substrate 100 may include a substrate mainly including SiO 2 of glass or a resin such as reinforced plastic, and may have rigid properties.

[0112] The substrate 100 may have a stacked structure formed by a layer including the above-mentioned polymer resin and a barrier layer located on the above-mentioned polymer resin layer. For example, the substrate 100 may have a structure in which a first polymer resin layer, a first barrier layer, a second polymer resin layer, and a second barrier layer are stacked. The substrate 100 including the polymer resin may increase flexibility. The barrier layer may include, for example, silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiOx )wait.

[0113] A buffer layer 201 that can prevent impurities from penetrating into the semiconductor layer Act of the thin film transistor TFT may be disposed on the substrate 100. The buffer layer 201 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, and silicon oxide, and may have a single layer or multilayer structure including the above inorganic insulating material.

[0114] The pixel circuit PC may be disposed on the buffer layer 201. The pixel circuit PC includes a thin film transistor TFT and a storage capacitor Cst. The thin film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. Figure 7 The thin film transistor TFT shown may be as described above with reference to Figure 4 The driving thin film transistor. Figure 7 A top-gate thin film transistor is shown, in which the gate electrode GE is disposed on the semiconductor layer Act, and the gate insulating layer 203 is disposed between the gate electrode GE and the semiconductor layer Act, but the embodiment is not limited thereto. For example, in an embodiment, the thin film transistor TFT may be a bottom-gate thin film transistor.

[0115] The semiconductor layer Act may include, for example, polycrystalline silicon. Alternatively, the semiconductor layer Act may include, for example, amorphous silicon, may include an oxide semiconductor, or may include an organic semiconductor. The gate electrode GE may include, for example, a low-resistance metal material. The gate electrode GE may include a conductive material including, for example, molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a single-layer or multi-layer structure including the above-mentioned materials.

[0116] The gate insulating layer 203 disposed between the semiconductor layer Act and the gate electrode GE may include an inorganic insulating material such as, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide. The gate insulating layer 203 may have a single layer or multilayer structure including the above materials.

[0117] The source electrode SE and the drain electrode DE may include a highly conductive material. The source electrode SE and the drain electrode DE may include a conductive material, such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a multilayer or single-layer structure including the above materials. In an embodiment, the source electrode SE and the drain electrode DE may include a multilayer composed of Ti / Al / Ti.

[0118] The storage capacitor Cst includes a lower electrode CE1 and an upper electrode CE2 overlapping each other, and a first interlayer insulating layer 205 is disposed therebetween. In an embodiment, the storage capacitor Cst may overlap with the thin film transistor TFT. In this regard, in an embodiment, the gate electrode GE of the thin film transistor TFT may be the lower electrode CE1 of the storage capacitor Cst. In an embodiment, the storage capacitor Cst may not overlap with the thin film transistor TFT. The storage capacitor Cst may be covered by a second interlayer insulating layer 207.

[0119] The first and second interlayer insulating layers 205 and 207 may include inorganic insulating materials such as, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc. The first and second interlayer insulating layers 205 and 207 may have a single layer or multilayer structure including the above materials.

[0120] The pixel circuit PC including the thin film transistor TFT and the storage capacitor Cst may be covered by the planarization insulating layer 209. The planarization insulating layer 209 may include a side having a substantially flat upper surface. The planarization insulating layer 209 may include an organic insulating material, such as a general polymer of poly(methyl methacrylate) (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, and a mixture thereof. In an embodiment, the planarization insulating layer 209 may include PI. Alternatively, the planarization insulating layer 209 may include an inorganic insulating material, or may include an inorganic insulating material and an organic insulating material.

[0121] The pixel electrode 221 may be disposed on the planarization insulating layer 209. The pixel electrode 221 may include a conductive oxide, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). In an embodiment, the pixel electrode 221 may include a reflective film, which includes, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound thereof. In an embodiment, the pixel electrode 221 may further include a film disposed on and / or under the above-mentioned reflective film, which film includes ITO, IZO, ZnO or In 2 O 3 .

[0122] The pixel defining film 211 may be disposed on the pixel electrode 221. The pixel defining film 211 may include an opening exposing the upper surface of the pixel electrode 221 and may cover the edge of the pixel electrode 221. The pixel defining film 211 may include an organic insulating material. Alternatively, the pixel defining film 211 may include an inorganic insulating material, such as silicon nitride (SiN x ), silicon oxynitride (SiON) or silicon oxide (SiO x ). Alternatively, the pixel defining film 211 may include an organic insulating material and an inorganic insulating material.

[0123] The intermediate layer 222 includes an emission layer 222b. The intermediate layer 222 may further include a first functional layer 222a disposed below the emission layer 222b and / or a second functional layer 222c disposed on the emission layer 222b. The emission layer 222b may include a polymer or a low-molecular organic material that emits light having a predetermined color.

[0124] The first functional layer 222a may have a single layer or a multilayer structure. For example, when the first functional layer 222a includes a polymer material, the first functional layer 222a may be a hole transport layer (HTL) having a single layer structure, and may include poly (3,4) -ethylene - dihydroxythiophene (PEDOT) or polyaniline (PANI). When the first functional layer 222a includes a low molecular weight material, the first functional layer 222a may include a hole injection layer (HIL) and the HTL.

[0125] In an embodiment, the second functional layer 222c may be omitted. In an embodiment, when the first functional layer 222a and the emission layer 222b include a polymer material, the second functional layer 222c may be provided. The second functional layer 222c may have a single layer or a multilayer structure. The second functional layer 222c may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0126] The emission layer 222b of the intermediate layer 222 may be provided for each pixel in the second area DA. The emission layer 222b may contact the upper surface of the pixel electrode 221 exposed through the opening in the pixel defining film 211. Unlike the emission layer 222b, the first functional layer 222a and the second functional layer 222c of the intermediate layer 222 may not only exist Figure 7 The second area DA (display area) is present in the third area MA (see Fig.12 For example, in an embodiment, the emission layer 222b is disposed in the second area DA (display area) but not in the third area MA, and the first and second functional layers 222a and 222c are disposed in the second area DA (display area) and the third area MA.

[0127] The opposing electrode 223 may include a conductive material having a low work function. For example, the opposing electrode 223 may include a (semi) transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), alloys thereof, etc. Alternatively, the opposing electrode 223 may further include a layer disposed on the (semi) transparent layer including the above-mentioned materials, such as ITO, IZO, ZnO or In 2 O 3 The opposite electrode 223 may be disposed not only over the second area DA but also over the third area MA (middle area). The middle layer 222 and the opposite electrode 223 may be formed, for example, by thermal deposition.

[0128] The capping layer 230 may be disposed on the opposing electrode 223. The capping layer 230 may include, for example, lithium fluoride (LiF), and may be formed, for example, by thermal deposition. Alternatively, the capping layer 230 may include an inorganic insulating material, such as, for example, silicon oxide, silicon nitride, or silicon oxynitride. Alternatively, the capping layer 230 may include an organic insulating material. Alternatively, the capping layer 230 may be omitted.

[0129] The spacer 213 may be disposed on the pixel defining film 211. The spacer 213 may include an organic insulating material such as PI. Alternatively, the spacer 213 may include an inorganic insulating material such as silicon nitride or silicon oxide, or may include an organic insulating material and an inorganic insulating material.

[0130] The spacer 213 may include a different material from the pixel defining film 211. Alternatively, the spacer 213 may include the same material as the pixel defining film 211, and in this case, the pixel defining film 211 and the spacer 213 may be formed together during a mask process using, for example, a halftone mask. In an embodiment, the pixel defining film 211 and the spacer 213 may include PI.

[0131] The organic light emitting diode OLED is covered by a thin film encapsulation layer 300. For example, the thin film encapsulation layer 300 is disposed on the organic light emitting diode OLED. The thin film encapsulation layer 300 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. In an embodiment, the thin film encapsulation layer 300 includes a first inorganic encapsulation layer 310 and a second inorganic encapsulation layer 330 and an organic encapsulation layer 320 disposed between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330. Figure 7 According to embodiments, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and their stacking order may be changed.

[0132] The first and second inorganic encapsulating layers 310 and 330 may include one or more inorganic insulating materials such as, for example, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, or silicon oxynitride, and may be formed by, for example, chemical vapor deposition (CVD).

[0133] The organic encapsulating layer 320 may include, for example, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyvinyl sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane (HMDSO), acrylic resin (eg, PMMA, poly(acrylic acid), etc.), or any combination thereof.

[0134] The input sensing layer 40 may be disposed on the display panel 10. In an embodiment, the input sensing layer 40 is directly formed on the display panel 10 so that it is in contact with the thin film encapsulation layer 300. Figure 7 shown.

[0135] Figure 8 is a schematic plan view of an input sensing layer 40 according to an embodiment. Figure 8 The input sensing layer 40 is shown corresponding to Figure 7 A portion of the second area DA is shown.

[0136] Reference Figure 8 , the input sensing layer 40 includes a first sensing electrode SP1 and a second sensing electrode SP2 located in the second area DA. In an embodiment, a plurality of first sensing electrodes SP1 are arranged in the x direction and connected to each other, and a plurality of second sensing electrodes SP2 are arranged across the first sensing electrodes SP1 in the y direction and connected to each other. The first sensing electrodes SP1 and the second sensing electrodes SP2 may cross each other in the vertical direction.

[0137] Corners of the first and second sensing electrodes SP1 and SP2 may be adjacent to each other. Adjacent first sensing electrodes SP1 may be electrically connected to each other in the x direction via the first connection electrode CP1, and adjacent second sensing electrodes SP2 may be electrically connected to each other in the y direction via the second connection electrode CP2.

[0138] Fig. 9A and Fig. 9B is an input sensing layer according to an embodiment (e.g., Figure 8 4 and 5. A plan view of a first conductive layer 410 and a second conductive layer 420 of an input sensing layer 40, respectively. Fig. 9C According to the embodiment Figure 8 The line VIII-VIII' is intercepted Fig. 9A and Fig. 9B 4 is a cross-sectional view of the input sensing layer 40.

[0139] Reference Fig. 9Aand Fig. 9B , the first sensing electrode SP1 and the second sensing electrode SP2 may be disposed on the same layer as each other. For example, the first conductive layer 410 may include a first connection electrode CP1 (see Fig. 9A ), the second conductive layer 420 may include a first sensing electrode SP1, a second sensing electrode SP2, and a second connection electrode CP2 (see Fig. 9B ).

[0140] The second sensing electrodes SP2 may be connected to each other through the second connection electrode CP2 disposed on the same layer. For example, the second sensing electrode SP2 and the second connection electrode CP2 may be disposed on the second conductive layer 420 (refer to Fig. 9B ). The first sensing electrodes SP1 may be disposed along the x direction and may be connected to each other through the first connection electrodes CP1 disposed on different layers. For example, the first sensing electrodes SP1 may be disposed on the second conductive layer 420 (refer to Fig. 9B ), and the first connection electrode CP1 may be disposed on the first conductive layer 410 (refer to Fig. 9A ).

[0141] Reference Fig. 9C An interlayer insulating layer or an intermediate insulating layer 403 may be disposed between the first conductive layer 410 and the second conductive layer 420. The first sensing electrode SP1 disposed in the second conductive layer 420 may be connected to the first connection electrode CP1 disposed in the first conductive layer 410 via a contact hole CNT in the intermediate insulating layer 403.

[0142] The second conductive layer 420 may be covered by the upper insulating layer 405, and the lower insulating layer 401 may be disposed under the first conductive layer 410. The lower insulating layer 401 and the intermediate insulating layer 403 may be inorganic insulating layers such as, for example, silicon nitride or organic insulating layers.

[0143] The upper insulating layer 405 may be an organic insulating layer or an inorganic insulating layer. The first conductive layer 410 and the second conductive layer 420 may include a metal layer or a transparent conductive layer. The metal layer may include, for example, molybdenum (Mo), manganese (Mb), silver (Ag), titanium (Ti), copper (Cu), aluminum (Al) and alloys thereof. The transparent conductive layer may include a transparent conductive oxide such as, for example, ITO, IZO, ZnO, indium tin zinc oxide (ITZO), etc. In addition, the transparent conductive layer may include a conductive polymer such as, for example, PEDOT, metal nanowires, carbon nanotubes, graphene, etc.

[0144] exist Fig. 9C In an embodiment, the lower insulating layer 401 is disposed between the thin film encapsulation layer 300 and the first conductive layer 410. In an embodiment, the lower insulating layer 401 may be omitted, and the first conductive layer 410 may be directly disposed on the thin film encapsulation layer 300.

[0145] Fig. 10A and Fig. 10B is an input sensing layer according to an embodiment (e.g., Figure 8 4 and 5. A plan view of a first conductive layer 410 and a second conductive layer 420 of an input sensing layer 40, respectively. Fig. 10C According to the embodiment Figure 8 The line VIII-VIII' is intercepted Fig. 10A and Fig. 10B 4 is a cross-sectional view of the input sensing layer 40.

[0146] Reference Fig. 10A and Fig. 10B , the first conductive layer 410 includes a first sensing electrode SP1 and a first connection electrode CP1 connected to the first sensing electrode SP1, and the second conductive layer 420 includes a second sensing electrode SP2 and a second connection electrode CP2 connected to the second sensing electrode SP2. The first conductive layer 410 may further include a second auxiliary sensing electrode S-SP2 connected to the second sensing electrode SP2, and the second conductive layer 420 may further include a first auxiliary sensing electrode S-SP1 connected to the first sensing electrode SP1.

[0147] Reference Fig. 10A Each first sensing electrode SP1 may have a grid structure including a plurality of holes H. The holes H may overlap with the emission region PE of the pixel. The second sensing electrode SP2, the first auxiliary sensing electrode S-SP1, and the second auxiliary sensing electrode S-SP2 may also have a grid structure including a plurality of holes corresponding to the emission region PE of the pixel, such as Fig. 10A shown.

[0148] Reference Fig. 10C , the first auxiliary sensing electrode S-SP1 can be connected to the first sensing electrode SP1 via the contact hole CNT in the intermediate insulating layer 403. This structure can reduce the resistance of the first sensing electrode SP1. Similarly, the second sensing electrode SP2 can be connected to the second auxiliary sensing electrode S-SP2 via the contact hole CNT in the intermediate insulating layer 403.

[0149] The lower insulating layer 401 and the intermediate insulating layer 403 may be inorganic insulating layers such as silicon nitride, or organic insulating layers, and the upper insulating layer 405 may be an organic insulating layer or an inorganic insulating layer.

[0150] The first conductive layer 410 and the second conductive layer 420 may include a metal layer or a transparent conductive layer. The metal layer may include, for example, molybdenum (Mo), manganese (Mb), silver (Ag), titanium (Ti), copper (Cu), aluminum (Al) and alloys thereof, and may have a single layer or multilayer structure including the above metals. For example, the first conductive layer 410 and the second conductive layer 420 may be a metal layer including three Ti / Al / Ti sublayers. As described above, the transparent conductive layer may include, for example, a transparent conductive oxide, a conductive polymer, a metal nanowire, graphene, etc.

[0151] Fig.11A and Fig. 11B is an input sensing layer according to an embodiment (e.g., Figure 8 4 and 5. A plan view of a first conductive layer 410 and a second conductive layer 420 of an input sensing layer 40, respectively. Fig. 11C According to the embodiment Figure 8 The line VIII-VIII' is intercepted Fig.11A and Fig. 11B 4 is a cross-sectional view of the input sensing layer 40.

[0152] Reference Fig.11A and Fig. 11B The first conductive layer 410 includes the first sensing electrode SP1 and the first connection electrode CP1 connected to the first sensing electrode SP1, and the second conductive layer 420 includes the second sensing electrode SP2 and the second connection electrode CP2 connected to the second sensing electrode SP2.

[0153] Reference Fig. 11C , the intermediate insulating layer 403 may be disposed between the first conductive layer 410 and the second conductive layer 420. The intermediate insulating layer 403 does not include a contact hole, and the first sensing electrode SP1 and the second sensing electrode SP2 may be electrically insulated from each other by the intermediate insulating layer 403 disposed therebetween.

[0154] The second conductive layer 420 may be covered by the upper insulating layer 405. A lower insulating layer 401 including an inorganic material or an organic material may be further included under the first conductive layer 410. The intermediate insulating layer 403 and the upper insulating layer 405 may be organic insulating layers or inorganic insulating layers.

[0155] The first conductive layer 410 and the second conductive layer 420 may include a metal layer or a transparent conductive layer. The metal layer may include, for example, molybdenum (Mo), manganese (Mb), silver (Ag), titanium (Ti), copper (Cu), aluminum (Al) and alloys thereof. The transparent conductive layer may include a transparent conductive oxide such as, for example, ITO, IZO, ZnO, ITZO, etc. In addition, the transparent conductive layer may include a conductive polymer such as, for example, PEDOT, metal nanowires, graphene, etc.

[0156] Fig.12 The display device according to the embodiment is Figure 6 A cross-sectional view taken along line XII-XII'. Fig.13 According to the embodiment Fig.12 Cross-sectional view of section XIII. Fig.14 is a cross-sectional view of a display device according to an embodiment, and shows Fig.12 Part XIV. Fig.15 and Fig.16 is a cross-sectional view of a display device according to an embodiment, and illustrates the periphery of a cover layer 730 . Fig.17 is a cross-sectional view of a display device according to an embodiment.

[0157] Reference Fig.12 , the display panel 10 may include a first opening 10H corresponding to the first area OA.

[0158] The second area DA includes a pixel circuit PC disposed on the substrate 100 , a pixel electrode 221 connected to the pixel circuit PC, and an intermediate layer 222 and an opposing electrode 223 sequentially stacked on the pixel electrode 221 .

[0159] The substrate 100 may include multiple layers. For example, the substrate 100 may include a first base layer 101, a first barrier layer 102, a second base layer 103, and a second barrier layer 104 that are sequentially stacked.

[0160] Each of the first substrate layer 101 and the second substrate layer 103 may include a polymer resin. For example, the first substrate layer 101 and the second substrate layer 103 may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate and / or cellulose acetate propionate. The above polymer resin may be transparent.

[0161] Each of the first barrier layer 102 and the second barrier layer 104 is a barrier layer that can prevent external foreign matter from penetrating, and may include a material such as silicon nitride (SiN x ) and / or silicon oxide (SiO x ) of a single or multilayer structure of inorganic materials.

[0162] The pixel circuit PC is located on the substrate 100 and includes, for example, a thin film transistor and a storage capacitor. The organic light emitting diode including the pixel electrode 221, the emission layer of the intermediate layer 222 and the opposite electrode 223 emits predetermined light and is covered by the thin film encapsulation layer 300. The components arranged in the second area DA are the same as those described above with reference to Figure 7 Those described are the same, and for the convenience of description, further description thereof is omitted.

[0163] Reference Fig.12 , the third area MA may include a first sub-middle area SMA1 relatively adjacent to the second area DA and a second sub-middle area SMA2 relatively adjacent to the first area OA or the first opening 10H. For example, the first sub-middle area SMA1 is closer to the second area DA than it is to the first area OA, and the second sub-middle area SMA2 is closer to the first area OA than it is to the second area DA.

[0164] The first sub-middle area SMA1 may be where the signal line (eg, Figure 5 The area through which the data line DL) is passed. Fig.12 The data line DL shown may correspond to a data line that detours the first area OA. The first sub-middle area SMA1 may be a line area or a detour area through which the data line DL passes. In an embodiment, the width of the first sub-middle area SMA1 may be less than or greater than the width of the second sub-middle area SMA2. In an embodiment, the width of the first sub-middle area SMA1 may be substantially the same as the width of the second sub-middle area SMA2.

[0165] like Fig.12 As shown, the data lines DL may be alternately arranged with an insulating layer disposed therebetween. For example, a first group of data lines DL may be disposed on the first interlayer insulating layer 205, a second interlayer insulating layer 207 may be disposed above the first group of data lines DL, and a second group of data lines DL may be disposed above the second interlayer insulating layer 207. The first group and the second group of data lines DL may be arranged in an alternating manner. When adjacent data lines DL are disposed above and below respectively with an insulating layer (e.g., the second interlayer insulating layer 207) disposed between adjacent data lines DL, the gap (spacing) between adjacent data lines DL may be reduced, and the width of the third region MA may be reduced.

[0166] In an embodiment, the data lines DL may be disposed on the same insulating layer (eg, the second interlayer insulating layer 207). Fig.12 The data lines DL disposed in the first sub-middle area SMA1 are shown, but as mentioned above with reference to Figure 5 The scan line that bypasses the first area OA may also be arranged in the first sub-middle area SMA1.

[0167] The shielding layer 80 may be disposed on the data lines DL and / or scan lines located in the first sub-middle area SMA1. The shielding layer 80 may overlap the data lines DL and / or scan lines, thereby preventing a user from seeing the data lines DL and / or scan lines. In an embodiment, the shielding layer 80 may include metal.

[0168] The second sub-middle area SMA2 is a groove area including a plurality of grooves G. Although Fig.12 Five grooves G provided in the second sub middle area SMA2 are illustrated, but the embodiment is not limited thereto and the number of the grooves G may be variously changed.

[0169] Each groove G may be in a multilayer film including a first layer and a second layer having materials different from each other. For example, in an embodiment, the groove G may be provided in a sublayer of the substrate 100, such as Fig.12 shown.

[0170] Reference Fig.12 and Fig.13 , the groove G may be formed by removing a portion of the second barrier layer 104 and a portion of the second base layer 103. The hole H2 formed through the second barrier layer 104 and the recess R1 formed in the second base layer 103 may be spatially connected to form the groove G. The second base layer 103 may correspond to the first layer of the above-mentioned multilayer film, and the second barrier layer 104 may correspond to the second layer of the multilayer film.

[0171] In the process of forming the groove G, a portion of the buffer layer 201 disposed on the second barrier layer 104 may be removed together with the second barrier layer 104 to form the hole H2. Although the buffer layer 201 and the second barrier layer 104 are described as separate components herein, in an embodiment, the buffer layer 201 disposed on the substrate 100 may be a sublayer of the second barrier layer 104 having a multi-layer structure.

[0172] The width of a portion of the groove G passing through the second barrier layer 104 (e.g., the hole H2) may be smaller than the width of a portion of the groove G passing through the second base layer 103 (e.g., the recess R1). The width W2 (or diameter) of the hole H2 may be smaller than the width W1 (or diameter) of the recess R1, and the groove G may have an undercut cross section.

[0173] The side surface of the second barrier layer 104 defining the hole H2 may protrude more toward the center of the groove G than the side surface of the second base layer 103 defining the recess R1. Fig.13 As shown, the distance from the side surface of the second barrier layer 104 adjacent to the groove G to the center of the groove G may be smaller than the distance from the side surface of the second base layer 103 adjacent to the groove G to the center of the groove G. The portion of the second barrier layer 104 protruding toward the center of the groove G may constitute a pair of eaves (or a pair of protruding ends or ends PT). The buffer layer 201 may also constitute a pair of eaves together with the second barrier layer 104.

[0174] The groove G may be formed before the process of forming the intermediate layer 222. A portion 222' of the intermediate layer 222, such as the first functional layer 222a and / or the second functional layer 222c extending to the third area MA, is discontinuous around the groove G. For example, the groove G may produce a break (or disconnection) in the intermediate layer 222. Similarly, the relative electrode 223 and the capping layer 230 including, for example, LiF may be discontinuous around the groove G. For example, the groove G may produce a break (or disconnection) in the relative electrode 223 and the capping layer 230. The length l of each of a pair of ends PT may be less than about 2.0 μm. For example, in an embodiment, the length l may be about 1.0 μm to about 1.8 μm.

[0175] although Fig.12 and Fig.13 It is shown that the bottom surface of the groove G is located on an imaginary plane between the bottom surface and the upper surface of the second base layer 103, but the embodiment is not limited thereto. For example, in an embodiment, the bottom surface of the groove G may be located on the same plane as the bottom surface of the second base layer 103. For example, during the etching process for forming the groove G, the depth dp of the recess R1 may be substantially the same as the thickness t of the second base layer 103, and in this case, the bottom surface of the groove G may be located on the same plane as the bottom surface of the second base layer 103. The depth dp of the recess R1 may be about 2.0 μm or more. When the depth dp of the recess R1 is substantially the same as the thickness t of the second base layer 103, the recess R1 may form a hole passing through the second base layer 103.

[0176] like Fig.12 As shown, the thin film encapsulation layer 300 covering the display element in the second area DA (display area) may extend to cover the third area MA. For example, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may extend to the third area MA.

[0177] The first and second inorganic encapsulating layers 310 and 330 may be formed, for example, by CVD and may have relatively good step coverage compared to the portion 222' of the intermediate layer 222 or the opposite electrode 223. Therefore, the first and second inorganic encapsulating layers 310 and 330 may each be continuous around the groove G instead of being discontinuous.

[0178] The first inorganic encapsulation layer 310 may cover the inner surface of the groove G. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may have different thicknesses from each other. For example, the first inorganic encapsulation layer 310 may have a thickness of about 1 μm, and the second inorganic encapsulation layer 330 may have a smaller thickness of about 0.7 μm. Alternatively, the thickness of the first inorganic encapsulation layer 310 and the thickness of the second inorganic encapsulation layer 330 may be substantially the same as each other, or the thickness of the first inorganic encapsulation layer 310 may be less than the thickness of the second inorganic encapsulation layer 330.

[0179] although Fig.12 and Fig.13 The capping layer 230 including LiF is shown as a discontinuous structure around the groove G, but the embodiment is not limited thereto. For example, in an embodiment, when the capping layer 230 includes an inorganic material like the first inorganic encapsulation layer 310, the capping layer 230 may continuously cover the inner surface of the groove G, rather than being discontinuous around the groove G. That is, in this case, the groove G does not generate a fracture (or disconnection) in the capping layer 230.

[0180] like Fig.12 As shown, the organic encapsulating layer 320 may cover the second area DA, and may have an end portion 320E disposed on one side of the first partition wall 510. The end portion 320E of the organic encapsulating layer 320 may contact the first partition wall 510.

[0181] The organic encapsulating layer 320 may be formed, for example, by dispersing and curing a monomer. The flow of the monomer may be controlled by the first partition wall 510 , and the thickness of the organic encapsulating layer 320 may be controlled by the first partition wall 510 .

[0182] The organic encapsulation layer 320 (eg, the end portion 320E of the organic encapsulation layer 320 ) may be spaced apart from the first area OA. As a result, external moisture penetrating through the first opening 10H may be prevented from traveling to the organic light emitting diode of the second area DA (display area) via the organic encapsulation layer 320 .

[0183] The first partition wall 510 may include a plurality of layers (eg, a plurality of insulating layers). Fig.12 The first partition wall 510 is shown to have a stacked structure formed of a layer including the same material as the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207, and a layer including the same material as the planarization insulating layer 209 and the pixel defining film 211. However, the embodiment is not limited thereto. For example, in an embodiment, the number of layers constituting the first partition wall 510 may be greater than or less than Fig.12 The number of layers shown.

[0184] The organic material layer 320A is adjacent to the first area OA and is spaced apart from the organic encapsulation layer 320 by a predetermined distance. The organic material layer 320A may be formed in the same process as the organic encapsulation layer 320 and may include the same material as the organic encapsulation layer 320. Since the flow of the monomer is regulated by the first partition wall 510 during the formation of the organic encapsulation layer 320, the organic material layer 320A may be regulated by the second partition wall 520, and an end portion 320AE of the organic material layer 320A may be disposed on one side of the second partition wall 520.

[0185] like Fig.12 As shown, the first inorganic encapsulating layer 310 and the second inorganic encapsulating layer 330 may be located over the third area MA while contacting each other.

[0186] When the contact area between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 is approximately equal to or greater than a certain value, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 or a surrounding layer (for example, a planarization layer 720 described later) may be lifted due to the stress of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330. However, by arranging Fig.12 The organic material layer 320A is shown to reduce the contact area between the first inorganic encapsulating layer 310 and the second inorganic encapsulating layer 330, thereby preventing or reducing such lifting.

[0187] When the organic material layer 320A is disposed spaced apart from the organic encapsulating layer 320 , the first inorganic encapsulating layer 310 and the second inorganic encapsulating layer 330 may contact each other between an end portion 320E of the organic encapsulating layer 320 and an end portion 320AE of the organic material layer 320A.

[0188] The planarization layer 720 may be disposed in the third area MA.

[0189] The planarization layer 720 may be an organic insulating layer. The planarization layer 720 may include a polymer-based material. The planarization layer 720 may include, for example, silicone resin, acrylic resin, epoxy resin, PI, polyethylene, etc. The polymer-based material may be transparent.

[0190] In an embodiment, the planarization layer 720 may include a material different from the organic encapsulation layer 320. For example, in an embodiment, the organic encapsulation layer 320 may include a silicone-based resin, and the planarization layer 720 may include an acrylic resin. In an embodiment, the organic encapsulation layer 320 and the planarization layer 720 may include the same material as each other.

[0191] The planarization layer 720 may cover at least one groove G in the third area MA. The planarization layer 720 may increase the flatness of the display panel 10 around the first area OA by covering at least an area in the third area MA that is not covered by the organic encapsulation layer 320. Therefore, the flatness of the display panel 10 may be prevented or reduced. Figure 2 ) input sensing layer 40 and / or ( Figure 2 The problem of separation or detachment of the optical functional layer 50 of the planarization layer 720 is solved. A portion of the planarization layer 720 may overlap with the organic encapsulation layer 320. One end of the planarization layer 720, for example, a first end 720E1 adjacent to the second area DA, may be disposed on the organic encapsulation layer 320. For example, the first end 720E1 of the planarization layer 720 may overlap with the thin film encapsulation layer 300.

[0192] The planarization layer 720 may be formed over the third area MA by, for example, an exposure and development process. During some formation processes (e.g., a washing process) of the planarization layer 720, when external foreign matter (e.g., moisture) travels in a lateral direction (e.g., a direction parallel to the xy plane) of the display panel 10, the organic light emitting diode of the second area DA may be damaged. However, according to an embodiment, by arranging insulating layers (e.g., a first insulating layer 710 and a second insulating layer 740) respectively below and above the planarization layer 720, the above-mentioned problems caused by moisture penetration and / or lifting of the surrounding film during and after the formation process of the planarization layer 720 may be prevented or reduced.

[0193] The first insulating layer 710 may be disposed directly below the planarization layer 720. For example, the first insulating layer 710 may contact the planarization layer 720, and no other layer may exist between the first insulating layer 710 and the planarization layer 720. The first insulating layer 710 may include an inorganic insulating material such as, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0194] The first insulating layer 710 may directly contact the thin film encapsulation layer 300. For example, the first insulating layer 710 may directly contact an upper surface of the second inorganic encapsulation layer 330.

[0195] The first insulating layer 710 may include the same material as the second inorganic encapsulating layer 330, or may include a material different from the second inorganic encapsulating layer 330. Even if the first insulating layer 710 includes the same material as the second inorganic encapsulating layer 330, such as silicon nitride, the detailed composition ratio (e.g., the content ratio of silicon and nitrogen) may be different, and an interface may exist between the first insulating layer 710 and the second inorganic encapsulating layer 330. The thickness of the first insulating layer 710 may be less than the thickness of the second inorganic encapsulating layer 330. Alternatively, the thickness of the first insulating layer 710 may be substantially the same as or greater than the thickness of the second inorganic encapsulating layer 330.

[0196] The second insulating layer 740 may be disposed on the planarization layer 720, for example, directly on the planarization layer 720. The second insulating layer 740 may include an inorganic insulating material such as, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0197] The first insulating layer 710 and the second insulating layer 740 may include the same material as each other or may include different materials from each other. The thickness of the second insulating layer 740 may be greater than the thickness of the first insulating layer 710. Alternatively, the thickness of the second insulating layer 740 may be less than or substantially equal to the thickness of the first insulating layer 710.

[0198] The planarization layer 720 may have a step relative to the underlying layer. Fig.14 , the first end 720E1 of the planarization layer 720 may have a step relative to its lower layer, for example, the upper surface of the first insulating layer 710. During the operation of manufacturing the display panel 10 and / or the operation of using the display panel 10 after manufacturing, in order to prevent the first end 720E1 of the planarization layer 720 from being separated or lifted from its lower layer due to the above steps, the first end 720E1 of the planarization layer 720 may be covered by the second insulating layer 740 and / or the cover layer 730.

[0199] In an embodiment, the capping layer 730 may completely overlap the first end 720E1 of the planarization layer 720, and may partially overlap the first insulating layer 710 and the second insulating layer 740, such as Fig.14 shown.

[0200] The cover layer 730 may include a material different from the first insulating layer 710 and the second insulating layer 740. For example, the cover layer 730 may include the same material as the first conductive layer 410 and / or the second conductive layer 420 of the input sensing layer 40 located in the second area DA. In an embodiment, the cover layer 730 may include a conductive material such as a metal.

[0201] The third width W3 of the cover layer 730 may be tens to hundreds of μm. For example, the third width W3 of the cover layer 730 may be about 50 μm to about 500 μm, about 50 μm to about 400 μm, about 50 μm to about 300 μm, about 50 μm to about 200 μm, about 50 μm to about 100 μm, or about 60 μm to about 100 μm.

[0202] The capping layer 730 may be disposed on the planarization layer 720. For example, the capping layer 730 may be directly disposed on the second insulating layer 740 covering the planarization layer 720.

[0203] In order to prevent the first end 720E1 of the planarization layer 720 from being separated or lifted from its lower layer due to the above steps, the upper portion of the planarization layer 720 is covered by the second insulating layer 740, and the capping layer 730 is formed close to the first end 720E1 of the planarization layer 720. However, gas components generated in the planarization layer 720 may accumulate and cause the capping layer 730 to lift.

[0204] According to an embodiment, by forming a plurality of through holes 740H in the second insulating layer 740 directly contacting the planarization layer 720 , degassing of the planarization layer 720 may be promoted, and thus lifting of the capping layer 730 may be prevented or reduced.

[0205] For example, according to an embodiment, each through hole 740H is not filled with another material. As a result, degassing of the planarization layer 720 can be promoted through the through hole 740H, and lifting of the cover layer 730 can be prevented or reduced. For example, although some material used to form a layer directly above the through hole 740H can enter the through hole 740H, the through hole 740H is not completely filled and remains at least partially open even if it is not completely open. As a result, the gas released by the planarization layer 720 can be released into the through hole 740H, which can reduce the pressure and thus prevent or reduce the lifting of the cover layer 730 that may be caused if the through hole 740H is not present.

[0206] In an embodiment, the first end 730E1 of the cover layer 730 is not disposed above the planarization layer 720 in a first portion of the cover layer 730 that further extends beyond the first end 720E1 of the planarization layer 720 in a direction toward the second area DA. Fig.14 The second end 730E2 of the capping layer 730 may be disposed above the planarization layer 720 in a second portion of the capping layer 730 that extends above the planarization layer 720 in a direction toward the first area OA.

[0207] The width W31 of the first portion of the cover layer 730 may be smaller than the width W32 of the second portion of the cover layer 730. For example, the width W31 of the first portion of the cover layer 730 may be about 20 μm, and the width W32 of the second portion of the cover layer 730 may be about 60 μm.

[0208] like Fig.14 As shown, in an embodiment, a first portion of the cover layer 730 having a width W31 does not cover the planarization layer 720, and a second portion of the cover layer 730 having a width W32 covers the planarization layer 720. Therefore, in an embodiment, the width W31 of the first portion of the cover layer 730 not covering the planarization layer 720 is smaller than the width W32 of the second portion of the cover layer 730 covering the planarization layer 720.

[0209] The third insulating layer 750 and the fourth insulating layer 760 may be disposed on the capping layer 730. The third insulating layer 750 may include an inorganic insulating material such as, for example, silicon oxide, silicon nitride, or silicon oxynitride. Alternatively, the third insulating layer 750 may include an organic insulating material. The fourth insulating layer 760 may include an inorganic insulating material or may include an organic insulating material. The fourth insulating layer 760 including an organic insulating material may have a substantially flat upper surface. The organic insulating material may be a photoresist (negative or positive), or may include a polymer-based organic material.

[0210] At least one of the first insulating layer 710, the second insulating layer 740, the third insulating layer 750, and the fourth insulating layer 760 may include the same as described above. Figures 8 to 11C The input sensing layer 40 is described as comprising the same material as the insulating layer.

[0211] In an embodiment, each of the first insulating layer 710, the second insulating layer 740, the third insulating layer 750, and the fourth insulating layer 760 may be formed in the same manner as described above. Figures 8 to 11C At least one insulating layer of the input sensing layer 40 is formed together in the same process as described. Fig.12 As shown, the first insulating layer 710 may include the same material as the first sub-lower insulating layer 401a, which is a part of the lower insulating layer 401 of the input sensing layer 40, and the first insulating layer 710 may be formed integrally with the first sub-lower insulating layer 401a of the input sensing layer 40. The second insulating layer 740 may include the same material as the second sub-lower insulating layer 401b, which is a part of the lower insulating layer 401, and the second insulating layer 740 may be formed integrally with the second sub-lower insulating layer 401b. The third insulating layer 750 may include the same material as the middle insulating layer 403 of the input sensing layer 40, and may be formed integrally with the middle insulating layer 403. The fourth insulating layer 760 may include the same material as the upper insulating layer 405 of the input sensing layer 40, and may be formed integrally with the upper insulating layer 405. In an embodiment, the first insulating layer 710, the second insulating layer 740, and the third insulating layer 750 may include an inorganic insulating material, and the fourth insulating layer 760 may include an organic insulating material.

[0212] The first opening 10H and the second opening 40H of the display device 1 may be formed, for example, by performing a cutting or scribing process after forming the above-mentioned components and layers on the substrate 100 .

[0213] In this regard, Fig.12The cross-sectional structure can be understood as a cross-sectional view of the display panel 10 manufactured by performing a cutting or scribing process along the first line SCL1. The end of the layer disposed on the substrate 100 around the first area OA may be on the same vertical line as the end 100E of the substrate 100 defining the first opening 10H. For example, the end 710E of the first insulating layer 710, the second end 720E2 of the planarization layer 720, and the end 740E of the second insulating layer 740 may be on the same vertical line as the end 100E of the substrate 100 defining the opening 100H. Similarly, the ends of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330, the organic material layer 320A, and the third and fourth insulating layers 750 and 760 may also be on the same vertical line as the end 100E of the substrate 100.

[0214] Fig.12 The illustrated region from the first line SCL1 to the n-th line SCLn may be a region CA through which a laser may pass in a cutting or scribing process in a manufacturing process of a display panel. That is, a cutting or scribing process may be performed along one of the first to n-th lines SCL1 to SCLn, and the resulting cross-sectional structure may correspond to the structure of a display device according to one or more embodiments.

[0215] Reference Fig.15 and Fig.16 According to an embodiment, the cover layer 730 may include a second through hole 730H. The width of the second through hole 730H may vary. In an embodiment, the second through hole 730H may overlap with the first through hole 740H, such as Fig.15 The second through hole 730H may completely overlap with the first through hole 740H (eg, the second through hole 730H may be aligned with the first through hole 740H), as shown in FIG. Fig.15 As shown, the second through hole 730H may at least partially overlap with the first through hole 740H. The second through hole 730H may have substantially the same size as the first through hole 740H. In an embodiment, the second through hole 730H does not overlap with the first through hole 740H. Fig.16 shown.

[0216] According to an embodiment, the through holes 730H and 740H are not filled with another material. As a result, the degassing of the planarization layer 720 can be promoted by the through holes 730H and 740H. For example, although some materials used to form a layer directly above the through holes 730H and 740H can enter the through holes 730H and 740H, the through holes 730H and 740H are not completely filled, and remain at least partially open even if not completely open. As a result, the gas released by the planarization layer 720 can be released into the through holes 730H and 740H, which can reduce the pressure and thus prevent or reduce the lifting of the cover layer 730 that may be caused if the through holes 730H and 740H are not present.

[0217] Fig.17 FIG. 4 shows a cross-sectional structure of the display panel 10 in which a cutting or scribing process is performed along the n-th line SCLn. Fig.12 The cross-sectional structure of the display panel shown in which one of the first to n-th lines SCL1 to SCLn undergoes a cutting or scribing process may correspond to an embodiment of the present application.

[0218] Fig.12 and Fig.17 The cross-sectional structure shown can be understood as a structure surrounding the first area OA. Figure 6 As described above, the groove G disposed between the first area OA and the second area DA may have a ring shape surrounding the first opening 10H and the first area OA. Similarly, on the plane, Fig.12 The planarization layer 720 may have a ring shape surrounding the first opening 10H and the first area OA, and in this regard, Fig.18 A planarization layer 720 is shown.

[0219] Fig.18 1 is a plan view of a first area OA and its periphery in a display device according to an embodiment, which is extracted from a planarization layer 720 and a capping layer 730 for convenience of description.

[0220] Reference Fig.18 The planarization layer 720 may have a ring shape surrounding the first area OA. The planarization layer 720 may be disposed in the third area MA, and on the plane, the second end 720E2 of the planarization layer 720 may be substantially the same as the profile of the first area OA.

[0221] The cover layer 730 may at least partially cover the first end 720E1 of the planarization layer 720. In this regard, Fig.18 The cover layer 730 is shown to have a ring shape surrounding the first area OA and completely covering the first end 720E1 of the planarization layer 720. However, the embodiment is not limited thereto. For example, in an embodiment, the cover layer 730 may partially cover the first end 720E1 of the planarization layer 720 and may have a shape partially surrounding the first area OA on the plane.

[0222] As described above, the cover layer 730 may include and include ( Fig.12 The same material as one of the conductive layers in the input sensing layer 40 and may be included in ( Fig.12The cover layer 730 may be disposed on the same layer as one of the conductive layers in the input sensing layer 40. For example, the cover layer 730 may include the same material as the first conductive layer 410 of the input sensing layer 40 or the second conductive layer 420 of the input sensing layer 40, and may be disposed on the same layer as the first conductive layer 410 of the input sensing layer 40 or the second conductive layer 420 of the input sensing layer 40.

[0223] The cover layer 730 may include a metal layer. For example, the cover layer 730 may have a metal multilayer structure in which, for example, a titanium layer, an aluminum layer, and a titanium layer are sequentially stacked.

[0224] FIG. 19A to FIG. 19D Various arrangements of vias in the second insulating layer 740 and the cover layer 730 according to embodiments are shown.

[0225] Fig.19A and Fig.19B An embodiment is shown in which only the second insulating layer 740 includes the first through hole 740H. Fig.19A The first through-holes 740H are shown arranged in columns, wherein the first through-holes 740H are aligned with each other in adjacent columns. Fig.19B The first through holes 740H are shown arranged in columns, wherein the first through holes 740H in adjacent columns are not aligned with each other. Fig.19B In the embodiment, the first through holes 740H in alternating columns may be aligned with each other.

[0226] Fig.19C and Fig.19D An embodiment is shown in which the second insulating layer 740 includes a first through hole 740H and the cover layer 730 includes a second through hole 730H. Fig.19C It is shown that some of the second through holes 730H overlap with the first through holes 740H, and some of the second through holes 730H do not overlap with the first through holes 740H. Fig.19D The second through hole 730H and the first through hole 740H are shown completely overlapping each other.

[0227] although FIG. 19A to FIG. 19D A quadrilateral through hole is shown, but the embodiment is not limited thereto. For example, in the embodiment, the through hole may be variously modified to have, for example, a circular shape, an elliptical shape, a polygonal shape such as a triangle or a quadrilateral, a star shape, a diamond shape, an atypical shape, etc.

[0228] According to one or more embodiments, malfunctions such as lifting or peeling of a film surrounding an opening area may be prevented or reduced.

[0229] Although one or more embodiments have been described herein with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the disclosure as defined by the following claims.

Claims

1. A display panel, comprising: at least one opening; a display area surrounding the at least one opening, wherein the display area includes a plurality of display elements; a first non-display area disposed between the at least one opening and the display area, wherein the first non-display area includes a groove; a thin film encapsulation layer covering the plurality of display elements; a planarization layer disposed above the groove, wherein a first end of the planarization layer overlaps the thin film encapsulation layer; a first insulating layer disposed above the thin film encapsulation layer; a second insulating layer disposed over the planarization layer, wherein the second insulating layer includes a first through hole; and a capping layer overlapping the first end of the planarization layer and partially overlapping the first insulating layer and the second insulating layer, The first through hole is arranged above the planarization layer. 2 . The display panel according to claim 1 , wherein the planarization layer comprises an organic insulating material. The display panel according to claim 1 , wherein the cover layer comprises a conductive material. The display panel according to claim 1 , wherein the cover layer comprises a second through hole. The display panel of claim 4 , wherein the first through hole and the second through hole at least partially overlap each other. The display panel according to claim 5 , wherein the first through hole and the second through hole have the same size. The display panel according to claim 1 , wherein the first insulating layer comprises an inorganic insulating material. The display panel according to claim 1 , wherein the second insulating layer comprises an inorganic insulating material. 9 . The display panel according to claim 1 , wherein a width of a first portion of the cover layer not covering the planarization layer is smaller than a width of a second portion of the cover layer covering the planarization layer.

10. The display panel according to claim 1, wherein the thin film encapsulation layer comprises an inorganic encapsulation layer and an organic encapsulation layer, The inorganic encapsulation layer of the thin film encapsulation layer covers the groove, and The first insulating layer covers the inorganic encapsulation layer.

11. The display panel according to claim 1, further comprising: a first partition wall disposed in the first non-display area, wherein the first partition wall comprises a plurality of insulating layers, The planarization layer is disposed on the first partition wall.

12. The display panel according to claim 1, further comprising a second non-display area surrounding the display area, The second non-display area includes drivers and / or wires electrically connected to the plurality of display elements in the display area. 13 . The display panel of claim 1 , wherein the first through hole comprises a plurality of through holes which are aligned with each other in adjacent columns in a plan view. 14 . The display panel of claim 1 , wherein the first through hole comprises a plurality of through holes which are not aligned with each other in adjacent columns but are aligned with each other in alternate columns in a plan view.

15. A display panel, comprising: at least one opening; a display area surrounding the at least one opening, wherein the display area includes a plurality of display elements; a first non-display area disposed between the at least one opening and the display area; a second non-display area surrounding the display area; a thin film encapsulation layer covering the plurality of display elements; a planarization layer disposed in the first non-display area, wherein a first end of the planarization layer overlaps the thin film encapsulation layer; a first insulating layer disposed above the thin film encapsulation layer; a second insulating layer disposed over and directly contacting the planarization layer, wherein the second insulating layer includes a first through hole; and An input sensing layer is disposed above the plurality of display elements.

16. The display panel according to claim 15, wherein the input sensing layer comprises: A first conductive layer including a first connecting electrode; A second conductive layer including a first sensing electrode, a second sensing electrode, and a second connecting electrode; and An interlayer insulating layer is disposed between the first conductive layer and the second conductive layer.

17. The display panel according to claim 16, further comprising: a covering layer overlapping the first end of the planarization layer and partially overlapping the first insulating layer and the second insulating layer; The covering layer is on the same layer as the first conductive layer or the second conductive layer. 18 . The display panel according to claim 17 , wherein the cover layer comprises a same material as the first conductive layer or the second conductive layer. 19 . The display panel of claim 17 , wherein the interlayer insulating layer extends over the cover layer and overlaps the cover layer.

20. The display panel of claim 17, wherein the cover layer comprises a second through hole.

21. The display panel according to claim 15, wherein the first non-display area comprises a groove, and The planarization layer is disposed above the groove.

22. The display panel according to claim 21, wherein the thin film encapsulation layer comprises at least one inorganic encapsulation layer and at least one organic encapsulation layer; The at least one inorganic encapsulation layer in the thin film encapsulation layer covers the groove.

23. The display panel of claim 15, wherein the second non-display area comprises drivers and / or wires electrically connected to the plurality of display elements of the display area.

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