Circuit design method and circuit design platform

Abstract

The invention discloses a circuit design method and a circuit design platform. Determining a time sequence margin threshold range corresponding to one or more time sequence paths in the first asynchronous circuit; searching an error time sequence path in the one or more time sequence paths through the time sequence analysis instruction; wherein the error time sequence path is a path in which the time sequence margin of the time sequence path exceeds a corresponding time sequence margin threshold range, the time sequence margin is the difference between a first time length and a second time length, the first time length is the time length from a transmitting clock of a first latch to a capturing clock of a second latch in the corresponding time sequence path, and the second time length is the time length from the transmitting clock of the second latch to the capturing clock of the second latch in the corresponding time sequence path. The second duration is a data calculation duration between the first latch and the second latch in the corresponding time sequence path; and adjusting a capture clock of a second latch of the error timing path to a clock position matched with the corresponding timing margin threshold range through the timing processing instruction. By adopting the embodiment of the invention, the problem of time sequence chaos in an asynchronous circuit realized based on a latch can be solved.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits, and in particular to a circuit design method and a circuit design platform. Background Art

[0002] Integrated Circuit (IC) is an electronic product that integrates one or more electronic devices (such as transistors, resistors, capacitors, etc.) on a tiny silicon chip and realizes its circuit functions and system functions through microelectronic process technology. Compared with traditional discrete component circuits, integrated circuits have the advantages of small size, light weight, low power consumption and high performance.

[0003] Register-based asynchronous circuits are an existing asynchronous circuit design method that uses registers as the main data storage and transmission elements, and uses asynchronous handshake templates to enable data to be transmitted without being constrained by the global clock. Instead, whenever a module is ready to send or receive data, it communicates through an asynchronous handshake template. This ensures the correct and synchronous transmission of data between different modules. Compared with traditional asynchronous designs based on combinational logic, register-based designs provide higher scalability, modularity, and easier integration with synchronous design methods.

[0004] Unlike registers that are edge-triggered, latches are triggered by changes in data signals or enable signals. If asynchronous circuits are designed based on latches, there may be timing confusion. For example, a transparent latch has the characteristic of high-level transparency, which can transmit or capture clocks at any time during the high-level conduction period, thereby greatly improving the response speed and performance; however, because of the high-level transparency of the transparent latch, the uncertainty of the transmitted clock and captured clock will result, so there are a large number of timing error problems in asynchronous circuits implemented based on transparent latches. How to solve the problem of timing confusion in asynchronous circuits implemented based on latches is a technical problem that needs to be solved urgently. Summary of the invention

[0005] The technical problem to be solved by the embodiments of the present application is to provide a circuit design method and a circuit design platform to solve the problem of timing confusion of asynchronous circuits implemented based on latches.

[0006] In a first aspect, an embodiment of the present application provides a method for asynchronous circuit design, which may include:

[0007] Applied to a first asynchronous circuit; the first asynchronous circuit includes M-level pipelines, where M is an integer greater than 1; wherein each level of the pipeline is controlled by an independent pulse signal; each level of the pipeline includes one or more latches, wherein a timing path is formed between a first latch and a second latch, and the first latch and the second latch are latches in the adjacent upper-level pipeline and next-level pipeline, respectively; the method includes: determining a timing margin threshold range corresponding to one or more timing paths in the first asynchronous circuit; finding errors in the one or more timing paths through a timing analysis instruction A timing path; wherein the erroneous timing path is a path whose timing margin exceeds a corresponding timing margin threshold range, and the timing margin is a difference between a first duration and a second duration, wherein the first duration is a duration between a transmission clock of the first latch in the corresponding timing path and a capture clock of the second latch, and the second duration is a data calculation duration between the first latch and the second latch in the corresponding timing path; through a timing processing instruction, the capture clock of the second latch of the erroneous timing path is adjusted to a clock position that matches the corresponding timing margin threshold range.

[0008] The embodiment of the present application provides a method for asynchronous circuit design. For the timing confusion problem that may exist in the asynchronous circuit design based on latches, a solution for quickly finding the timing confusion path (i.e., the wrong path) and adjusting the timing confusion is provided to achieve the correct timing constraints of the asynchronous circuit implemented based on latches, synthesize the correct circuit and realize the corresponding functions. Specifically, the threshold range of the timing margin corresponding to each timing path is first determined, and then the erroneous timing paths in the asynchronous circuit are screened through the timing analysis instructions in the circuit design tool, and the timing paths whose timing margins are not within the corresponding timing margin threshold range are quickly found (for example, the timing paths whose timing margins are less than the A value, and / or the timing paths whose timing margins are greater than the B value), and then the number of clock cycles of each erroneous timing path (that is, the capture clock corresponding to the latch used to capture data in the timing path) is adjusted to the corresponding correct number of clock cycles through the timing processing instructions, thereby realizing the rapid finding of the erroneous timing path (that is, the erroneous timing path can be found by screening through the boundary value of the timing margin threshold range), and accurate timing adjustment of the erroneous timing path (that is, the erroneous timing path in the result can be specifically identified, avoiding the overall adjustment of the entire asynchronous circuit), so that the asynchronous circuit based on latch implementation can be designed by using the existing circuit design tools without the need for special circuit design tools, and the design cost, design efficiency and design performance of the asynchronous circuit can be guaranteed. In the prior art, the timing check method is usually for asynchronous circuits implemented based on registers, and there is no timing check method for asynchronous circuits implemented by latches. Among them, the report generated by the timing check method is an important basis for designers to evaluate and adjust the design, but the timing disorder will cause this process to fail to proceed normally; and the timing adjustment method is also usually to perform global timing adjustment on the entire circuit structure, or only perform local inspection and adjustment. Since there are too many timing paths that need to be compared or only local timing optimization leads to global timing imbalance, there may be problems such as high cost, performance degradation, or circuit abnormality. In summary, the embodiment of the present application is based on the implementation of asynchronous circuits based on latches, and the error timing path is quickly screened out through the timing margin threshold range, and the timing adjustment is accurately performed through the identification result. The error timing path is found with a small amount of resources and a faster speed, and the timing adjustment is performed for the error timing path, which reduces the waste of resources and improves the performance of various aspects of circuit design, thereby solving the problem of timing disorder of asynchronous circuits implemented based on latches.

[0009] In a possible implementation, the one or more timing paths correspond to the same timing margin threshold range; or, the one or more timing paths correspond to their respective margin threshold ranges. In an embodiment of the present application, the threshold range of the timing margin can be flexibly set according to the actual needs and application scenarios of the circuit. Specifically, multiple timing paths can correspond to the same timing margin threshold range, that is, when adjusting the timing, all timing paths can be processed uniformly, avoiding the cumbersome process of repeatedly inputting the threshold ranges of different paths (for example, the timing margin thresholds corresponding to all latches in the same level pipeline can be set to the same); optionally, one or more timing paths can also correspond to their respective margin threshold ranges, that is, set their margin standards according to the actual conditions of each path, and provide greater design freedom. In summary, by corresponding multiple timing paths to the same timing margin threshold range, or allowing timing paths to correspond to their respective margin threshold ranges, the setting method of the timing margin threshold can be flexibly selected according to the needs of circuit design to enhance the flexibility of timing analysis in circuit design.

[0010] In a possible implementation, the boundary value of the timing margin threshold range is a multiple of the clock cycle of the target pulse signal, and the target pulse signal is the pulse signal of the pipeline stage to which the first latch in the corresponding timing path belongs. In the embodiment of the present application, the timing margin threshold range can be set to a multiple of the clock cycle of the pulse signal of the pipeline stage to which the first latch in the corresponding timing path belongs, so that the timing analysis instruction in the circuit design tool can screen the erroneous timing path in the asynchronous circuit; in the prior art, because the timing margin of some timing paths may be too large or too small, it cannot be directly and intuitively reported in the timing report, and the timing disorder usually occurs after the first latch corresponding to the timing path performs data calculation and before the second latch successfully captures the clock (i.e., captures data). In the embodiment of the present application, by setting the timing margin threshold range to a multiple of the clock cycle of the pulse signal corresponding to the first latch in the data path, the timing margin and the timing margin threshold can be compared with the clock reference value of the same pulse signal, thereby improving the accuracy of finding the timing path with timing disorder.

[0011] In one possible implementation, a timing analysis instruction is executed through a timing analysis report tool in the EDA, wherein the input parameters of the timing analysis instruction include a timing margin threshold range corresponding to the one or more timing paths; and an erroneous timing path whose timing margin exceeds the corresponding timing margin threshold range is output. In an embodiment of the present application, a timing analysis instruction is executed based on a timing analysis report tool in an EDA, and the instruction is executed using a timing margin threshold range corresponding to the timing path as an input parameter of the instruction. The erroneous timing paths are screened out by comparing the boundary values ​​of the timing margin threshold range in the timing analysis report tool, and there is no need to determine whether each timing path is an erroneous timing path one by one, thereby improving the speed and performance of checking the timing paths. In the prior art, checking the timing paths may require designers to identify the timing margin of each timing path one by one, or compare them one by one with the boundary values ​​of the timing threshold range. In an embodiment of the present application, the boundary values ​​of the timing margin threshold range are used as parameters for screening the timing analysis instruction, so that the erroneous timing paths that are not within the timing margin threshold range can be screened out in the timing analysis report tool, thereby improving the speed of checking the timing paths.

[0012] In a possible implementation, the method further includes: marking or recording the erroneous timing path by any one or more of software tags, log files, database records, and graphical interface annotations. In the embodiment of the present application, by specially marking the erroneous timing path, it is possible to quickly identify the erroneous timing path during timing processing to improve the speed of timing processing; for these erroneous timing paths that have been marked, in subsequent timing processing, on the one hand, by adding clear marks to the erroneous timing paths, the system can quickly locate and identify these paths in the data stream, and this fast identification mechanism can reduce the time and computing resource consumption of searching for the source of the problem in a large data set, thereby increasing processing speed and efficiency; on the other hand, accurate marking not only speeds up the location of the problem, but the automated marking and recording mechanism reduces these potential risks and improves the accuracy and reliability of the system.

[0013] In one possible implementation, the second latch in the error timing path belongs to the latch in the target level pipeline; the capture clock of the second latch of the error timing path is adjusted to a clock position that matches the corresponding timing margin threshold range through the timing processing instruction, including: adjusting the capture clocks of all latches in the target level pipeline to a clock position that matches the corresponding timing margin threshold range through the timing processing instruction. In an embodiment of the present application, a timing processing instruction can be used to uniformly operate the capture clocks of latches in the target level pipeline to which the second latch in the erroneous timing path belongs, so as to achieve a uniform adjustment of the capture clocks of the erroneous timing paths; in the prior art, the erroneous timing paths are mostly adjusted separately, which may result in a reduction in the timing processing speed. Optionally, the timing paths in the entire circuit can be uniformly adjusted, but because the capture clocks of the timing paths in pipelines of different levels may be different, a uniform adjustment of the entire circuit may cause timing confusion in the timing paths in pipelines of some levels; and in an embodiment of the present application, the capture clocks of latches at the same level are adjusted using a pulse signal as a constraint, which can not only improve the speed and performance of the timing processing, but also greatly avoid the occurrence of more erroneous timing paths.

[0014] In a possible implementation, a first netlist file of a second asynchronous circuit is obtained; the second asynchronous circuit includes M-level pipelines, wherein each level of the pipeline is controlled by an independent pulse signal; each level of the pipeline includes one or more target memories, each of the target memories is an edge-triggered memory, and a timing path is formed between two registers of two adjacent pipelines; a receiving module recognizes instructions to identify the target memory in the first netlist file; the N target memories in the first netlist file are replaced with the latches respectively to obtain the first asynchronous circuit, where N is an integer greater than or equal to 1; and a second netlist file for designing the first asynchronous circuit is generated. In an embodiment of the present application, an asynchronous circuit based on a latch can be designed using existing circuit tools and design logic (i.e., related tools and processes for asynchronous circuit design based on registers), thereby realizing an asynchronous circuit based on a latch based on existing design resources and design processes. Specifically, based on the generation of the corresponding first netlist file (e.g., gate-level netlist file) based on the second asynchronous circuit, the module recognition instruction is received to identify one or more target memories that need to be replaced, thereby accurately determining which parts need to be converted; through the above-mentioned identification information, each of the above-mentioned target memories that need to be replaced is replaced with a latch (e.g., the identification information of the target memory can be replaced with the identification information of the latch), so that the asynchronous circuit based on the latch is realized through a simple replacement operation. In the prior art, the second asynchronous circuit based on the target memory is controlled by a clock signal, while the latch in the first asynchronous circuit in the embodiment of the present application is controlled by an enable signal, for example, it can work without a clock signal, and the latch is operated only during the activation of the enable signal, and no additional power consumption is generated at other times, so the performance of the circuit can be improved, the power consumption can be reduced, and the effect of simplifying the circuit design can be achieved; after completing the above-mentioned replacement operation, a second netlist file for designing the first asynchronous circuit will be generated, so that subsequent steps, such as timing check verification and simulation, can be more convenient. In summary, the embodiments of the present application replace the target memory with a latch, thereby achieving flexibility, performance improvement, power consumption reduction and simpler system integration, thereby establishing a highly energy-efficient asynchronous circuit based on a latch.

[0015] In a possible implementation, the N target memories are target memories distributed in one or more target areas in the second asynchronous circuit; the module identification instruction includes identification information of the one or more target areas, and identification information of the N target memories. In the embodiment of the present application, the identification information of the target area to be replaced and the identification information of these target memories are obtained through the module identification instruction (for example, the identification instruction executed by programming tools such as Python or matlab), so that the part to be replaced can be clearly replaced (for example, the target area to which the target memory belongs that can improve performance after replacement), without replacing the entire second asynchronous circuit, so as to avoid partial performance degradation or circuit structure errors.

[0016] In a possible implementation, the N target memories in the first netlist file are replaced with the latches, respectively, including: replacing the device names and port information of the N target memories with the device names and port information of the latches. In the embodiment of the present application, by replacing the device names and port information of the N target memories with the device names and port information of the latches, respectively, it can be ensured that the other parts of the circuit remain unchanged, thereby maintaining the integrity and functional stability of the circuit; specifically, the device name and port information of the memory are used to determine its position and function in the entire circuit, and the replacement of the memory can be achieved by adjusting the above information without adjusting other settings (such as connection line information), avoiding the tedious work of resetting the circuit structure, greatly simplifying the memory replacement process, and improving work efficiency.

[0017] In a possible implementation, the module identification instruction is executed by one or more programming tools in Python or matlab. In the embodiment of the present application, the module identification instruction can be executed by one or more programming tools in Python or matlab, so as to support the overall design of the register-based asynchronous circuit or the register-latch replacement of the target area in the design to realize the latch-based asynchronous circuit; and the replacement process can be encapsulated as a replacement program by Python or matlab programming tools, and the registers in different target areas are replaced in batches, so as to realize efficient replacement work.

[0018] In a possible implementation, the target memory is a register. In the embodiment of the present application, the existing asynchronous circuit based on register implementation can be modified, and the asynchronous circuit based on latch is implemented by only changing part of the structure (for example, replacing the register with a latch), without the need to fully design the entire asynchronous circuit, so that the existing circuit design can be simply used to implement the asynchronous circuit based on latch, reducing the design cost.

[0019] In a possible implementation manner, the latch in the first asynchronous circuit is one or more of a transparent latch, a pulse latch, and a multi-phase clock latch. In the embodiments of the present application, the latch can be set to one or more of a transparent latch, a pulse latch and a multi-phase clock latch, so as to flexibly realize asynchronous circuit design and different effects based on the characteristics of different latches; specifically, the transparent latch has the characteristic of high-level transparency, and can transmit or capture the clock at any time point during the high-level conduction period, thereby greatly improving the response speed and performance; for the pulse latch, its delay time is much smaller than the register, and because the latch is transparent, this design is not affected by clock offset and jitter to a certain extent, and the timing model of the pulse-triggered latch is simpler than the latch and is similar to a faster register, which makes the pulse latch an ideal timing unit for high-performance and low-power ASIC design and traditional high-performance microprocessor design; based on the multi-phase clock latch, the design of the clock-driven master and slave latches, and the circuit is optimized in conjunction with the retiming method, the latch design based on the multi-phase clock can better play the characteristics of latch timing borrowing and further play the performance of the circuit.

[0020] In a possible implementation, the timing processing instruction is executed by a timing analysis report tool in an electronic design automation tool EDA. In the embodiment of the present application, the electronic design automation tool EDA can be used to perform timing processing on asynchronous circuits; in the prior art, it is usually necessary to design a special tool for each different asynchronous circuit design method, and the embodiment of the present application can use the existing electronic design automation tool EDA to design asynchronous circuits based on latch implementation without the need for special circuit design tools, while ensuring the design cost, design efficiency and design performance of the asynchronous circuit.

[0021] In a possible implementation, the first asynchronous circuit includes one or more control paths, and the pulse signal corresponding to each stage of the pipeline is controlled by an independent control path, and each pulse signal is generated by the corresponding control path based on one or more asynchronous handshake protocol interactions. In the embodiment of the present application, a pulse signal is generated as a local clock after the asynchronous handshake protocol interaction to implement a latch-based asynchronous circuit or a register-based asynchronous circuit; specifically, the asynchronous handshake protocol is used in the embodiment of the present application, and there is no need to wait for the synchronization signal, that is, a pulse signal can be generated in the control path as a local clock, and the frequency can be changed according to the change of the data, and the target module can be selected to be turned on or off, so as to optimize the performance and power consumption and improve the flexibility of the system in processing data; in addition, since the asynchronous handshake operation is only triggered when the data arrives, the power consumption of the asynchronous circuit will be reduced in the absence of data transmission, which is conducive to optimizing resource utilization and improving performance.

[0022] In a possible implementation, the asynchronous handshake protocol includes a Click asynchronous handshake protocol. In the embodiment of the present application, the Click asynchronous handshake protocol can be used to implement an asynchronous circuit, which can filter out glitches and reduce the possibility of false triggering of latches; based on the Click asynchronous handshake protocol, a short pulse signal can be generated. Because the short pulse signal has a short duration, data can be transmitted faster, thereby reducing the waiting time for data transmission and greatly improving the performance of the circuit.

[0023] In a second aspect, an embodiment of the present application provides a circuit design platform, which is applied to the design of a first asynchronous circuit; the first asynchronous circuit includes M-level pipelines, where M is an integer greater than 1; wherein each level of the pipeline is controlled by an independent pulse signal; each level of the pipeline includes one or more latches, wherein a timing path is formed between the first latch and the second latch, and the first latch and the second latch are latches in the adjacent upper-level pipeline and next-level pipeline, respectively; the circuit design platform may include:

[0024] A determination module is configured to determine a timing margin threshold range corresponding to one or more timing paths in the first asynchronous circuit;

[0025] A first identification module is configured to search for an erroneous timing path in the one or more timing paths through a timing analysis instruction; wherein the erroneous timing path is a path whose timing margin exceeds a corresponding timing margin threshold range, and the timing margin is a difference between a first duration and a second duration, wherein the first duration is a duration between a transmitting clock of the first latch in the corresponding timing path and a capturing clock of the second latch, and the second duration is a data calculation duration between the first latch and the second latch in the corresponding timing path;

[0026] The timing processing module adjusts the capture clock of the second latch of the erroneous timing path to a clock position matching the corresponding timing margin threshold range through the timing processing instruction.

[0027] The embodiment of the present application provides a method for asynchronous circuit design. For the timing confusion problem that may exist in the asynchronous circuit design based on latches, a solution for quickly finding the timing confusion path (i.e., the wrong path) and adjusting the timing confusion is provided to achieve the correct timing constraints of the asynchronous circuit implemented based on latches, synthesize the correct circuit and realize the corresponding functions. Specifically, the threshold range of the timing margin corresponding to each timing path is first determined, and then the erroneous timing paths in the asynchronous circuit are screened through the timing analysis instructions in the circuit design tool, and the timing paths whose timing margins are not within the corresponding timing margin threshold range are quickly found (for example, the timing paths whose timing margins are less than the A value, and / or the timing paths whose timing margins are greater than the B value), and then the number of clock cycles of each erroneous timing path (that is, the capture clock corresponding to the latch used to capture data in the timing path) is adjusted to the corresponding correct number of clock cycles through the timing processing instructions, thereby realizing the rapid finding of the erroneous timing path (that is, the erroneous timing path can be found by screening through the boundary value of the timing margin threshold range), and accurate timing adjustment of the erroneous timing path (that is, the erroneous timing path in the result can be specifically identified, avoiding the overall adjustment of the entire asynchronous circuit), so that the asynchronous circuit based on latch implementation can be designed by using the existing circuit design tools without the need for special circuit design tools, and the design cost, design efficiency and design performance of the asynchronous circuit can be guaranteed. In the prior art, the timing check method is usually for asynchronous circuits implemented based on registers, and the number of clock cycles of each timing path needs to be compared with the corresponding correct number of clock cycles one by one, and the timing adjustment method is also usually to perform global timing adjustment on the entire circuit structure, or only perform local inspection and adjustment. Since there are too many timing paths that need to be compared or only local timing optimization leads to global timing imbalance, there may be problems such as high cost, performance degradation, or circuit abnormality. In summary, the embodiment of the present application is based on the implementation of asynchronous circuits based on latches, and the erroneous timing paths are quickly screened out through the timing margin threshold range, and the timing adjustment is accurately performed through the identification results. The erroneous timing path is found with a small amount of resources and a faster speed, and the timing adjustment is performed for the erroneous timing path, which reduces the waste of resources and improves the performance of various aspects of circuit design, thereby solving the problem of timing confusion of asynchronous circuits implemented based on latches.

[0028] In a possible implementation manner, the one or more timing paths correspond to the same timing margin threshold range; or, the one or more timing paths correspond to respective margin threshold ranges.

[0029] In a possible implementation, a boundary value of the timing margin threshold range is a multiple of a clock period of a target pulse signal, and the target pulse signal is a pulse signal of a pipeline stage to which the first latch in a corresponding timing path belongs.

[0030] In a possible implementation, the circuit design platform includes EDA; and the first identification module is specifically configured to:

[0031] Running a timing analysis instruction through a timing analysis report tool in the EDA, wherein an input parameter of the timing analysis instruction includes a timing margin threshold range corresponding to the one or more timing paths;

[0032] The faulty timing paths whose output timing margin exceeds the corresponding timing margin threshold range.

[0033] In a possible implementation, the circuit design platform further includes:

[0034] The marking module marks or records the error timing path based on the error timing path through any one or more of software tags, log files, database records, and graphical interface annotations.

[0035] In a possible implementation, the second latch in the error timing path belongs to a latch in a target level pipeline; and the timing processing module is specifically configured to:

[0036] Through the timing processing instruction, the capture clocks of all latches in the target level pipeline are adjusted to the clock position matching the corresponding timing margin threshold range.

[0037] In a possible implementation, the circuit design platform further includes:

[0038] An acquisition module is used to acquire a first netlist file of a second asynchronous circuit; the second asynchronous circuit includes M-stage pipelines, wherein each stage of the pipeline is controlled by an independent pulse signal; each stage of the pipeline includes one or more target memories, each of the target memories is an edge-triggered memory, and a timing path is formed between two registers of two adjacent stages of the pipeline;

[0039] A second identification module, used for receiving a module identification instruction and identifying the target memory in the first netlist file;

[0040] A replacement module, used for replacing N target memories in the first netlist file with the latches respectively to obtain the first asynchronous circuit, where N is an integer greater than or equal to 1;

[0041] A generating module generates a second netlist file for designing the first asynchronous circuit.

[0042] In a possible implementation, the N target memories are target memories distributed in one or more target areas in the second asynchronous circuit; the module identification instruction includes identification information of the one or more target areas and identification information of the N target memories.

[0043] In a possible implementation, the replacement module is specifically used to:

[0044] Replacing the device names and port information of the N target memories with the device name and port information of the latch respectively;

[0045] The first instantiation information of the N target memories is replaced with the second instantiation information of the latch respectively.

[0046] In a possible implementation, the circuit design platform includes one or more programming tools in Python or MATLAB; the module recognition instruction is an instruction executed by one or more programming tools in Python or MATLAB.

[0047] In a possible implementation manner, the target memory is a register.

[0048] In a possible implementation manner, the latch in the first asynchronous circuit is one or more of a transparent latch, a pulse latch, and a multi-phase clock latch.

[0049] In a possible implementation, the circuit design platform includes EDA; and the timing processing instruction is an instruction executed by a timing analysis report tool in the EDA.

[0050] In a possible implementation, the first asynchronous circuit includes one or more control paths, and the pulse signal corresponding to each pipeline stage is controlled by an independent control path, and each pulse signal is generated by the corresponding control path after one or more asynchronous handshake protocol interactions.

[0051] In a possible implementation, the asynchronous handshake protocol includes a Click asynchronous handshake protocol.

[0052] In a third aspect, an embodiment of the present application provides a computer storage medium for storing computer software instructions used in a circuit design platform provided in the second aspect above, which includes a program for executing the program designed in the above aspect.

[0053] In a fourth aspect, an embodiment of the present application provides a computer program, which includes instructions. When the computer program is executed by a computer, the computer can execute the process executed in the circuit design platform in the second aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.

[0055] Figure 1A It is a structural schematic diagram of a circuit design platform provided in an embodiment of the present application.

[0056] Figure 1B This is a schematic diagram of a first asynchronous circuit structure implemented based on a latch provided in an embodiment of the present application.

[0057] Figure 1C This is a schematic diagram of a first asynchronous circuit generating a pulse signal through an asynchronous handshake protocol provided in an embodiment of the present application.

[0058] Figure 1D It is a schematic diagram of a second asynchronous circuit structure implemented based on a target memory provided in an embodiment of the present application.

[0059] Figure 1E This is a schematic diagram of a second asynchronous circuit providing a pulse signal through an asynchronous handshake protocol according to an embodiment of the present application.

[0060] Figure 1F This is a schematic diagram of first storage component identification information provided in an embodiment of the present application.

[0061] Figure 1G This is a schematic diagram of a pulse generating circuit provided in an embodiment of the present application.

[0062] Figure 1H It is a schematic diagram of a memory storage mechanism provided in an embodiment of the present application.

[0063] Figure 2A It is a flowchart of a timing processing provided in an embodiment of the present application.

[0064] Figure 2B It is a flowchart of implementing asynchronous circuit design based on a latch provided in an embodiment of the present application.

[0065] Figure 2C It is a schematic diagram of the overall process of an asynchronous circuit design provided in an embodiment of the present application.

[0066] Figure 2D It is a schematic diagram of the overall process of another asynchronous circuit design provided in an embodiment of the present application.

[0067] Figure 3A It is a timing analysis schematic diagram based on a first asynchronous circuit provided in an embodiment of the present application.

[0068] Figure 3B This is an example diagram of an erroneous clock cycle based on a first asynchronous circuit provided in an embodiment of the present application.

[0069] Figure 3C This is another example diagram of an erroneous clock cycle based on a first asynchronous circuit provided in an embodiment of the present application.

[0070] Figure 3D An example diagram of a normal clock cycle based on a first asynchronous circuit is provided in an embodiment of the present application. DETAILED DESCRIPTION

[0071] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0072] In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0073] The terms "first", "second", "third", and "fourth" in the specification and claims of the present application and the drawings are used to distinguish different objects rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. A process, device, system, product, or equipment that exemplarily includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units inherent to the process, device, product, or equipment.

[0074] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0075] First, some terms in this application are explained to facilitate understanding by those skilled in the art.

[0076] (1) Asynchronous Circuit: An electronic circuit in which the operation sequence between components is determined by a local or distributed trigger mechanism rather than by a global clock signal. In an asynchronous circuit, signal transmission usually depends on data and control signals rather than a unified clock signal.

[0077] (2) Latch: A basic storage element in digital electronics used to store binary information. The latch is level-triggered. When the enable terminal is high, the output of the latch changes as the input changes.

[0078] (3) Register: A small storage device used to temporarily store and move data. A register is an edge-triggered memory. Edge triggering is generally divided into two types:

[0079] Rising Edge Triggered: When the input signal jumps from a low level to a high level (0 to 1), the register samples the input signal at the rising edge and can change its stored state according to the change of the input signal.

[0080] Falling Edge Triggered: In contrast to rising edge triggering, when the input signal changes from a high level to a low level (1 to 0), the register samples the input signal at the falling edge and can change its stored state according to the change of the input signal.

[0081] (4) Asynchronous Handshake Protocol: A communication template used to transmit data and control information in asynchronous circuit design. It can also be called an asynchronous handshake protocol. In asynchronous circuit design, the operations between components are not synchronized by a global clock, but are coordinated and synchronized through local handshake signals. The asynchronous handshake template allows the sender and receiver to work together when transmitting data, even if their operating rates are different.

[0082] For example, the Click asynchronous handshake template is a two-way communication mechanism based on request and confirmation signals, which enables reliable data transmission without a global clock. In the Click template, the sender and receiver each have their own request and confirmation signals.

[0083] (5) Synchronous Circuit: A synchronous circuit is a digital logic circuit in which all operations are synchronized by a global clock signal. All logic units and storage elements of a synchronous circuit are controlled by a unified clock signal, which ensures that the operation of the entire system is orderly and synchronous, and all operations are performed on a specific edge of the clock signal (usually the rising edge or the falling edge).

[0084] (6) Clock Cycle: In microprocessors and other digital integrated circuits, the clock cycle is the time from one complete rising edge to the next rising edge of the clock signal in the digital system, or from one falling edge to the next falling edge. It defines the basic time unit of logical operations in the system. The operation of asynchronous circuits does not rely on a unified clock signal, but when the input changes, the output will change accordingly.

[0085] (7) Electronic Design Automation (EDA): EDA is a collection of software tools used for the design and development of electronic systems (such as integrated circuits, printed circuit boards, etc.). EDA tools provide engineers and designers with a variety of functions for designing, simulating, analyzing, and producing electronic systems.

[0086] DC synthesis, also known as logic synthesis, is an automated process that converts RTL (register transfer level) descriptions into gate-level descriptions. RTL descriptions are usually expressed in hardware description languages ​​such as Verilog or VHDL. This process is performed by EDA (electronic design automation) tools.

[0087] (8) Static Timing Analysis (STA): It is a key step in the integrated circuit design process. It is used to evaluate whether the digital design can meet the timing requirements under all possible operating conditions and chip process changes, and to derive the timing margin (Slack), which measures the difference between the actual signal transmission time and the expected timing requirements.

[0088] (9) Data Path: A set of functional units and connections used to perform data processing and computing tasks. The data path is usually a core component of complex electronic systems such as processor architectures, ASICs (application-specific integrated circuits), and FPGAs (field-programmable gate arrays). It usually includes a series of hardware components used to perform specific tasks, such as arithmetic logic units (ALUs), registers, multipliers, adders, caches, and the complex logic and circuits connected to them.

[0089] In digital circuit design, a timing path generally refers to the complete route for data to flow from one storage element (such as a trigger or register) to another storage element. These paths include not only the storage elements themselves, but also logic gates, circuit interconnections, and possible buffers. The timing paths mentioned in the embodiments of the present application mainly refer to the timing paths between latches.

[0090] First, the technical problem of timing error that the present application specifically aims to solve is analyzed and proposed. In the prior art, asynchronous circuits have different implementation structures, among which the Click structure is one of the asynchronous controller structures. The structure has the following features: for example, it can be implemented by standard cells, and can be independent of the process library; and it can be recognized by EDA tools, and has a high degree of fit with the synchronous design process. It does not require full custom design like other asynchronous handshake structures, or the introduction of new design languages ​​and EDA tools. These features have led to a lot of research based on the Click structure, and there have been attempts to propose new design processes for converting synchronous circuits to asynchronous circuits. It not only retains the characteristics of asynchronous circuits, but also can quickly convert synchronous circuits. However, these current works focus on the control path, and the design paths are all designed based on registers. Compared with other asynchronous controllers, the current work based on the Click control structure abandons the performance and area advantages of the combination of asynchronous circuits and latches, and there is less optimization work on the data path. In common asynchronous circuit design, registers are usually used in combination with asynchronous circuits. Since latches have a smaller area and lower power consumption, latches can be used as storage units instead of registers in the embodiments of the present application. However, since they do not have the characteristic of unified control by a global clock, the asynchronous circuit needs to rely on an asynchronous handshake template to control the data flow. The use of latches requires more sophisticated timing control than other triggers, which increases the complexity of relying on asynchronous handshake templates, which may cause timing errors, but cannot quickly locate the path of timing errors, and the method for timing adjustment is too complicated. The following three problems still exist in the current technology:

[0091] Problem 1: Wrong number of clock cycles caused by wrong capture clock position in the timing path.

[0092] In an asynchronous circuit implemented by a latch based on an asynchronous handshake template, if a latch is used as a timing unit of the circuit, a "timing error" phenomenon may occur, that is, an error may occur when the EDA tool performs timing analysis (including hold time and setup time analysis), which is reflected in the cycle number error in the timing analysis. Taking the setup time as an example, when a timing error occurs, the setup time analysis will have a cycle number error problem. Similarly, the hold time analysis is also wrong, which is also a cycle number error. Specifically, when the EDA tool analyzes the timing path, if a latch appears, it may cause it to use the wrong transmission clock and capture clock in the analysis, thus causing the timing confusion of the timing path. In order to deal with the timing error problem, asynchronous circuit design usually requires an asynchronous handshake template. However, the current asynchronous handshake template cannot completely solve the asynchronization problem caused by physical limitations (such as propagation delay); further, when multiple asynchronous handshake modules need to communicate with each other, the asynchronization problem may be further complicated, because each module has its own handshake template and timing constraints, and these constraints may be inconsistent between modules. Due to the lack of synchronization, critical data may be lost, resulting in erroneous calculation results. Frequent asynchrony may even lead to system performance degradation because more time is needed to correct these errors. When these problems are amplified in multi-level or multi-module asynchronous circuits, they will seriously affect the reliability and performance of the circuit. In summary, timing errors are a very serious problem in the asynchronous circuit design based on the asynchronous handshake template implemented by the latch. It not only affects the function of the same module, but may also have a cumulative effect in a larger system, resulting in global clock cycle errors and data inconsistency.

[0093] Problem 2: Unable to quickly locate the incorrect timing path.

[0094] In the asynchronous circuit design implemented by the latch based on the asynchronous handshake template, each different time point and source may have its own signal transmission characteristics and delays, which makes it complicated to diagnose and locate the specific fault path. This problem not only increases the difficulty of debugging and maintaining the circuit, but also increases the cost required to solve these problems. In asynchronous circuits, data is usually transmitted at multiple different time points and through multiple different paths, which leads to the need to check multiple paths and time points when timing errors occur. Compared with synchronous circuits, such an investigation and location process is more complicated and time-consuming. Exemplarily, solving this problem may require additional hardware support for problem tracking and diagnosis, such as adding more test points or using advanced signal analysis tools. In addition to the investment in hardware and human resources, the solution may also involve the adjustment of software and strategies; it may also be necessary to adopt a conservative strategy to handle all timing paths that may have problems, such as reducing the operating speed or adding additional fault tolerance mechanisms, which may have adverse effects on the performance and reliability of the circuit; and difficult to locate problems means that more time and resources will be used to diagnose and repair the problem, which further increases the overall maintenance cost of the system. In a complex system, a small timing error may trigger a series of other problems, and such a chain reaction may cause the entire system to become unstable. In summary, the inability to quickly locate the wrong timing path has led to multiple burdens in terms of cost, time, and resources.

[0095] Problem 3: Timing adjustments for asynchronous circuit designs are too complex

[0096] The methods for timing checking and timing adjustment in the prior art are mainly in synchronous circuit design. In synchronous circuit design, timing adjustment is mainly to constrain the paths in the same clock domain or between different clock domains, allowing designers to set the correct number of clock cycles for a specific signal path to complete data transmission or logical operations, which is very practical in synchronous circuits because all operations are designed around the same or a few clock signals. However, in asynchronous circuit design, the application scenarios and utility of timing adjustment in the prior art are subject to certain limitations; because the timing adjustment methods in synchronous circuits mainly rely on a unified clock signal, which does not exist in asynchronous circuits, asynchronous circuits cannot process pulse signals in asynchronous circuits; therefore, it is necessary to find alternative methods to handle the timing constraints of asynchronous paths. Specifically, the problem of multiple sources and multiple sinks cannot be solved. A circuit may have multiple data or signal sources, and these sources may be sent to multiple targets or sinks at different times and under different conditions. In this complex scenario, because it is no longer possible to use a common clock in the synchronous circuit to perform global timing constraints, multiple data or signal sources need to be analyzed and adjusted in detail, which increases more computing and hardware requirements, resulting in increased costs and decreased performance.

[0097] In order to solve the problem of timing errors in asynchronous circuits implemented by latches based on asynchronous handshake templates and achieve the goal of reducing waiting delays, considering the shortcomings of the prior art, the technical problems actually to be solved by the present application may include some or all of the following aspects:

[0098] Improve the overall stability of the system, quickly locate the path of timing errors based on timing checks, and reduce the complexity of timing adjustments for asynchronous circuits based on latches to solve the problem of timing errors caused by clock cycle errors. Specifically, the frequency of errors and the time overhead caused by timing errors can be significantly reduced, and fewer hardware resources can be used to handle timing errors, so that these resources can be used for other useful computing or data transmission tasks, improving resource utilization and thus improving performance.

[0099] In summary, the existing timing processing method cannot meet the actual speed and performance requirements in the asynchronous circuit design based on latch implementation, which seriously affects its execution efficiency and waiting time. Therefore, the timing processing method provided in the embodiment of the present application is used to solve some or all of the above technical problems to improve performance and reduce power consumption.

[0100] Based on the above, the present application embodiment provides a circuit design platform 10. Figure 1A , Figure 1AA schematic diagram of the structure of a circuit design platform provided in an embodiment of the present application, the circuit design platform 10 can be an integrated platform for designing circuits, illustratively, can be a personal computer (used to run various electronic design automation tools 101, such as Cadence, Synopsys, Altium Designer, KiCad, etc.), a workstation (used for more complex and computationally intensive circuit design tasks), a field programmable gate array board (Field-Programmable Gate Array, FPGA, used for circuit prototyping and testing), an application-specific integrated circuit (Application-Specific Integrated Circuit, ASIC), a cloud computing platform (used to provide a cloud version for the electronic design automation tool 101, allowing circuit design and simulation on a more powerful server), an embedded development board (used for design and testing of microcontroller circuits), an integrated development environment (Integrated Development Environment, IDE, for example, Keil, IAR, etc. for embedded system design), a network service (such as EasyEDA, an online electronic design automation tool 101), dedicated hardware (such as logic analyzers, oscilloscopes, etc., used for circuit testing and debugging), mobile phones and tablet computers (for example, including a simple mobile version of the electronic design automation tool 101) and other devices.

[0101] like Figure 1A As shown in , the circuit design platform 10 may include an electronic design automation tool 101 and a code tool 102, wherein the electronic design automation tool 101 is used to perform timing processing on the first asynchronous circuit 20-A, and the code tool 102 is used to perform detailed design on the first asynchronous circuit 20-A. Specifically,

[0102] Electronic design automation tool 101: After the circuit logic and physical design have been processed and verified, they can be converted into implementable hardware description language (HDL) code through code tool 102. Electronic design automation tool 101 can be specifically used to process unique design elements and structures in integrated circuits, such as different types of handshake protocols and signal control mechanisms. In an embodiment of the present application, the electronic design automation tool 101 can be used to perform timing analysis, timing processing and other operations on the first asynchronous circuit 20-A; for example, the electronic design automation tool 101 can be used to perform static timing analysis on the first asynchronous circuit 20-A (i.e., the electronic design automation tool 101 will automatically identify all timing paths and clock paths, perform delay calculations on the gate delay and interconnection delay of each path, and perform timing checks on each path to check for paths with timing errors, etc.) or dynamic timing analysis (i.e., define the initial conditions and trigger events of the simulation, simulate the behavior of the circuit under different input and working conditions, and collect and analyze simulation data to identify possible dynamic timing problems), and timing processing (i.e., by operating the timing analysis report tool in the electronic design automation tool 101, perform timing checks on the first asynchronous circuit 20-A, and mark timing paths with incorrect clock cycle numbers, or perform timing adjustments on timing paths with incorrect clock cycle numbers). The electronic design automation tool 101 can also perform logic synthesis to convert the HDL code into a netlist file (e.g., a gate-level netlist file).

[0103] Code tool 102: In the embodiment of the present application, it refers to a code tool that can be used to implement or design the first asynchronous circuit 20-A through code, for example, through Tcl script (Tool Command Language, Tcl script can be used to automate complex design processes, such as simulation, synthesis, layout and routing, etc., can be used to parse simulation results, extract key data and generate reports) or Verilog code (can support hardware descriptions at gate level, data flow level and behavioral level, allowing designers to design at different levels of abstraction, usually organized into modules, these modules can be reused and combined to build more complex circuits) to design the first asynchronous circuit 20-A, or through programming languages ​​such as matlab or python (for example, through regular matching to implement the function of replacing the target memory with a latch for the first asynchronous circuit 20-A, the regular matching refers to the technology of searching and matching strings through specific patterns, and encapsulating it into an automatically executed program to achieve the overall replacement or partial replacement of the first asynchronous circuit 20-A) to perform the replacement function to implement the first asynchronous circuit 20-A.

[0104] The first asynchronous circuit 20-A is an asynchronous circuit based on a latch, see Figure 1BThe first asynchronous circuit 20-A includes pipelines of different levels and pipeline circuits of different levels; each pipeline level is controlled by an independent pulse signal; the adjacent upper-level pipeline and the next-level pipeline include pipeline circuits of corresponding levels for connecting adjacent-level pipelines; each pipeline level includes one or more latches, and each pipeline circuit includes one or more timing paths; wherein, assuming that the first latch and the second latch are latches in the adjacent upper-level pipeline and the next-level pipeline, respectively, a timing path is formed between the first latch and the second latch. For controlling the pulse signal generated by the path, please refer to Figure 1C The first asynchronous circuit 20-B in the circuit is different from the synchronous circuit. The asynchronous circuit does not rely on the global clock, but is combined with an asynchronous handshake protocol (such as the Click handshake protocol), in which the structural unit responsible for handshake constitutes a control path, in which each control module is connected to perform handshake, and the pulse generated by each handshake is used as a local clock. For example, the first pulse signal is sent to the first-level pipeline and is set to be the first local clock, and so on; originally, each level is driven by a synchronous clock in the synchronous circuit, but now each level in the asynchronous circuit is driven by pulses of different levels, driving the latch in the data path to capture or release data, thereby realizing the asynchronous circuit design based on latches. The register is triggered at the edge of the clock and stores or releases data, and the data path based on the register also works according to this principle. The latch is high-level transparent and has a different storage method from the register. There are two different storage mechanisms for latches, (1) from rising edge to rising edge (that is, the same as the storage method of the register), and (2) from high-level conduction period to high-level conduction period. The difference between these two methods is that in (2), the latch performs timing borrowing (such as Figure 1H As shown). The latch-based data path can select between two modes in the synthesis stage. Different storage mechanisms can be selected when designing the data path according to power consumption and performance requirements. Traditional triggers need to act on every clock edge, even if there is no new data update, while latches with high-level transparency characteristics can work at any time during the high-level period. Since the timing unit in the first asynchronous circuit 20-A is a latch, and the latch has the characteristic of high-level transparency, both the transmitting clock and the capturing clock can be turned on during the high-level conduction period, which greatly improves the timing flexibility of the circuit. Therefore, due to its high-level transparency characteristics, the data throughput of the asynchronous circuit implemented based on the latch may be higher due to timing borrowing, and the timing is more flexible, which makes the latch-based asynchronous circuit more suitable for high-speed data processing application scenarios.

[0105] Understandably, Figure 1A or Figure 1BThe structure of the first asynchronous circuit 20-A is only some exemplary implementations provided in the embodiments of the present application. The structure of the first asynchronous circuit 20-A in the embodiments of the present application includes but is not limited to the above implementations.

[0106] It can also be understood that both the electronic design automation tool 101 and the code tool 102 can operate and design the first asynchronous circuit 20-A, and the embodiment of the present application does not specifically limit this. The structure illustrated in the embodiment of the present application does not constitute a specific limitation of the circuit design platform 10. In other embodiments of the present application, the circuit design platform 10 may include more or fewer components than shown in the figure, or combine certain components, or split certain components, or arrange the components differently. The illustrated components can be implemented in hardware, software, or a combination of software and hardware.

[0107] Combine the following Figure 1A-1B The structure of the first asynchronous circuit 20-A is shown, and the timing check, timing adjustment method and register-latch replacement method provided in the embodiment of the present application are specifically introduced. In the asynchronous circuit design method provided in the embodiment of the present application, it involves the circuit design platform 10 performing timing check on the asynchronous circuit based on latch implementation through the electronic design automation tool 101, quickly locating the wrong timing path, and the related process of timing adjustment for the above-mentioned wrong timing path. Furthermore, a replacement operation is performed on an existing asynchronous circuit implemented based on a target memory (e.g., a register) (e.g., replacing the target memory with a latch), and the latch-based asynchronous circuit can be implemented through a code tool 102 (e.g., a Python or matlab programming tool); when the electronic design automation tool 101 (e.g., an EDA tool) uses a predefined timing margin threshold as a screening parameter in a timing analysis instruction, a timing path that is not within the timing margin threshold range is screened out in a timing analysis report tool, a timing path with an erroneous number of clock cycles is determined, and the timing path is marked as a path with an erroneous timing; and then the electronic design automation tool 101 executes a timing processing instruction to adjust the capture clock of the second latch of the erroneous timing path to a clock position that matches the corresponding timing margin threshold range (i.e., the number of clock cycles in each erroneous timing path is adjusted to a predefined number of normal clock cycles).

[0108] The following describes how the circuit design platform 10 side uses the code tool 102 to replace the second asynchronous circuit implemented based on the target memory to implement the first asynchronous circuit 20-A; and how the electronic design automation tool 101 performs timing processing on the first asynchronous circuit 20-A, to specifically illustrate the timing processing method provided in this application.

[0109] (i) How the circuit design platform 10 performs a replacement operation on the asynchronous circuit implemented based on the target memory through the code tool 102 to implement the first asynchronous circuit 20-A.

[0110] In the embodiment of the present application, the following points will be used to exemplify how the circuit design platform 10 performs the replacement operation through the code tool 102: 1. After obtaining the first netlist file (for example, a gate-level netlist file) generated based on the first asynchronous circuit 20-A, the target memory in the target area to be replaced is identified through the area identification instruction. 2. After replacing the target memories in one or more target areas in the second asynchronous circuit 30-A with latches, the first asynchronous circuit 20-A is implemented, and a second netlist file is generated based on the first asynchronous circuit 20-A. Among them,

[0111] 1. After obtaining a first netlist file (eg, a gate-level netlist file) generated based on the first asynchronous circuit 20-A, a target memory in a target region to be replaced is identified through a region identification instruction.

[0112] Take code tool 102 as an example. Figure 1B-Figure 1E The identification of the target memory in the embodiment of the present application mainly includes the following process:

[0113] Exemplarily, on the circuit design platform 10 side, after the code tool 102 reads the first netlist file generated by the second asynchronous circuit 30-A, the code tool 102 receives a region identification instruction and can use a special parsing module, which can be used to determine how to identify and mark the target memory in the target area, first the location of the target area, then identify all target memories in the target area, and select an appropriate parsing algorithm (for example, by regular matching) to identify the identification information of these target memories and mark them.

[0114] 2. After the target memories in one or more target areas in the second asynchronous circuit 30-A are replaced with latches respectively, the first asynchronous circuit 20-A is implemented, and a second netlist file is generated according to the first asynchronous circuit 20-A.

[0115] Take code tool 102 as an example. Figure 1D-1F The identification of the target memory in the embodiment of the present application mainly includes the following process:

[0116] Exemplarily, the code tool 102 can analyze the device name and port information of the target memory based on the identification information of the first storage component in each identified target area, and then replace it with the device name and port information of the latch; and after the instantiation information of the target memory is also replaced with the instantiation information of the latch, the wiring information therein remains unchanged, and the replacement can be achieved without changing the wiring information, thereby realizing the operation of replacing the target memory with the latch; after the target memories in all target areas are replaced with latches, a series of static and dynamic tests are run to ensure that the replacement operation does not introduce new errors or inconsistencies. After all replacements and verifications are completed, a second netlist file containing an asynchronous circuit that has been replaced with a latch is exported using the code tool 102. In summary, the embodiment of the present application can use a latch to convert the data path without interfering with the control path, and realize the first asynchronous circuit 20-A on the basis of the second asynchronous circuit 30-A. In short, the latch has a level transparent characteristic, which will increase the risk of holding time violations. The latch can be driven by a short pulse to reduce the time of latch level transparency. There are two problems: 1. How to generate short pulses; 2. How to solve the timing of the latch. The first problem can be solved by using an asynchronous handshake structure, and the second problem can be solved by the timing processing method in the embodiment of the present application. Specifically, in the field of asynchronous circuits and synchronous circuits, attempts are being made to utilize the advantages of latches while reducing the impact of hold time violations caused by level transparency. For example, in the field of pulse latches, a dedicated pulse generation circuit ( Figure 1G As shown) to generate pulses to drive the latch. However, this may cause signal quality problems and timing analysis problems. If glitches occur due to the following structural violations, competition-hazard phenomena may occur, resulting in false triggering of the latch. The embodiment of the present application can solve two problems: (1) circuit conversion and (2) timing and EDA tool adaptation of asynchronous-latch design, combining an asynchronous circuit and a latch, and adapting the EDA tool to utilize the short pulses generated by the handshake signal, and further utilize the weak glitch characteristics and short pulse characteristics of the pulse generated by the handshake structure to give full play to the advantages of the latch.

[0117] (ii) How the circuit design platform 10 performs timing processing on the asynchronous circuit implemented based on the target memory through the electronic design automation tool 101.

[0118] In the embodiment of the present application, the following points will be used to exemplify how the circuit design platform 10 performs the replacement operation: 1. The circuit design platform 10 uses the electronic design automation tool 101 to screen out timing paths that are not within the timing margin threshold range in the timing analysis report tool based on the predefined timing margin threshold, thereby determining the timing path with an incorrect number of clock cycles and marking the timing path as a path with an incorrect timing. 2. Adjust the capture clock of the second latch of the incorrect timing path to a clock position that matches the corresponding timing margin threshold range (i.e., adjust the number of clock cycles in each incorrect timing path to a predefined number of normal clock cycles). Among them,

[0119] 1. The circuit design platform 10 uses the electronic design automation tool 101 to screen out timing paths that are not within the timing margin threshold range in the timing analysis report tool based on a predefined timing margin threshold, thereby determining a timing path with an incorrect number of clock cycles and marking the timing path as a path with an incorrect timing.

[0120] Taking Electronic Design Automation Tools 101 as an example, please refer to Figure 1B The identification of the target memory in the embodiment of the present application mainly includes the following process:

[0121] Exemplarily, the electronic design automation tool 101 opens the timing analysis report tool based on the first asynchronous circuit 20-A, and inputs the timing margin threshold range (for example, the boundary value of the timing margin threshold range is a predictable multiple of the clock period of the target pulse signal, the target pulse signal is the pulse signal of the pipeline stage to which the first latch in the corresponding timing path belongs, and the timing margin threshold can be pre-defined by the designer, and the threshold range can be that all timing margins correspond to the same common threshold range, or that the timing margin of each timing path corresponds to a threshold range respectively), thereby filtering out the timing paths whose timing margins are not within the timing margin threshold range; exemplarily, the timing margin threshold range can be pre-defined by the designer, and the ... " command and "-slack_lesser_than", "-slack_greater_than" options for checking, where the "report_timing" command and the "-slack_lesser_than" command are used to find the timing path whose timing margin is less than the corresponding timing margin threshold range, and the "report_timing" command and the "-slack_greater_than" command are used to find the timing path whose timing margin is greater than the corresponding timing margin threshold range (for example, the timing margin threshold is 4ns, and the instruction can be used to find the timing path whose timing margin change is greater than 4ns to quickly determine the wrong timing path). In addition, it can also be marked or recorded by any one or more of software labels, log files, database records, and graphical interface annotations to mark it as an erroneous timing path.

[0122] 2. Adjust the number of clock cycles in each erroneous timing path to a predefined number of normal clock cycles.

[0123] Taking Electronic Design Automation Tools 101 as an example, please refer to Figure 1B The identification of the target memory in the embodiment of the present application mainly includes the following process:

[0124] Exemplarily, the electronic design automation tool 101 can adjust the number of clock cycles for timing paths within different ranges through the "set_multicycle_path" instruction based on the erroneous timing path marked in the first asynchronous circuit 20-A; for example, a pulse signal can be used as a constraint to uniformly adjust the capture clocks of the second latches of all timing paths in the corresponding pipeline level of the erroneous timing path. Specifically, for example, the capture clock of the above-mentioned erroneous timing path can be adjusted to the correct clock position corresponding to the corresponding timing margin threshold through the "set_multicycle_path" instruction; the module can also be used as a constraint, with the first latch in the target erroneous timing path as the first module and the second latch as the second module, and the "set_multicycle_path" instruction is used to input the first module as the starting port and the second module as the destination port to adjust the erroneous timing path, and adjust the capture clock of the above-mentioned erroneous timing path to the correct clock position corresponding to the corresponding timing margin threshold; thereby, the adjustment of the number of clock cycles of the erroneous timing path is achieved, and the problem of timing errors is solved.

[0125] Based on the above Figure 1A-1F The structure of the asynchronous circuit design provided in the embodiment of the present application is combined with the timing check, timing adjustment and register-latch replacement method to specifically analyze and solve the technical problems raised in the present application.

[0126] See also Figure 2A , Figure 2A This is a flow chart of a method for processing a timing disorder problem provided by an embodiment of the present application. The method can be applied to the above Figure 1A-1F In the system architecture, the circuit design platform 10 and the first asynchronous circuit 20-A can be used to support and execute Figure 2A The method flow steps S101 to S103 shown in FIG. Figure 2A Described from the processor side, the method may include the following steps S101 to S103, and may optionally include steps S200 to S203.

[0127] Step S101: determining a timing margin threshold range corresponding to one or more timing paths in a first asynchronous circuit.

[0128] Exemplarily, the first asynchronous circuit is Figure 1A-1B Taking the first asynchronous circuit 20-A in FIG. 2 as an example, a timing margin threshold range corresponding to one or more timing paths in the first asynchronous circuit is determined.

[0129] Specifically, the timing margin threshold range can be pre-defined according to the circuit design requirements, or the electronic design automation tool 101 (such as an EDA tool) can be used to perform timing analysis on the first asynchronous circuit 20-A, and after analyzing the timing information of all timing paths (such as the timing path formed between two latches in two adjacent stages of the asynchronous circuit), the corresponding timing margin threshold range is defined according to the timing information of different timing paths; specifically, the EDA tool can perform timing analysis by simulating circuit behavior (i.e., obtaining timing parameters by simulating the actual operation of the circuit) or analyzing mathematical models (i.e., solving timing parameters based on mathematical models of circuit elements); through the above timing analysis, key timing parameters of each timing path can be obtained, such as setup time (Setup Time, i.e., the shortest time that must pass from the data being stable at the input end to the rising edge or falling edge of the clock end of the latch), hold time (Hold Time, i.e., the shortest time that the data needs to remain stable at the input end after the rising edge or falling edge of the clock end of the latch), and the number of clock cycles (Clock Period, the period of the clock signal used in the circuit), and timing margin (Slack, the difference between the required time and the arrival time); the electronic design automation tool 101 can extract the information of the above-mentioned first asynchronous circuit 20-A from the netlist file or the HDL (hardware description language) source code. After parsing this information, the electronic design automation tool 101 can automatically identify the timing information of all timing paths in the circuit, and can use this information to set the corresponding timing margin threshold range for each timing path.

[0130] In a possible implementation, one or more timing paths in the first asynchronous circuit 20-A correspond to the same timing margin threshold range; or, the one or more timing paths correspond to respective margin threshold ranges. Specifically, multiple timing paths may correspond to the same timing margin threshold range, that is, when performing timing adjustment, all timing paths may be processed uniformly, avoiding the tedious process of repeatedly inputting threshold ranges of different paths (for example, the timing margin thresholds corresponding to all latches in the same level of pipeline may be set to the same); optionally, one or more timing paths may also correspond to respective margin threshold ranges, that is, the margin standards of each path may be set according to its actual conditions, providing greater design freedom.

[0131] In a possible implementation, the boundary value of the timing margin threshold range is a predictable multiple of the clock cycle of the target pulse signal, and the target pulse signal is the pulse signal of the pipeline stage to which the first latch in the corresponding timing path belongs. For example, see Figure 3AA timing analysis schematic diagram based on a first asynchronous circuit is provided. Because the timing margin of some timing paths may be too large or too small, the timing check may not be able to directly check the timing margin of each timing path, and the timing confusion usually occurs after the first latch data of the timing path is calculated and before the second latch of the timing path successfully captures the clock. The embodiment of the present application sets the timing margin threshold range to a multiple of the clock period of the pulse signal corresponding to the first latch in the timing path, so that the timing margin and the timing margin threshold can be compared with the clock reference value of the same pulse signal, thereby improving the accuracy of finding the timing path with timing confusion.

[0132] Step S102: searching for an erroneous timing path in one or more timing paths through a timing analysis instruction.

[0133] Exemplarily, the first asynchronous circuit is Figure 1A-1B Taking the first asynchronous circuit 20-A in FIG. 1 as an example, the circuit design platform 10 executes a timing analysis instruction through the electronic design automation tool 101 to find an erroneous timing path.

[0134] Specifically, the embodiment of the present application describes a timing check method for an asynchronous circuit, which uses a timing analysis instruction to find an erroneous timing path in one or more timing paths; for example, see Figure 3A-3D The timing analysis example diagram based on the first asynchronous circuit 20-A shown in the figure can use the timing analysis report tool of the electronic design automation tool 101 (such as an EDA tool) to perform timing analysis on the first asynchronous circuit 20-A and compare the timing margin of the timing path with the corresponding timing margin threshold range. Since the first asynchronous circuit 20-A is implemented based on a latch, and the latch is triggered by an enable signal, such as a transparent latch, due to its high-level transparent characteristics, the transmission clock and the capture clock can be from the high-level conduction period to the high-level conduction period, instead of having to transmit the clock on the rising edge of the clock and capture the clock on the rising edge of the clock, so it may cause timing confusion when transmitting the clock, such as Figure 3B-Figure 3C As shown; in the embodiment of the present application, a timing check can be performed through a timing analysis instruction. For example, the timing analysis instruction can be a "report_timing" instruction and one or more of "-slack_lesser_than" and "-slack_greater_than" to cooperate to find out the wrong timing path; wherein the wrong timing path is a path in which the timing margin of the timing path exceeds the corresponding timing margin threshold range, the timing margin is the difference between the first duration and the second duration, the first duration is the duration between the emission clock of the first latch in the corresponding timing path to the capture clock of the second latch, and the second duration is the data calculation duration between the first latch and the second latch in the corresponding timing path.

[0135] In a possible implementation, a timing analysis instruction is run through a timing analysis report tool in an electronic design automation tool EDA, wherein the input parameters of the timing analysis instruction include a timing margin threshold range corresponding to the one or more timing paths; and an erroneous timing path whose timing margin exceeds the corresponding timing margin threshold range is output. Specifically, the timing margin threshold range (for example, the boundary value of the timing margin threshold range may be a multiple of the clock period of a target pulse signal, the target pulse signal is a pulse signal of a pipeline stage to which the first latch in the corresponding timing path belongs, and the timing margin threshold may be predefined by a designer) is used as a parameter for the timing analysis instruction screening for comparison; the TΔslack (i.e., the timing margin threshold range) may be input in the timing analysis report tool by using the "report_timing" instruction and "-slack_lesser_than", "-slack_greater_than" The values ​​are compared, where the "report_timing" instruction and "-slack_lesser_than" can be used to check the timing path whose timing margin is less than the threshold range, and the "report_timing" instruction and "-slack_greater_than" can be used to check the timing path whose timing margin is greater than the threshold range. The above-mentioned multiple timing analysis instructions can be used separately for comparison and screening, or together for comparison and screening, which is not specifically limited here; assuming that the timing margin of the first target timing path compared in the timing analysis report tool is 5ns, and If the timing margin threshold range TΔslack of the first target timing path is between 2ns and 4ns, then the timing margin of the first target timing path is not within the timing margin threshold range, and the target timing path is judged to have an error in the number of clock cycles, which is an error timing path. The error timing path can be screened out and output to the display interface of the timing analysis report tool; further, the first asynchronous circuit 20-A can be compared with the same preset timing margin threshold range or multiple preset timing margin threshold ranges; for example, for the comparison of the timing paths in the same level of the pipeline using the same timing margin threshold range, the comparison can be set. The timing margin threshold range of all timing paths in the first asynchronous circuit 20-A is unified to be between 2ns and 4ns. As long as the timing margin of a timing path exceeds the timing margin threshold range, the timing analysis report tool will determine that the timing path is an erroneous timing path and screen it out. By comparing multiple preset timing margin threshold ranges, the timing margin of each timing path can have a corresponding timing margin threshold range. For example, the timing margin threshold range corresponding to timing path A is between 2ns and 4ns, and the timing margin threshold range corresponding to timing path B is between 4ns and 7ns. No specific limitation is made in the embodiments of the present application.

[0136] In one possible implementation, the erroneous timing path is marked or recorded by any one or more of software tags, log files, database records, and graphical interface annotations. By specially marking the erroneous timing path, it is possible to quickly identify the erroneous timing path during timing processing to improve the speed of timing processing; for these erroneous timing paths that have been marked, in subsequent timing processing, on the one hand, by adding clear marks to the erroneous timing paths, the system can quickly locate and identify these paths in the data stream. This fast identification mechanism can reduce the time and computing resource consumption of searching for the source of the problem in a large data set, thereby increasing processing speed and efficiency; on the other hand, accurate marking not only speeds up the location of the problem, but the automated marking and recording mechanism reduces these potential risks and improves the accuracy and reliability of the system. In addition, all erroneous timing paths that are marked or recorded as erroneous timing paths can be stored in a list, which can be used as input for the next step of the timing adjustment process.

[0137] In a possible implementation, it is necessary to check the timing error problem. The current electronic design automation tool 101 cannot fully support latch-based design when performing timing analysis. One point is that the above-mentioned timing error phenomenon does not appear in the timing paths of all latches, but only in a part of the paths. It is necessary to perform a timing check to quickly locate the wrong timing path to facilitate subsequent processing. Since this timing error is reflected in the cycle number error, the timing margin (slack) of the wrong path will change, and the module with the timing error can be quickly located through the timing report + timing margin.

[0138] In the above example process, the circuit design platform 10 is described through the electronic design automation tool 101 as an example, and can be applied to other tools or software that can design integrated circuits, and is not specifically limited in the embodiments of the present application; in addition, after the above timing check is completed, the path marked as a timing error can be used in the timing adjustment method described below.

[0139] Step S103: adjusting the capture clock of the second latch of the error timing path to a clock position matching the corresponding timing margin threshold range through the timing processing instruction.

[0140] Exemplarily, the first asynchronous circuit is Figure 1A-1B Taking the first asynchronous circuit 20-A in the embodiment as an example, the timing adjustment method in the embodiment of the present application is described:

[0141] Specifically, in the embodiment of the present application, the error timing path is found by a special mark for the timing error timing path, and the timing margin in the error timing path is adjusted to the corresponding timing margin reference value by adjusting the number of clock cycles in the error timing path. After the error timing path is accurately marked and identified by the electronic design automation tool 101, the electronic design automation tool 101 will start and execute its adjustment strategy, aiming to adjust the number of clock cycles in the above-mentioned error timing path to the predefined correct number of clock cycles (that is, adjust the capture clock of the second latch of the error timing path to the clock position matching the corresponding timing margin threshold range). Exemplarily, in the embodiment of the present application, the module can be used as a constraint (that is, the module is set, and the target timing path is adjusted from the module level), and the timing processing instruction (for example, the "set_multicycle_path" instruction can be used to set the number of clock cycles of the target timing path) to adjust the number of clock cycles of the timing path with the timing error.

[0142] Using modules as constraints: For example, Figure 1B As shown in the first asynchronous circuit 20-A, it is assumed that there is a first-stage pipeline and a second-stage pipeline in the first asynchronous circuit 20-A, and both pipelines have one or more latches. The first-stage pipeline is connected to a latch FF2 in the second-stage pipeline through one of the latches FF1. The path connecting them is the timing path, which is the wrong timing path marked after the timing check; please refer to Figure 3B-Figure 3DIn the timing analysis diagram in FIG, the timing path requires 1 clock cycle from the emission clock to the capture clock, but due to a timing error caused by some reasons (for example, a timing error caused by replacing a register with a latch), the number of clock cycles from the emission clock to the capture clock of the timing path is now 0 clock cycles (that is, the clock is captured directly after the emission clock), thus causing a timing error. The number of clock cycles of the timing path can be adjusted by the "set_multicycle_path" instruction; illustratively, the timing processing instruction code for the erroneous timing path can be set_multicycle_path. le_path-from[get_registers{FF1}]-to[get_registers{FF2}]1, where -to is used to specify a specific timing path (i.e., the timing path between latch FF1 and latch FF2). The correct number of clock cycles predefined in the embodiment of the present application is 1. For example, the number of clock cycles can be set to 1 through the above code, and the capture clock of the erroneous timing path is thereby adjusted to the correct clock position corresponding to the corresponding timing margin threshold. The timing confusion problem of the erroneous timing path is solved through the specific operation of the above-mentioned timing processing instructions. It can be understood that in the embodiment of the present application, setting the value of the number of clock cycles in the target timing path to 1 through the timing adjustment instruction code is a possible implementation method. The number of clock cycles can also be set to other values, which is not specifically limited in the embodiment of the present application.

[0143] In one possible implementation, since the second latch in the error timing path belongs to the latch in the target level pipeline, the capture clock of all latches in the target level pipeline can be adjusted to a clock position that matches the corresponding timing margin threshold range through a timing processing instruction. The adjustment strategy of the electronic design automation tool 101 can adopt a variety of implementation forms to adapt to timing error timing paths of different types and characteristics. Exemplarily, in an embodiment of the present application, a pulse signal can be used as a constraint (i.e., an asynchronous control path generates different pulse signals, which are used as local clocks to drive different pipeline stages, and the instruction can use the clock as a constraint point, so a pulse signal can be used for constraint).

[0144] Taking pulse signals as constraints: For example, assume that the first asynchronous circuit 20-A includes a first-stage pipeline and a second-stage pipeline, both of which have one or more latches, and the first-stage pipeline is connected to the M latches in the second-stage pipeline through N latches therein (where N and M are both integers not less than 1), and the path connecting them is the timing path, and there are one or more erroneous timing paths marked after the timing check in the above timing paths; see Figure 3B-Figure 3DIn the timing analysis diagram in , the corresponding target level pipeline is found based on the second latch of the wrong timing path. The number of clock cycles corresponding to the threshold range of all timing margins in the target level pipeline is 1 (that is, the correct clock position of the capture clock of all latches should be the position where 1 clock cycle is located), but due to timing errors caused by some reasons (for example, after replacing the original target memory with a latch, the timing error caused by the different memory types), one or more timing paths in these timing paths now have a clock cycle of 0 cycle (that is, after the first latch of the timing path transmits the clock, the second latch of the timing path directly captures the clock), or these wrong timings The number of clock cycles of the path is 2 cycles, which causes timing errors in some timing paths. The capture clocks of all latches in the target level pipeline can be adjusted to the clock position that matches the corresponding timing margin threshold range through the timing processing instruction; specifically, the timing processing instruction can be a "set_multicycle_path" code instruction, through which the number of clock cycles controlling all timing paths in the pipeline of this level is uniformly adjusted (that is, the capture clocks of all latches in the target level pipeline are adjusted to the clock position that matches the corresponding timing margin threshold range); for example, assuming that the name of the pulse signal corresponding to the first-level pipeline is get_clocks click5_2, and the name of the pulse signal corresponding to the first-stage pipeline is get_clocks click5_3, and the timing adjustment can be performed through the following code: set_multicycle_path-setup-from[get_clocks click5_2]-to[get_clocks click5_3]1 (the timing adjustment instruction can set the number of clock cycles of all timing paths in the pipeline circuit of the corresponding level between the first-stage pipeline and the second-stage pipeline); wherein, -to is used to specify a specific timing path, and the correct number of clock cycles in the embodiment of the present application is 1. For example, the number of clock cycles can be set to 1 through the above code. Through the above timing processing instruction example operation, the capture clocks of all latches in the second-stage pipeline have been adjusted to the correct clock position corresponding to the corresponding timing margin threshold, solving the timing confusion problem of all timing paths in the second-stage pipeline. It can be understood that in the embodiment of the present application, setting the value of the number of clock cycles in the target timing path to 1 through the timing adjustment instruction code is a possible implementation method, and the number of clock cycles can also be set to other values, which is not specifically limited in the embodiment of the present application.

[0145] Optionally, before the above step S101 is performed, the following steps S200 to S203 may also be included:

[0146] Acquire a first netlist file of a second asynchronous circuit; the second asynchronous circuit includes M pipelines, wherein each pipeline is controlled by an independent pulse signal; each pipeline includes one or more target memories, each of which is edge-triggered, and a timing path is formed between two registers of two adjacent pipelines; receive a module recognition instruction to identify the target memory in the first netlist file; replace the N target memories in the first netlist file with the latches respectively to obtain the first asynchronous circuit, where N is an integer greater than or equal to 1; generate a second netlist file for designing the first asynchronous circuit.

[0147] Specifically, in the embodiment of the present application, a possible implementation method for implementing the first asynchronous circuit 20-A is provided, see Figure 1D-1F The second asynchronous circuit 30-A is an asynchronous circuit implemented based on a target memory (such as a register). The second asynchronous circuit 30-A includes an M-level pipeline, wherein each level of the pipeline is controlled by an independent pulse signal; each level of the pipeline includes one or more target memories, each of which is an edge-triggered memory, and a timing path is formed between the two target memories of two adjacent pipeline levels; the second asynchronous circuit 30-B is a detailed description of the control path and the data path of the first asynchronous circuit 20-A. The pulse signal generated by handshaking with each other through the asynchronous handshake protocol is used as a local clock to control the corresponding level of the pipeline or the target memory therein. Since the target memory is edge-triggered, the data path is transmitted from rising edge to rising edge (that is, from the rising edge of the clock to transmit the clock to the rising edge of another clock to capture the clock).

[0148] For example, see Figure 2B , Figure 2B This is a schematic diagram of a process for implementing asynchronous circuit design based on a latch in an embodiment of the present application. The allocation process may include the following steps S200 to S203.

[0149] Step S200: Obtain a first netlist file of a second asynchronous circuit.

[0150] The second asynchronous circuit includes M-level pipelines, wherein each level of the pipeline is controlled by an independent pulse signal; each level of the pipeline includes one or more target memories, each of the target memories is an edge-triggered memory, and a timing path is formed between two registers of two adjacent pipeline levels; a first netlist file is generated based on the second asynchronous circuit 30-A. Exemplarily, the first netlist file can be a SPICE netlist, Verilog code or output generated by other electronic design automation tools 101. The first netlist file can include basic component information (for example, logic gates, target memories, buffers and inverters, etc.), connection information (for example, port connection lines, input / output ports, timing paths), hierarchical structures and modules, etc. in the second asynchronous circuit 30-A.

[0151] Step S201: Receive a module identification instruction and identify a target memory in a first netlist file.

[0152] Based on the generation of the corresponding first netlist file (eg, gate-level netlist type file) from the second asynchronous circuit, the module receives instructions to identify one or more target memories that need to be replaced, thereby accurately determining which parts need to be converted.

[0153] In a possible implementation, the circuit design platform includes one or more programming tools such as Python and matlab; the module identification instruction is an instruction executed by one or more programming tools such as Python and matlab. Exemplarily, taking the code tool 102 as a Python tool, after receiving the module identification instruction, the data in the first netlist file can be read line by line based on the loop of this code by the code for line in netlist_data:if'DFF'in line:parse_flip_flop(line); for example, to find the area including the target memory, when the Python tool encounters a keyword such as 'DFF'in line when parsing line by line, the parse_flip_flop(line) function can be called to further parse the line of data, and the identification information of all the target memories in the target area to be replaced can be found, so that it can be clearly pointed out which target memories need to be replaced.

[0154] Step S202: Replace N target memories in the first netlist file with latches respectively to obtain a first asynchronous circuit.

[0155] By using the identification information of the above module identification instruction, each target memory to be replaced is replaced with a latch (for example, the identification information of the target memory can be replaced with the identification information of the latch), so that the asynchronous circuit based on the latch is realized through a simple replacement operation. In the prior art, the second asynchronous circuit based on the target memory is controlled by a clock signal, while the latch in the first asynchronous circuit in the embodiment of the present application is controlled by an enable signal, for example, it can work without a clock signal, and the latch only operates during the activation of the enable signal, and no additional power consumption is generated at other times, so the performance of the circuit can be improved, the power consumption can be reduced, and the circuit design can be simplified.

[0156] In a possible implementation, the N target memories are target memories distributed in one or more target areas in the second asynchronous circuit; the module identification instruction includes identification information of one or more target areas, and identification information of the N target memories. Taking the code tool 102 as a Python tool as an example, based on the above-mentioned module replacement instruction and the identification result, the module analysis and identification are performed on the found target memory, and the target memories of one or more target areas in the first netlist file are replaced with latches respectively. Specifically, it can be through the code: for component incircuit_components:if component.type=='DFF':(used to find a trigger with a type equal to the target memory), replace_with_latch(component) (used to define the scope of replacement), def replace_with_latch(component):component.type='Latch'(used to replace the target memory in the target area with a latch); specifically, the content of the replacement is mainly to replace the device name and port information of the target memory in one or more target areas with the device name and port information of the latch, so as to realize the operation of replacing the target memory with the latch. In addition, this replacement function can also be automatically completed through EDA tools or other custom scripts, or it can be achieved by manually editing the netlist file, which is not specifically limited in the embodiments of the present application.

[0157] Step S203: Generate a second netlist file for designing the first asynchronous circuit.

[0158] Based on the replacement results in one or more target areas, a second netlist file for designing an asynchronous circuit is generated. Exemplarily, it can be generated using an EDA tool, and the second netlist file will include all newly added latches and their corresponding connection information, thereby realizing the first asynchronous circuit 20-A based on latches, so that subsequent steps, such as timing check verification and simulation, can be more convenient. In addition, compared with the target memory in the second asynchronous circuit 30-A, the latch has lower power consumption and lower driving requirements, the non-combinatorial logic power consumption of the latch-based design is reduced, and the clock tree and its power consumption are smaller.

[0159] For example, Figure 2C-Figure 2D An overall design process is provided for the embodiment of the present application. The embodiment of the present application first synthesizes the asynchronous circuit design based on register implementation, executes the replacement program to realize the asynchronous circuit netlist based on latch, and then performs secondary synthesis on the netlist file, supplements the timing, and finally realizes the asynchronous circuit design based on latch. The embodiment of the present application proposes an asynchronous circuit implementation method based on latch design. At present, there are clear regulations and guidance for the hardware description language modeling of registers, but there is no clear method for the guidance and modeling method of latches. Therefore, the embodiment of the present application realizes the asynchronous circuit based on latch by gate-level netlist identification and replacement. The method can be implemented at different levels, which can be module level or design level. And it can be encapsulated into an automated program using regular matching of programming languages ​​to complete design-independent batch processing. Exemplarily, in the first asynchronous circuit 20-A, the handshake process is to ensure that data is correctly transmitted between different circuit components. Since the latch is combined, the process does not rely on the global clock, so very precise timing control is required to prevent false triggering. The handshake structure usually includes timing units. These timing units act as filters and can effectively filter out glitch signals caused by circuit noise or other non-ideal conditions, which greatly reduces the possibility of false triggering, thereby improving the reliability and stability of the circuit; and a local clock signal generated by the asynchronous handshake is also a stable short pulse signal, which can be used to control the latch. Since the short pulse signal is stable, it reduces clock jitter and phase error compared to the problems of the global clock signal in the synchronous circuit. Such a design not only reduces power consumption, but also improves timing accuracy. The energy efficiency is roughly calculated in the form of [power consumption / frequency]. The embodiment of the present application can bring a 15% power consumption benefit when the frequency is increased. Therefore, the first asynchronous circuit 20-A implemented by the replacement operation in the embodiment of the present application can be called a high-efficiency asynchronous circuit design method. Since the target memory is replaced by a latch, the number of clock cycles of some timing paths in the first asynchronous circuit 20-A may be wrong. For this problem, see Figure 2A The described embodiments address this.

[0160] In a possible implementation, the first asynchronous circuit 20-A in the embodiment of the present application can also be implemented by a pulse latch; further, for the pulse latch, its delay time is much shorter than that of the register, and because the latch is transparent, this design is not affected by clock offset and jitter to a certain extent, and the timing model of the pulse-triggered latch is simpler than that of the latch and is similar to a faster register, which makes the pulse latch an ideal timing unit for high-performance and low-power ASIC design and traditional high-performance microprocessor design. The circuit based on the pulse latch is usually a latch driven by a short clock pulse. This driving method has two types: implicit and explicit. The former combines the pulse generating module and the latch to encapsulate a pulse generating module and a latch into a new timing unit, and the latter generates a pulse to drive a certain number of latches within a certain range by a special circuit module. The similarity between this field and the embodiment of the present application is that the asynchronous circuit handshake module is similar to the special circuit that generates short pulses in the pulse latch circuit. The functions are both to generate short pulses, and the difference is that the triggering method of generating pulses is different. Secondly, in order to achieve the conversion from synchronous circuit to pulse latch-based circuit, it is usually achieved by replacing all (or part) of the timing units, thereby saving clock cycles and power consumption, which is similar to the technology of the present invention.

[0161] In another possible implementation, the first asynchronous circuit 20-A in the embodiment of the present application can also be implemented by a multi-phase latch; compared to a register, a latch has the characteristic of high-level conduction, which will cause a short path violation in the latch. Shortening the high-level conduction or driving with a multi-phase clock are both ways to alleviate this problem. The former derives the design direction of a pulse latch, and the latter derives the design of a two-phase or three-phase clock driven master and slave latch, and cooperates with the retiming method to optimize the circuit. The latch design based on a multi-phase clock can better play the characteristics of latch timing borrowing and further play the performance of the circuit. Usually, the latch design of multiple clocks also requires a process of converting from a synchronous circuit to a latch-based circuit, mapping a single register to a single or multiple latches, and moving the combinational logic back to different latches through a certain algorithm. This process is generally a targeted retiming for performance, power consumption or area.

[0162] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0163] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the order of the actions described, because according to the present application, some steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0164] In the several embodiments provided in the present application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only schematic, and the division of the above-mentioned units is exemplarily only a logical function division. There may be other division methods in actual implementation. Exemplarily, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0165] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0166] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0167] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server or a network device, etc., specifically a processor in a computer device) to perform all or part of the steps of the above-mentioned methods of each embodiment of the present application. Among them, the aforementioned storage medium may include: U disk, mobile hard disk, magnetic disk, optical disk, read-only memory (Read-Only Memory, abbreviated: ROM) or random access memory (Random Access Memory, abbreviated: RAM) and other media that can store program codes.

[0168] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A circuit design method, characterized in that: Applied to a first asynchronous circuit, the first asynchronous circuit includes M-level pipelines, where M is an integer greater than 1; wherein each level of the pipeline is controlled by an independent pulse signal, and each level of the pipeline includes one or more latches; wherein a timing path is formed between a first latch and a second latch, and the first latch and the second latch are latches in an adjacent upper-level pipeline and a next-level pipeline, respectively; the method includes: Determine a timing margin threshold range corresponding to one or more timing paths in the first asynchronous circuit; Through the timing analysis instruction, find an erroneous timing path in the one or more timing paths; wherein the erroneous timing path is a path whose timing margin exceeds the corresponding timing margin threshold range, and the timing margin is the difference between a first duration and a second duration, wherein the first duration is the duration between the emission clock of the first latch in the corresponding timing path and the capture clock of the second latch, and the second duration is the data calculation duration between the first latch and the second latch in the corresponding timing path; Through the timing processing instruction, the capture clock of the second latch of the erroneous timing path is adjusted to a clock position matching the corresponding timing margin threshold range.

2. The method according to claim 1, characterized in that The one or more timing paths correspond to the same timing margin threshold range; or, the one or more timing paths correspond to respective margin threshold ranges.

3. The method according to claim 1 or 2, characterized in that: The boundary value of the timing margin threshold range is a multiple of a clock period of a target pulse signal, and the target pulse signal is a pulse signal corresponding to the pipeline stage to which the first latch in the corresponding timing path belongs.

4. The method according to any one of claims 1 to 3, characterized in that The step of searching for an erroneous timing path in the one or more timing paths through a timing analysis instruction includes: Running a timing analysis instruction through a timing analysis report tool in an electronic design automation tool EDA, wherein an input parameter of the timing analysis instruction includes a timing margin threshold range corresponding to the one or more timing paths; The faulty timing paths whose output timing margin exceeds the corresponding timing margin threshold range.

5. The method according to any one of claims 1 to 4, characterized in that The method further comprises: The erroneous timing path is marked or recorded by any one or more of software tags, log files, database records, and graphical interface annotations.

6. The method according to any one of claims 1 to 5, characterized in that The second latch in the error timing path belongs to a latch in a target level pipeline; the capture clock of the second latch in the error timing path is adjusted to a clock position matching a corresponding timing margin threshold range through a timing processing instruction, comprising: Through the timing processing instruction, the capture clocks of all latches in the target level pipeline are adjusted to the clock position matching the corresponding timing margin threshold range.

7. The method according to any one of claims 1 to 6, characterized in that The method further comprises: Acquire a first netlist file of a second asynchronous circuit; the second asynchronous circuit comprises M-stage pipelines, wherein each stage of the pipeline is controlled by an independent pulse signal; each stage of the pipeline comprises one or more target memories, each of the target memories is an edge-triggered memory, and a timing path is formed between two target memories of two adjacent stages of the pipeline; receiving a module identification instruction to identify the target memory in the first netlist file; Replacing N target memories in the first netlist file with latches respectively to obtain the first asynchronous circuit, where N is an integer greater than or equal to 1; A second netlist file for designing the first asynchronous circuit is generated.

8. The method according to claim 7, characterized in that The N target memories are target memories distributed in one or more target areas in the second asynchronous circuit; the module identification instruction includes identification information of the one or more target areas and identification information of the N target memories.

9. The method according to claim 7 or 8, characterized in that: The step of replacing the N target memories in the first netlist file with latches respectively includes: The device names and port information of the N target memories are replaced with the device name and port information of the latch respectively.

10. The method according to any one of claims 7 to 9, characterized in that The module identification instruction is executed by one or more programming tools in Python or matlab.

11. The method according to any one of claims 7 to 10, characterized in that: The target memory is a register.

12. The method according to any one of claims 1 to 11, characterized in that The latch in the first asynchronous circuit is one or more of a transparent latch, a pulse latch and a multi-phase clock latch.

13. The method according to any one of claims 1 to 12, characterized in that The timing processing instruction is executed by a timing analysis report tool in an electronic design automation tool EDA.

14. The method according to any one of claims 1 to 13, characterized in that The first asynchronous circuit includes one or more control paths, and the pulse signal corresponding to each pipeline stage is controlled by an independent control path. Each pulse signal is generated by the corresponding control path after one or more asynchronous handshake protocol interactions.

15. The method according to claim 14, characterized in that The asynchronous handshake protocol includes the Click asynchronous handshake protocol.

16. A circuit design platform, characterized in that: The invention is applied to the design of a first asynchronous circuit; the first asynchronous circuit comprises M-level pipelines, where M is an integer greater than 1; each level of the pipeline is controlled by an independent pulse signal; each level of the pipeline comprises one or more latches, wherein a timing path is formed between a first latch and a second latch, and the first latch and the second latch are latches in the adjacent upper-level pipeline and next-level pipeline, respectively; the circuit design platform comprises; A determination module is configured to determine a timing margin threshold range corresponding to one or more timing paths in the first asynchronous circuit; A first identification module is configured to search for an erroneous timing path in the one or more timing paths through a timing analysis instruction; wherein the erroneous timing path is a path whose timing margin exceeds a corresponding timing margin threshold range, and the timing margin is a difference between a first duration and a second duration, wherein the first duration is a duration between a transmitting clock of the first latch in the corresponding timing path and a capturing clock of the second latch, and the second duration is a data calculation duration between the first latch and the second latch in the corresponding timing path; The timing processing module adjusts the capture clock of the second latch of the erroneous timing path to a clock position matching the corresponding timing margin threshold range through the timing processing instruction.

17. The circuit design platform according to claim 16, characterized in that: The one or more timing paths correspond to the same timing margin threshold range; or, the one or more timing paths correspond to respective margin threshold ranges.

18. The circuit design platform according to claim 16 or 17, characterized in that: The boundary value of the timing margin threshold range is a multiple of a clock period of a target pulse signal, and the target pulse signal is a pulse signal of a pipeline stage to which the first latch in a corresponding timing path belongs.

19. The circuit design platform according to any one of claims 16 to 18, characterized in that: The circuit design platform includes EDA; the first identification module is specifically used for: Running a timing analysis instruction through a timing analysis report tool in the EDA, wherein an input parameter of the timing analysis instruction includes a timing margin threshold range corresponding to the one or more timing paths; The faulty timing paths whose output timing margin exceeds the corresponding timing margin threshold range.

20. The circuit design platform according to any one of claims 16 to 19, characterized in that: The circuit design platform also includes: The marking module marks or records the error timing path based on the error timing path through any one or more of software tags, log files, database records, and graphical interface annotations.

21. The circuit design platform according to any one of claims 16 to 20, characterized in that: The second latch in the error timing path belongs to a latch in a target level pipeline; the timing processing module is specifically used for: Through the timing processing instruction, the capture clocks of all latches in the target level pipeline are adjusted to the clock position matching the corresponding timing margin threshold range.

22. The circuit design platform according to any one of claims 16 to 21, characterized in that: The circuit design platform also includes: an acquisition module, used for acquiring a first netlist file of a second asynchronous circuit; the second asynchronous circuit comprises M-stage pipelines, wherein each stage of the pipeline is controlled by an independent pulse signal; each stage of the pipeline comprises one or more target memories, each of the target memories is an edge-triggered memory, and a timing path is formed between two target memories of two adjacent stages of the pipeline; A second identification module, used for receiving a module identification instruction and identifying the target memory in the first netlist file; A replacement module, used for replacing N target memories in the first netlist file with the latches respectively to obtain the first asynchronous circuit, where N is an integer greater than or equal to 1; A generating module generates a second netlist file for designing the first asynchronous circuit.

23. The circuit design platform according to claim 22, characterized in that: The N target memories are target memories distributed in one or more target areas in the second asynchronous circuit; the module identification instruction includes identification information of the one or more target areas and identification information of the N target memories.

24. The circuit design platform according to claim 22 or 23, characterized in that: The replacement module is specifically used for: The device names and port information of the N target memories are replaced with the device name and port information of the latch respectively.

25. The circuit design platform according to any one of claims 22-24, characterized in that: The circuit design platform includes one or more programming tools in Python or matlab; the module identification instruction is an instruction executed by one or more programming tools in Python or matlab.

26. The circuit design platform according to any one of claims 22-25, characterized in that: The target memory is a register.

27. The circuit design platform according to any one of claims 16 to 26, characterized in that: The latch in the first asynchronous circuit is one or more of a transparent latch, a pulse latch and a multi-phase clock latch.

28. The circuit design platform according to any one of claims 16-27, characterized in that: The circuit design platform includes EDA; the timing processing instructions are instructions executed by a timing analysis report tool in the EDA.

29. The circuit design platform according to any one of claims 16-28, characterized in that: The first asynchronous circuit includes one or more control paths, and the pulse signal corresponding to each pipeline stage is controlled by an independent control path. Each pulse signal is generated by the corresponding control path after one or more asynchronous handshake protocol interactions.

30. The circuit design platform according to claim 29, characterized in that: The asynchronous handshake protocol includes the Click asynchronous handshake protocol.

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