Controllable code sending device for simulating track signal

Abstract

The invention relates to a controllable code sending device for simulating track signals, which comprises a processor, an FSK (Frequency Shift Keying) signal generation module and a signal amplification circuit which are connected in sequence, and also comprises a power amplifier board, a recovery circuit and a comparison circuit, and the input end of the power amplifier board is connected to the output end of the FSK signal generation module; the output end is connected to the input end of the recovery circuit and the input end of the comparison circuit, the output end of the recovery circuit is connected to the processor, the output end of the comparison circuit is connected to the FSK signal generation module, and the processor is further connected to the upper computer; and the power amplifier board collects the FSK signal output by the FSK signal generation module and forwards the FSK signal to the recovery circuit and the comparison circuit. Compared with the prior art, the system has the advantages that the stoping circuit and the comparison circuit are added, and the signals generated by the FSK signal generation module can be stoped, compared and shaped, so that the accuracy and reliability of the generated FSK signals are improved.

Description

Technical Field

[0001] The invention relates to a controllable code-generating device, in particular to a controllable code-generating device for simulating track signals. Background Art

[0002] According to the needs of railway transportation, in order to meet the requirements that locomotives can receive frequency-shifted locomotive signal information through tracks in stations, especially factories, mines and local railways also have intelligent control requirements for in-station electronic coding equipment. Owners are more inclined to use multi-information railway station electronic coding products with reasonable prices, stronger functions and higher reliability.

[0003] At present, frequency shift technology is used in railway section automatic blocking and locomotive coding in stations. It is an automatic control system based on frequency shift track circuits. The sending device sends low-frequency modulated frequency signals to the track, and the receiving device can demodulate the low-frequency information from the modulated carrier signal to automatically control the corresponding signal display and equipment, thereby realizing train speed supervision and control. There are two main types of frequency shift coding equipment used in China. The two types of frequency shift coding equipment are the same in principle, but there are great differences in equipment structure, application installation and debugging methods. One type of coding equipment has a high engineering cost and complex installation requirements; the other type of frequency shift coding equipment is realized by dividing the frequency through a discrete crystal oscillator through a digital logic chip, and faces the use of many types of crystal oscillators.

[0004] In order to solve the above problems, some existing technologies have adopted microelectronic solutions to realize frequency shift coding. For example, the digital frequency synthesizer (DDS) proposed in the related existing technologies is used to realize phase FSK modulation, but they often lack corresponding signal acquisition and comparison, resulting in unreliable generated FSK signals. Summary of the invention

[0005] The purpose of the present invention is to provide a controllable coding device for simulating track signals, which adds a sampling circuit and a comparison circuit, and can perform sampling and comparison shaping on the signal generated by the FSK signal generation module, thereby improving the accuracy and reliability of the generated FSK signal.

[0006] The purpose of the present invention can be achieved by the following technical solutions:

[0007] A controllable code-generating device for simulating track signals, comprising a processor, an FSK signal generating module and a signal amplifying circuit connected in sequence, the device also comprising a power amplifier board, a sampling circuit and a comparison circuit, the input end of the power amplifier board is connected to the output end of the FSK signal generating module, the output end is respectively connected to the input end of the sampling circuit and the comparison circuit, the output end of the sampling circuit is connected to the processor, the output end of the comparison circuit is connected to the FSK signal generating module, and the processor is also connected to a host computer;

[0008] The power amplifier board collects the FSK signal output by the FSK signal generation module and forwards it to the acquisition circuit and the comparison circuit.

[0009] The recovery circuit includes a recovery voltage divider circuit, a recovery follower, a first recovery diode and a second recovery diode. One end of the recovery voltage divider circuit is connected to the output end of the power amplifier board, the anode of the first recovery diode and the cathode of the second recovery diode. The other end of the recovery voltage divider circuit is grounded, the voltage divider output end is connected to the input end of the recovery follower, the output end of the recovery follower is connected to the processor, the cathode of the first recovery diode is connected to the positive pole of the first DC power supply, and the anode of the second recovery diode is grounded.

[0010] The recovery voltage divider circuit is obtained by connecting two fixed resistors with equal resistance in series.

[0011] The comparison circuit includes a first comparison voltage divider circuit, a zero-crossing signal generating module, a shaping comparator and a first amplification module, wherein the input end of the first comparison voltage divider circuit is connected to the output end of the power amplifier board, and the output end is connected to the inverting input end of the shaping comparator, the zero-crossing signal generating module is connected to the non-phase input end of the shaping comparator, the shaping comparator is connected to the input end of the first amplification module, and the output end of the first amplification module is connected to the FSK signal generating module.

[0012] The first comparison voltage-dividing circuit is obtained by connecting two fixed resistors in series.

[0013] The zero-crossing signal generating module includes a first zero-crossing voltage-dividing resistor and a second zero-crossing voltage-dividing resistor, one end of the first zero-crossing voltage-dividing resistor is connected to the positive electrode of the second DC power supply, and the other end is connected to one end of the second zero-crossing voltage-dividing resistor and the non-phase input end of the shaping comparator, the other end of the second zero-crossing voltage-dividing resistor is grounded, and the resistance value of the first zero-crossing voltage-dividing resistor is 10 times or more of the resistance value of the second zero-crossing voltage-dividing resistor.

[0014] The FSK signal generation module comprises:

[0015] A DDS module, connected to the processor, for outputting a controllable 2FSK weak signal;

[0016] The CPLD module is connected to the processor, the DDS module and the comparison circuit, and is used for receiving the output of the comparison circuit and obtaining the carrier frequency and the low-frequency signal.

[0017] There are two processors in total.

[0018] The signal amplifying circuit comprises a voltage amplifying circuit and a current amplifying circuit. The input end of the voltage amplifying circuit is connected to the output end of the FSK signal generating module, and the output end is connected to the input end of the current amplifying circuit.

[0019] A filter capacitor is provided in the current amplifying circuit.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] 1. The sampling circuit and comparison circuit are added to sample and compare the signal generated by the FSK signal generation module, thereby improving the accuracy and reliability of the generated FSK signal.

[0022] 2. The voltage divider circuit and follower are used to realize the recovery function, which has better maintainability and scalability. The subsequent replacement of some original parts will not cause overall changes. In addition, the two recovery diodes can filter out signals within the specified range.

[0023] 3. The voltage divider circuit is obtained by connecting two fixed resistors of equal resistance in series, which can halve the amplitude of the signal input to the follower, thus balancing accuracy and power consumption.

[0024] 4. The comparison circuit also reduces the amplitude through the first comparison voltage divider circuit to balance accuracy and power consumption.

[0025] 5. The zero-crossing signal generation module is composed of two resistors with greatly different resistance values, which improves the stability of the zero-crossing signal and also improves the durability.

[0026] 6. The DDS module can generate a controllable 2FSK weak signal, which can be used after amplification. The input of the sampling circuit and the comparison circuit uses this controllable 2FSK weak signal to reduce power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a structural schematic diagram of the application system of the present invention;

[0028] Figure 2 A schematic diagram of data interaction between the device of the present invention and a host computer;

[0029] Figure 3 It is a schematic diagram of the composition of the device of the present invention;

[0030] Figure 4 is a schematic diagram of a comparison circuit;

[0031] Figure 5 It is a schematic diagram of the recovery circuit;

[0032] Figure 6 is a schematic diagram of a voltage amplifier circuit;

[0033] Figure 7 is a schematic diagram of a current amplifier circuit;

[0034] Wherein: 1. host computer, 2. data transmission device, 3. controllable coding device, 4. power supply interface, 5. I / 0 coding selection interface, 6. first DC conversion circuit, 7. second DC conversion circuit, 8. third DC conversion circuit, 21. CAN bus, 31. processor, 32. CPLD module, 33. four-way FSK selection output device, 34. signal amplification circuit, 35. sampling circuit, 36. comparison circuit, 37. voltage detection circuit, 38. watchdog, 39. power amplifier re-detection interface of power amplifier board, 310. DDS module. DETAILED DESCRIPTION

[0035] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. This embodiment is implemented based on the technical solution of the present invention, and provides a detailed implementation method and specific operation process, but the protection scope of the present invention is not limited to the following embodiments.

[0036] A controllable coding device for simulating track signals, such as Figure 3 As shown, it includes a processor 31, an FSK signal generating module and a signal amplifying circuit 34 connected in sequence, and the device also includes a power amplifier board, a sampling circuit 35 and a comparison circuit 36. The input end of the power amplifier board is connected to the output end of the FSK signal generating module, and the output end is respectively connected to the input end of the sampling circuit 35 and the comparison circuit 36. The output end of the sampling circuit 35 is connected to the processor 31, and the output end of the comparison circuit 36 ​​is connected to the FSK signal generating module. The processor 31 is also connected to the host computer; the power amplifier board collects the FSK signal output by the FSK signal generating module and forwards it to the sampling circuit 35 and the comparison circuit 36. It has an output sampling function, and the voltage information, carrier frequency information and low frequency information of the output 2FSK signal are sampled and processed;

[0037] The addition of the sampling circuit 35 and the comparison circuit 36 ​​can perform sampling and comparison shaping on the signal generated by the FSK signal generation module, thereby improving the accuracy and reliability of the generated FSK signal.

[0038] In certain embodiments, such as Figure 3 As shown, there are two processors 31, which are capable of receiving and processing data respectively through dual-channel CPUs, verifying each other, and jointly outputting, thereby improving reliability.

[0039] like Figure 1As shown, when the device of the present application is used, it is connected to the host computer 1 through the controllable code sending device 3 through the data transmission device 2. The data transmission device 2 adopts a USB to CAN interface, specifically including a USB cable, a USB to CAN circuit and a CAN bus 21. The processor 31 has the function of receiving data on the CAN bus and the function of receiving coded signals at the IO port. In some embodiments, it also has a dual CPU verification inconsistency alarm function and converts the sampled data into a signal for uploading, and has the functions of sampled data processing, carrier frequency and low frequency over-limit alarm.

[0040] The function of the upper computer is to send configuration information (including carrier frequency, low frequency, offset frequency and signal duration, etc.) to the controllable coding device 3 through the data transmission device 2, send power adjustment to the controllable coding device 3, and receive heartbeat information, alarm information and configuration information sent by the controllable coding device 3.

[0041] Here’s how this application works:

[0042] like Figure 2 As shown in the figure, the data interaction diagram between the PC control terminal and the controllable code sending unit is as follows:

[0043] After the controllable coding device 3 is powered on, the system parameters and external interfaces are initialized first, and the CAN communication handshake signal is obtained regularly. When the host computer 1 sends the coding signal through the CAN bus, the controllable coding device 3 updates the coding information in time and replies that the configuration is successful. The processor 31 cooperates with the instructions of the host computer 1 to adjust the FSK signal output according to the strength of the signal sent by the controllable coding device 3. If the controllable coding device 3 is successfully configured, it will also reply to the host computer 1 that the configuration is successful. The host computer 1 can query the operating status, configuration data and alarm information of the controllable coding device 3 as needed.

[0044] The controllable coding device 3FSK output method is that the CPU sends a carrier frequency control signal to the DDS module 310 and sends a low-frequency control signal to the CPLD module 32 according to the received coding information. The CPU controls one of the four channels of the DDS module 310 as an output, and the weak FSK signal is amplified by the signal amplifier circuit 34 and output externally.

[0045] The dual processors 31 of the controllable code-generating device 3 receive exactly the same data, perform calculations and processing respectively, and send the processing results to each other through the internal SPI interface, and jointly output information after verifying the consistency.

[0046] The controllable code sending device 3 regularly collects the FSK signal output by the power amplifier to determine whether its voltage value, carrier frequency and low frequency are beyond the normal range, otherwise it outputs an alarm message. The controllable code sending unit regularly sends a heartbeat signal to the outside for external perception of its operation.

[0047] In certain embodiments, such as Figure 5As shown, the recovery circuit 35 includes a recovery voltage divider circuit, a recovery follower U1, a first recovery diode D2 and a second recovery diode D3, one end of the recovery voltage divider circuit is connected to the output end of the power amplifier board, the anode of the first recovery diode D2 and the cathode of the second recovery diode D3, the other end of the recovery voltage divider circuit is grounded, the voltage divider output end is connected to the input end of the recovery follower U1, the output end of the recovery follower U1 is connected to the processor 31, the cathode of the first recovery diode D2 is connected to the positive electrode of the first DC power supply, and the anode of the second recovery diode D3 is grounded. Figure 3 As shown, the recovery voltage divider circuit is connected to the power amplifier board through the power amplifier return detection interface 39 connected to the power amplifier board. Generally speaking, the first DC power supply is a 5V DC power supply. The recovery signal provided by the power amplifier return detection interface 39 is reduced in amplitude by the voltage divider circuit and enters the recovery follower U1. The voltage divider circuit and follower U1 are used to realize the recovery function, which has better maintainability and scalability. Subsequent replacement of less than part of the original parts will not cause overall changes. In addition, the two recovery diodes can filter out signals within a specified range. The recovery voltage divider circuit is obtained by connecting two fixed resistors with equal resistance in series. The two resistors are R142 and R144 respectively. In this embodiment, the recovery voltage divider circuit is obtained by connecting two fixed resistors with equal resistance in series, both of which are 10KΩ, which can halve the amplitude of the signal input to the follower, thereby balancing accuracy and power consumption.

[0048] like Figure 4 As shown, the comparison circuit 36 ​​includes a first comparison voltage-dividing circuit, a zero-crossing signal generating module, a shaping comparator U29 and a first amplifying module, the input end of the first comparison voltage-dividing circuit is connected to the output end of the power amplifier board, the output end is connected to the inverting input end of the shaping comparator U29, the zero-crossing signal generating module is connected to the non-inverting input end of the shaping comparator U29, the output end of the shaping comparator U29 is connected to the input end of the first amplifying module, and the output end of the first amplifying module is connected to the FSK signal generating module. In this embodiment, the first comparison voltage-dividing circuit is obtained by connecting two fixed resistors in series, namely R141 and R143, and the resistance values ​​of the two may be slightly different.

[0049] In this embodiment, the zero-crossing signal generating module includes a first zero-crossing voltage-dividing resistor R133 and a second zero-crossing voltage-dividing resistor R136, one end of the first zero-crossing voltage-dividing resistor R133 is connected to the positive electrode of the second DC power supply, and the other end is connected to one end of the second zero-crossing voltage-dividing resistor R133 and the positive phase input terminal of the shaping comparator U29, the other end of the second zero-crossing voltage-dividing resistor R133 is grounded, and the resistance value of the first zero-crossing voltage-dividing resistor R133 is 10 times or more of the resistance value of the second zero-crossing voltage-dividing resistor R133. Thus, the input voltage of the positive phase input terminal of the shaping comparator U29 can be a voltage value slightly greater than 0.

[0050] The output of the shaping comparator U29 is a square wave model, and the first amplification module is implemented using a triode.

[0051] like Figure 3 As shown, the FSK signal generation module includes:

[0052] A DDS module, connected to the processor 31, for outputting a controllable 2FSK weak signal;

[0053] The CPLD module 31 is connected to the processor 31, the DDS module and the comparison circuit 36, and is used to receive the output of the comparison circuit 36 ​​to obtain the carrier frequency and the low-frequency signal.

[0054] The signal amplifying circuit 34 includes a voltage amplifying circuit and a current amplifying circuit. The input end of the voltage amplifying circuit is connected to the output end of the FSK signal generating module, and the output end is connected to the input end of the current amplifying circuit.

[0055] Voltage amplifier circuit such as Figure 6 As shown, the voltage amplifier circuit uses a two-stage operational amplifier for amplification, and the current amplifier circuit is as follows Figure 7 As shown, it realizes current amplification through inductor L4 and inductor L5, and capacitor 49, and is equipped with three filter capacitors, which are Figure 7 C52, C53 and C54.

[0056] If the above functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc., which can store program code.

Claims

1. A controllable code generating device for simulating track signals, comprising a processor, an FSK signal generating module and a signal amplifying circuit connected in sequence, characterized in that: The device also includes a power amplifier board, a sampling circuit and a comparison circuit. The input end of the power amplifier board is connected to the output end of the FSK signal generation module, and the output end is respectively connected to the input end of the sampling circuit and the comparison circuit. The output end of the sampling circuit is connected to the processor, and the output end of the comparison circuit is connected to the FSK signal generation module. The processor is also connected to the host computer; The power amplifier board collects the FSK signal output by the FSK signal generation module and forwards it to the acquisition circuit and the comparison circuit.

2. A controllable coding device for simulating track signals according to claim 1, characterized in that: The recovery circuit includes a recovery voltage divider circuit, a recovery follower, a first recovery diode and a second recovery diode. One end of the recovery voltage divider circuit is connected to the output end of the power amplifier board, the anode of the first recovery diode and the cathode of the second recovery diode. The other end of the recovery voltage divider circuit is grounded, the voltage divider output end is connected to the input end of the recovery follower, the output end of the recovery follower is connected to the processor, the cathode of the first recovery diode is connected to the positive pole of the first DC power supply, and the anode of the second recovery diode is grounded.

3. A controllable coding device for simulating track signals according to claim 2, characterized in that: The recovery voltage divider circuit is obtained by connecting two fixed resistors with equal resistance in series.

4. A controllable coding device for simulating track signals according to claim 1, characterized in that: The comparison circuit includes a first comparison voltage divider circuit, a zero-crossing signal generating module, a shaping comparator and a first amplification module, wherein the input end of the first comparison voltage divider circuit is connected to the output end of the power amplifier board, and the output end is connected to the inverting input end of the shaping comparator, the zero-crossing signal generating module is connected to the non-phase input end of the shaping comparator, the shaping comparator is connected to the input end of the first amplification module, and the output end of the first amplification module is connected to the FSK signal generating module.

5. A controllable coding device for simulating track signals according to claim 4, characterized in that: The first comparison voltage-dividing circuit is obtained by connecting two fixed resistors in series.

6. A controllable coding device for simulating track signals according to claim 4, characterized in that: The zero-crossing signal generating module includes a first zero-crossing voltage-dividing resistor and a second zero-crossing voltage-dividing resistor, one end of the first zero-crossing voltage-dividing resistor is connected to the positive electrode of the second DC power supply, and the other end is connected to one end of the second zero-crossing voltage-dividing resistor and the non-phase input end of the shaping comparator, the other end of the second zero-crossing voltage-dividing resistor is grounded, and the resistance value of the first zero-crossing voltage-dividing resistor is 10 times or more of the resistance value of the second zero-crossing voltage-dividing resistor.

7. The controllable coding device for simulating track signals according to claim 1, characterized in that: The FSK signal generation module comprises: A DDS module, connected to the processor, for outputting a controllable 2FSK weak signal; The CPLD module is connected to the processor, the DDS module and the comparison circuit, and is used for receiving the output of the comparison circuit and obtaining the carrier frequency and the low-frequency signal.

8. The controllable coding device for simulating track signals according to claim 1, characterized in that: There are two processors in total.

9. The controllable coding device for simulating track signals according to claim 1, characterized in that: The signal amplifying circuit comprises a voltage amplifying circuit and a current amplifying circuit. The input end of the voltage amplifying circuit is connected to the output end of the FSK signal generating module, and the output end is connected to the input end of the current amplifying circuit.

10. A controllable coding device for simulating track signals according to claim 9, characterized in that: A filter capacitor is provided in the current amplifying circuit.

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