Wide-area super-multistable memristor chaotic circuit system

Abstract

The invention, which belongs to the technical field of circuit design, discloses a wide-area super-multistable memristor chaotic circuit system comprising a memristor, a capacitor and an inductor. An equivalent circuit of the chaotic circuit system comprises a memristor circuit, a resistance network, a voltage conveyor, an anti-phase proportioner, an anti-phase proportion adder, an anti-phase integrator, a multiplier, an external inductor and a capacitor. The voltage conveyor is used for conveying a voltage value to isolate current transmission; the anti-phase proportioner is used for realizing proportional operation of the output voltage and the input voltage and enabling the polarities of the output voltage and the input voltage to be opposite; the anti-phase proportion adder is used for realizing additive operation of a plurality of input voltages, so that the sum is used as an output voltage and is in an anti-phase state; the anti-phase integrator is used for realizing integral operation on an input voltage signal; and the multiplier is used for realizing product operation of two input signals.

Description

Technical Field

[0001] The invention belongs to the technical field of circuit design, and in particular relates to a wide-area super-multistable memristor chaotic circuit system. Background Art

[0002] Since memristors are nonlinear devices, they are convenient for constructing chaotic circuit systems. In recent years, the design of super-multistable chaotic systems based on memristors has become one of the hot research directions of memristor research. As one of the most representative chaotic circuits, the Chua circuit has become a paradigm for theoretical and experimental research on chaos. On this basis, memristors are used to construct deformed Chua circuits, multi-scroll Chua circuits, etc., and many novel dynamic behaviors have been discovered. In recent years, multistable states and super-multistable states have become research hotspots in chaos-related fields. Multistable states refer to the situation that when the system parameters remain unchanged and the initial conditions are changed, the system presents different stable states such as point attractors, periods, quasi-periods, chaos, and hyperchaos. In particular, when there are infinite attractors coexisting in the system, the system is called a super-multistable state. If the system has multistable states or super-multistable states, its dynamic behavior is in a specific parameter set, and the state switches frequently with the change of the initial value, and the system exhibits extremely rich and complex dynamic behaviors. However, the systems constructed in the existing research all exhibit super-multistability under a specific set of parameters, and there is a lack of research on super-multistability within a wide range of parameters. To this end, the present invention constructs a memristive chaotic system that exhibits super-multistability within a wide range of multiple parameters.

[0003] The present invention proposes a wide-area super-multistable memristor chaotic circuit system, which is a unique feature that general super-multistable systems do not have. It has rich dynamic behaviors and certain cutting-edge characteristics, and is worthy of in-depth study. This research will lay the necessary foundation for further exploring the super-multistable operation mechanism of the memristor chaotic circuit system, promoting the commercial production of memristor devices, and its application in brain-like intelligence. At the same time, when each parameter in the designed memristor chaotic circuit system parameter set takes a value in a large range, the system exhibits super-multistable states as the initial value changes, that is, the system has wide-area super-multistability. The extremely rich dynamic behavior of the system will provide basic support for the engineering application and development of chaotic circuits and memristors. Therefore, the wide-area super-multistable memristor chaotic circuit system proposed by the present invention and its realization from the circuit is a very valuable and meaningful work. Summary of the invention

[0004] In view of the above technical problems existing in the prior art, the present invention proposes a wide-area super-multistable memristor chaotic circuit system, which has a reasonable design, solves the shortcomings of the prior art and has good effects.

[0005] In order to achieve the above object, the present invention adopts the following technical solution:

[0006] A wide-area super-multistable memristor chaotic circuit system, the chaotic circuit system is composed of a memristor, a capacitor and an inductor, and the equivalent circuit of the chaotic circuit system includes a memristor circuit, a resistor network, a voltage conveyor, an inverting proportional device, an inverting proportional adder, an inverting integrator, a multiplier, an external inductor and a capacitor;

[0007] The voltage transmitter is used to transmit voltage value and isolate current transmission, which is realized by operational amplifier U1;

[0008] The inverting proportional device is used to realize the proportional operation of the output voltage and the input voltage and make the polarities of the two opposite, and includes a first inverting proportional device U2 and a second inverting proportional device U5;

[0009] The inverting proportional adder is used to implement the addition operation of multiple input voltages so that their sum is used as the output voltage and is in antiphase, including an inverting proportional adder U4;

[0010] The inverting integrator is used to implement the integration operation of the input voltage signal, including an inverting integrator U3;

[0011] The multiplier is used to implement the product operation of two input signals, including a first multiplier M1, a second multiplier M2 and a third multiplier M3;

[0012] The external inductor and capacitor include capacitors C1, C2 and inductor L.

[0013] Furthermore, the chaotic circuit system expression is:

[0014]

[0015] Among them, x and y are state variables transformed from the voltage of capacitors C1 and C2, z and w are state variables transformed from the current of inductor L and the conductance of memristor, α, β, γ are system parameters related to capacitance and inductance values, K, D, E, F are parameters of memristor, and τ represents time.

[0016] Furthermore, the first multiplier M1, the second multiplier M2 and the third multiplier M3 all use AD633JN chips;

[0017] The X pin and the Y pin of the first multiplier M1 are commonly connected to the first end of the capacitor C0, the output end of the inverting integrator U3 and the Y pin of the third multiplier M3, and the output end of the first multiplier M1 is connected to the first end of the resistor R1; the X pin of the third multiplier M3 is connected to the first end of the resistor R8, the X pin and the Y pin of the second multiplier M2, and the negative input end and the output end of the operational amplifier U1, and the output end of the third multiplier M3 is connected to the first end of the resistor R4; the output end of the second multiplier M2 is connected to the first end of the resistor R3.

[0018] Furthermore, the operational amplifier U1 adopts an AD633JN chip, the positive input end of the operational amplifier U1 is connected to the first end of the resistor R13, the first end of the capacitor C1 and the first end of the inductor L, the second end of the inductor L is connected to the first end of the capacitor C2, and the second end of the capacitor C2 and the second end of the capacitor C1 are grounded together.

[0019] Furthermore, the first inverting proportional device U2 and the second inverting proportional device U5 both use OP07CP chips;

[0020] The positive input terminal of the first inverting proportional device U2 is grounded, the negative input terminal is connected to the second end of the resistor R1 and the first end of the resistor R2, and the output terminal of U2 is connected to the second end of the resistor R2 and the first end of the resistor R7; the positive input terminal of the second inverting proportional device U5 is grounded, the negative input terminal is connected to the first end of the resistor R9 and the first end of the resistor R10, and the output terminal of U5 is connected to the second end of the resistor R10 and the second end of the resistor R13.

[0021] Furthermore, the inverting proportional adder U4 adopts an OP07CP chip; the positive input terminal of the inverting proportional adder U4 is grounded, the negative input terminal is connected to the second end of the resistor R4, the second end of the resistor R8, and the first end of the resistor R5, and the output terminal of U4 is connected to the second end of the resistor R5 and the second end of the resistor R9.

[0022] Furthermore, the inverting integrator U3 adopts an OP07CP chip; the positive input terminal of the inverting integrator U3 is grounded, and the negative input terminal is connected to the second end of the capacitor C0, the second end of the resistor R7, the second end of the resistor R3, and the first end of the resistor R6; the second end of the resistor R6 is connected to the positive electrode of the power supply V1, and the negative electrode of V1 is grounded.

[0023] The beneficial technical effects brought by the present invention are:

[0024] The present invention designs a wide-area super-multistable memristor chaotic circuit system, and implements the physical realization of the circuit. The circuit exhibits super-multistable state with the change of initial conditions in a specific parameter set. When the parameter set limits a parameter change, the system still has super-multistable state when the parameter takes any specific value within a larger range. At the same time, when multiple parameters take specific parameters within a larger range, the system still has super-multistable state. This provides flexible parameter selection for the application of the system in engineering technology, and the appropriate initial conditions can be selected as needed, and the required dynamic characteristics can be used to perform control operations to achieve engineering purposes. At the same time, the present invention also provides a research idea for determining the completely different performance of the system. Through the analysis and research of the system, the necessary research carrier will be provided for the complex characteristic performance of the neural network system, and the core support will be provided for revealing the internal mechanism of the complex dynamics of the determination system. Compared with the super-multistable chaotic circuit implementation method, the method used in the present invention uses fewer multipliers and operational amplifier devices, has lower cost, and the boundary between the memristor and the external device is clear, which is more convenient to add or reduce external devices to reconstruct the memristor super-multistable chaotic circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The present invention will be further described below in conjunction with the accompanying drawings:

[0026] Figure 1 It is a structural diagram of the wide-area ultra-multi-stable-state memristor chaotic circuit system in the present invention;

[0027] Figure 2 This is a simulation circuit diagram of a memristor in the present invention;

[0028] Figure 3 A volt-ampere hysteresis curve diagram of a memristor simulation circuit in the present invention;

[0029] Figure 4 The volt-ampere hysteresis curve diagram of the memristor simulation circuit in the present invention when the AC power frequency is 200 Hz and the amplitudes are 4 V, 5 V, and 6 V respectively;

[0030] Figure 5 It is an equivalent circuit diagram of the wide-area super-multistable memristor chaotic circuit system in the present invention;

[0031] Figure 6 When the parameters are α=7, β=6, γ=1, D=1.4, E=0.6, F=-0.2, K=-2, the phase trajectory diagram of the system in the xy plane changes with the initial component x(0);

[0032] Among them, (a) is the arc attractor under eight initial values; (b) is the 7-shaped attractor under eight initial values; (c) is the s-shaped attractor under four initial values ​​and the trapezoidal attractor under eight initial values; (d) is the linear attractor under four initial values;

[0033] Figure 7 The circuit simulation result diagram is when the parameters are α=7, β=6, γ=1, D=1.4, E=0.6, F=-0.2, K=-2;

[0034] Among them, (a) is the circuit simulation result corresponding to the initial component x(0) of 10; (b) is the circuit simulation result corresponding to the initial component x(0) of -5; (c) is the circuit simulation result corresponding to the initial component x(0) of -2.7; (d) is the circuit simulation result corresponding to the initial component x(0) of 5.85;

[0035] Figure 8 Phase trajectory diagram of the system in the xy plane obtained with the change of initial component x(0) when parameters α=500, β=5, γ=0.5, D=1.4, E=0.6, F=-0.2, K=-0.02;

[0036] Fig. 9 The circuit simulation results are as follows: α = 500, β = 5, γ = 0.5, D = 1.4, E = 0.6, F = -0.2, K = -0.02;

[0037] Among them, (a) is the circuit simulation result corresponding to the initial component x(0) of 0.03; (b) is the circuit simulation result corresponding to the initial component x(0) of 0.17;

[0038] Fig.10 The circuit simulation results corresponding to the parameters α = 500, β = 5, γ = 0.5, D = 1.4, E = 0.6, F = -0.2, K = -0.02, and the initial component x(0) is 0.05, 0.08, and 0.68 respectively; DETAILED DESCRIPTION

[0039] The present invention proposes a wide-area super-multistable memristor chaotic circuit system. In order to make the advantages and technical solutions of the present invention clearer and more specific, the present invention is described in detail below in conjunction with specific embodiments.

[0040] A wide-area super-multistable memristor chaotic circuit system, such as Figure 1 As shown in the figure, the memristor chaotic circuit system consists of a memristor, two capacitors and an inductor. The expression of the memristor is:

[0041]

[0042] in, is the conductance of the memristor, v is the voltage of the memristor, D, E, F, K are constant coefficients, and I is the current of the memristor.

[0043] The expression of memristor chaotic circuit system is:

[0044]

[0045] Where, v1 is the voltage of the memristor, which is also the voltage of capacitor C1, v2 is the voltage of capacitor C2, and i L is the current of the inductor L, and also the current of the capacitor C2, is the conductance of the memristor, D, E, F, K are constant coefficients, C1, C2, L are the values ​​of capacitance C1, C2 and inductance L respectively.

[0046] Furthermore, the system expression can be transformed into:

[0047]

[0048] Among them, x and y are state variables transformed from the voltage of capacitors C1 and C2, z and w are state variables transformed from the current of inductor L and the conductance of memristor, α, β, γ are system parameters related to capacitance and inductance values, K, D, E, F are parameters of memristor, and τ represents time.

[0049] In order to speed up the circuit simulation, time transformation is introduced here, that is, τ = ηt, where η is the time scale transformation factor. Generally speaking, the larger the η value, the faster the time domain evolution of the system, the denser the chaotic motion trajectory, and the more convenient it is to quickly obtain the circuit simulation results. Appropriate adjustment of the η value can reduce the resistance value of the integrated circuit and facilitate circuit debugging. Let η = 1000, and substitute τ = 1000t into formula (3) to obtain:

[0050]

[0051] According to formula 4, the equivalent circuit of the system is designed as follows: Figure 5 As shown, the equivalent circuit of the chaotic circuit system includes a resistor network, a voltage conveyor, an inverting proportional device, an inverting proportional adder, an inverting integrator, a multiplier, and external inductors and capacitors;

[0052] Voltage transmitter, used to transmit voltage value and isolate current transmission, realized by operational amplifier U1;

[0053] An inverting proportional device, used to realize the proportional operation of the output voltage and the input voltage and make the polarities of the two opposite, including a first inverting proportional device U2 and a second inverting proportional device U5;

[0054] An inverting proportional adder, used to implement the addition operation of multiple input voltages, so that the sum of them is used as the output voltage and is inverted, including an inverting proportional adder U4;

[0055] An inverting integrator, used to implement an integration operation on an input voltage signal, including an inverting integrator U3;

[0056] A multiplier, used to implement a product operation of two input signals, comprising a first multiplier M1, a second multiplier M2 and a third multiplier M3;

[0057] The external capacitor and inductor are used to connect with the memristor circuit to form a chaotic circuit system, including capacitors C1, C2 and inductor L.

[0058] The first multiplier M1, the second multiplier M2 and the third multiplier M3 all use AD633JN chips;

[0059] The X pin and the Y pin of the first multiplier M1 are commonly connected to the first end of the capacitor C0, the output end of the inverting integrator U3 and the Y pin of the third multiplier M3, and the output end of the first multiplier M1 is connected to the first end of the resistor R1; the X pin of the third multiplier M3 is connected to the first end of the resistor R8, the X pin and the Y pin of the second multiplier M2, and the negative input end and the output end of the operational amplifier U1, and the output end of the third multiplier M3 is connected to the first end of the resistor R4; the output end of the second multiplier M2 is connected to the first end of the resistor R3.

[0060] The operational amplifier U1 adopts the AD633JN chip. The positive input terminal of the operational amplifier U1 is connected to the first end of the resistor R13, the first end of the capacitor C1 and the first end of the inductor L. The second end of the inductor L is connected to the first end of the capacitor C2. The second end of the capacitor C2 and the second end of the capacitor C1 are grounded together.

[0061] The positive input terminal of the first inverting proportional device U2 is grounded, the negative input terminal is connected to the second end of the resistor R1 and the first end of the resistor R2, and the output terminal of U2 is connected to the second end of the resistor R2 and the first end of the resistor R7; the positive input terminal of the second inverting proportional device U5 is grounded, the negative input terminal is connected to the first end of the resistor R9 and the first end of the resistor R10, and the output terminal of U5 is connected to the second end of the resistor R10 and the second end of the resistor R13.

[0062] The inverting proportional adder U4 adopts the OP07CP chip; the positive input terminal of the inverting proportional adder U4 is grounded, the negative input terminal is connected to the second end of the resistor R4, the second end of the resistor R8, and the first end of the resistor R5, and the output terminal of U4 is connected to the second end of the resistor R5 and the second end of the resistor R9.

[0063] The inverting integrator U3 adopts the OP07CP chip; the positive input terminal of the inverting integrator U3 is grounded, and the negative input terminal is connected to the second end of the capacitor C0, the second end of the resistor R7, the second end of the resistor R3, and the first end of the resistor R6; the second end of the resistor R6 is connected to the positive electrode of the power supply V1, and the negative electrode of V1 is grounded.

[0064] The inverting proportional adder U4 is used to implement the addition operation of multiple input voltages, so that the sum is used as the output voltage and is inverted. The negative input terminal is connected to the output terminal of the third multiplier M3 through the resistor R4, and the negative input terminal is also connected to the output terminal of the operational amplifier U1 through R8. The output voltage of the output terminal of the third multiplier M3 is defined as wx, and the output voltage of the output terminal of the operational amplifier U1 is defined as x. Then the output voltage of the output terminal of the inverting proportional adder U4 is:

[0065]

[0066] The operational amplifier U1 is used to transmit voltage values ​​to isolate current transmission. The positive input terminal is connected to the output terminal of the second inverting proportional device U5 through the resistor R13, and is connected to the first terminal of the capacitor C1 and the first terminal of the inductor L. The voltage at the node between the input terminal of the operational amplifier U1 and the resistor R13 is defined as x, and the output voltage of the output terminal of the operational amplifier U1 is:

[0067] v o1 =x; (6)

[0068] The first inverting proportional device U2 is used to realize that the output voltage is proportional to the input voltage and is inversely proportional. The positive input terminal of the first inverting proportional device U2 is grounded, the negative input terminal is connected to the output terminal of the first multiplier M1 through the resistor R1 and is connected to its own output terminal through the resistor R2, and the output terminal is connected to the negative input terminal of the inverting integrator U3 through the resistor R7. Then, the output voltage of the output terminal of the first inverting proportional device U2 is:

[0069] v o2 =-w 2 ; (7)

[0070] The second inverting proportional device U5 is configured to realize that the output voltage is in a proportional operation relationship with the input voltage and is in an inverted phase, the positive input terminal is grounded, the negative input terminal is connected to the output terminal of the inverting proportional adder U4 through the resistor R9 and is connected to its own output terminal through the resistor R10, the output terminal is connected to the positive input terminal of the operational amplifier U1 through the resistor R13 and is connected to the first terminal of the capacitor C1 and the first terminal of the inductor L through the resistor R13, then the output voltage of the output terminal of the first inverting proportional device U9 is:

[0071]

[0072] The X pin and the Y pin of the first multiplier M1 are both connected to the output end of the inverting integrator U3. The output end of the first multiplier M1 is connected to the negative input end of the first inverting proportional device U2 through the resistor R1. The output voltage of the inverting integrator is defined as w, and the voltage of the output pin of the first multiplier M1 is:

[0073] v M1 =w2 ; (9)

[0074] The X pin and the Y pin of the second multiplier M2 are both connected to the output end of the operational amplifier U1, and the output end of the second multiplier M2 is connected to the negative input end of the inverting integrator U3 through the resistor R3, then the voltage of the output pin of the second multiplier M2 is:

[0075] v M2 =x 2 ; (10)

[0076] The X pin of the third multiplier M3 is connected to the output end of the operational amplifier U1, the Y pin of the third multiplier M3 is connected to the output end of the inverting integrator U3, and the output end of the third multiplier M3 is connected to the negative input end of the inverting proportional adder U4 through the resistor R4, then the voltage of the output pin of the third multiplier M3 is:

[0077] v M3 =wx; (11)

[0078] The positive input terminal of the inverting integrator U3 is grounded, the negative input terminal is connected to the DC power supply V1 through the resistor R6, the negative input terminal is also connected to the output terminal of the first inverting proportional device U2 through the resistor R7, the negative input terminal is also connected to the output terminal of the second multiplier M2 through the resistor R3, the negative input terminal is also connected to its own output terminal through the capacitor C, the output terminal is connected to the X pin and the Y pin of the first multiplier M1, and the output terminal is also connected to the Y pin of the third multiplier M3. The following relationship can be obtained from the inverting integrator U3:

[0079]

[0080] Then the expression of the memristor equivalent circuit is:

[0081]

[0082] The equivalent simulation circuit structure of the memristor is as follows Figure 2 As shown in Figure 1, by connecting an AC power source v = Asin(2πft) to the outside and setting different amplitudes and frequencies, the characteristics of the memristor can be verified. The circuit simulation results of the memristor under the stimulation of an AC voltage signal are shown in Figure 1. Figure 3 , Figure 4 shown. Figure 3 The volt-ampere hysteresis curves are shown in Figure 1 when the AC power amplitude A is 5V and the frequencies f are 200Hz, 400Hz, and 1000Hz respectively. It can be seen that the area of ​​the hysteresis curve gradually decreases as the power frequency increases. Figure 4 The volt-ampere hysteresis curves are shown when the AC power frequency is fixed at 200Hz and the amplitude A is 4V, 5V, and 6V respectively. It can be seen that the area of ​​the hysteresis curve gradually increases with the increase of the power amplitude. The designed memristor simulator conforms to the characteristics of the memristor.

[0083] Capacitors C1, C2 and inductor L are connected to the outside of the memristor equivalent simulation circuit to form a super-multistable memristor chaotic circuit system. Its equivalent circuit is as follows: Figure 5 shown.

[0084] In summary, the equivalent circuit expression of the wide-area super-multistable memristor chaotic system is:

[0085]

[0086] A large number of numerical simulation results show that the system has frequent trajectory switching under different parameter sets as the initial conditions change, showing super-multistable phenomena. Some trajectory phase diagrams are shown in Figure 6-Figure 10 When the parameters are α=7、β=6、γ=1、D=1.4、E=0.6、F=-0.2、K=-2, some numerical simulation diagrams of the system as the initial conditions change ( Figure 6 ) and circuit simulation diagram ( Figure 7 ). When the parameters α=500, β=5, γ=0.5, D=1.4, E=0.6, F=-0.2, K=-0.02, some numerical simulation diagrams of the system obtained as the initial conditions change ( Figure 8 ) and circuit simulation diagram ( Fig. 9 , Fig.10 ).

[0087] In order to obtain the component parameters of the system equivalent circuit, the system parameters are first substituted into the system after time scale transformation, that is, formula (4), and then the coefficients of formula (4) are compared with the coefficients of formula (14) to obtain the component parameters of the equivalent circuit. When the memristor chaotic circuit system is α = 7, β = 6, γ = 1, D = 1.4, E = 0.6, F = -0.2, K = -2, the equivalent circuit of the corresponding system is C1 = 142.857μF, C2 = 166.667μF, L = 1mH, R13 = 1Ω, and other device parameters are as follows Figure 2 As shown, the circuit simulation results under different initial conditions are as follows Figure 7 As shown, the circuit simulation results are consistent with the Matlab numerical simulation results (see Figure 6 ). When the memristor chaotic circuit system is α=500, β=5, γ=0.5, D=1.4, E=0.6, F=-0.2, K=-0.02, the equivalent circuit of the corresponding system is C1=2μF, C2=200μF, L=2mH, R13=100Ω, and other device parameters and Figure 2 The parameter values ​​shown are the same. At this time, the circuit simulation results under different initial conditions are as follows Fig. 9 and Fig.10 As shown, the circuit simulation results are consistent with the Matlab numerical simulation results (see Figure 8). A large number of experiments have found that when a parameter set is selected and a parameter is changed, within a specific range, the system has super-multi-stable states. The above-mentioned phase diagram of the xy plane under different initial conditions for only two sets of parameters is consistent with the circuit simulation, which shows the correctness of the circuit designed by the present invention.

[0088] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by technicians in this technical field within the essential scope of the present invention should also fall within the protection scope of the present invention.

Claims

1. A wide-area super-multistable memristor chaotic circuit system, characterized in that: The chaotic circuit system is composed of a memristor, a capacitor and an inductor, and the equivalent circuit of the chaotic circuit system includes a memristor circuit, a resistor network, a voltage conveyor, an inverting proportional device, an inverting proportional adder, an inverting integrator, a multiplier, an external inductor and a capacitor; The voltage transmitter is used to transmit voltage value and isolate current transmission, which is realized by operational amplifier U1; The inverting proportional device is used to realize the proportional operation of the output voltage and the input voltage and make the polarities of the two opposite, and includes a first inverting proportional device U2 and a second inverting proportional device U5; The inverting proportional adder is used to implement the addition operation of multiple input voltages so that their sum is used as the output voltage and is in antiphase, including an inverting proportional adder U4; The inverting integrator is used to implement the integration operation of the input voltage signal, including an inverting integrator U3; The multiplier is used to implement the product operation of two input signals, including a first multiplier M1, a second multiplier M2 and a third multiplier M3; The external inductor and capacitor include capacitors C1, C2 and inductor L.

2. The wide-area super-multistable memristor chaotic circuit system according to claim 1, characterized in that: The chaotic circuit system expression is: Among them, x and y are state variables transformed from the voltage of capacitors C1 and C2, z and w are state variables transformed from the current of inductor L and the conductance of memristor, α, β, γ are system parameters related to capacitance and inductance values, K, D, E, F are parameters of memristor, and τ represents time.

3. The wide-area super-multistable memristor chaotic circuit system according to claim 1, characterized in that: The first multiplier M1, the second multiplier M2 and the third multiplier M3 all use AD633JN chips; The X pin and the Y pin of the first multiplier M1 are commonly connected to the first end of the capacitor C0, the output end of the inverting integrator U3 and the Y pin of the third multiplier M3, and the output end of the first multiplier M1 is connected to the first end of the resistor R1; the X pin of the third multiplier M3 is connected to the first end of the resistor R8, the X pin and the Y pin of the second multiplier M2, and the negative input end and the output end of the operational amplifier U1, and the output end of the third multiplier M3 is connected to the first end of the resistor R4; the output end of the second multiplier M2 is connected to the first end of the resistor R3.

4. The wide-area super-multistable memristor chaotic circuit system according to claim 3, characterized in that: The operational amplifier U1 adopts an AD633JN chip, the positive input end of the operational amplifier U1 is connected to the first end of the resistor R13, the first end of the capacitor C1 and the first end of the inductor L, the second end of the inductor L is connected to the first end of the capacitor C2, and the second end of the capacitor C2 and the second end of the capacitor C1 are grounded together.

5. The wide-area super-multistable memristor chaotic circuit system according to claim 4, characterized in that: The first inverting proportional device U2 and the second inverting proportional device U5 both use OP07CP chips; The positive input terminal of the first inverting proportional device U2 is grounded, the negative input terminal is connected to the second end of the resistor R1 and the first end of the resistor R2, and the output terminal of U2 is connected to the second end of the resistor R2 and the first end of the resistor R7; the positive input terminal of the second inverting proportional device U5 is grounded, the negative input terminal is connected to the first end of the resistor R9 and the first end of the resistor R10, and the output terminal of U5 is connected to the second end of the resistor R10 and the second end of the resistor R13.

6. The wide-area super-multistable memristor chaotic circuit system according to claim 5, characterized in that: The inverting proportional adder U4 adopts an OP07CP chip; the positive input end of the inverting proportional adder U4 is grounded, the negative input end is connected to the second end of the resistor R4, the second end of the resistor R8, and the first end of the resistor R5, and the output end of U4 is connected to the second end of the resistor R5 and the second end of the resistor R9.

7. The wide-area super-multistable memristor chaotic circuit system according to claim 6, characterized in that: The inverting integrator U3 adopts an OP07CP chip; the positive input terminal of the inverting integrator U3 is grounded, and the negative input terminal is connected to the second end of the capacitor C0, the second end of the resistor R7, the second end of the resistor R3, and the first end of the resistor R6; the second end of the resistor R6 is connected to the positive electrode of the power supply V1, and the negative electrode of V1 is grounded.

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