Nanosecond narrow pulse circuit capable of programmably adjusting pulse width and laser

Abstract

The nanosecond narrow pulse circuit comprises a nanosecond narrow pulse signal generation circuit and a signal driving enhancement circuit, an external trigger signal respectively passes through a first buffer and a second buffer of the nanosecond narrow pulse signal generation circuit to obtain two paths of same signals, a second resistor of the second RC time delay circuit is a digital potentiometer, the pulse width of signals can be set by changing the resistance value of the digital potentiometer, narrow pulse signals are obtained after two paths of same signals pass through a first AND gate, and narrow pulse signals with opposite phases and high driving capacity are obtained after the narrow pulse signals are input into a gate driving chip. And when the signal output by the gate driving chip is low level, the bias voltage, the current-limiting resistor and the light emitting diode form a current loop through the gate driving chip, and the light emitting diode is excited to emit light. The technical problems that an existing scheme for achieving a second narrow pulse laser is high in cost, difficult to be suitable for batch production and low in reliability are solved.

Description

Technical Field

[0001] The invention relates to the technical field of electronic circuits, and in particular to a nanosecond narrow pulse circuit and a laser capable of adjusting pulse width programmably. Background Art

[0002] The existing methods for realizing nanosecond narrow pulse lasers are as follows:

[0003] 1. RF solution: A high-speed trigger combined with a low-noise amplifier and a RF amplifier is used to amplify the narrow pulse signal, so that the narrow pulse signal has driving capability. This solution uses a high-speed trigger, a low-noise amplifier and a RF amplifier, so the cost is high, and the RF amplifier also needs to be configured with a suitable bias. During mass production, the bias is less consistent, and to achieve the best effect, each needs to be debugged, which is inefficient.

[0004] 2. GaN solution: GaN has a faster switching speed, but it is easily affected by parasitic inductance during the switching process, oscillates during switching, and the consistency of parasitic parameters is difficult to control. The performance of products from different batches is difficult to control consistently. In addition, GaN has a low switching threshold, is easily interfered with, and has low reliability.

[0005] 3. Dedicated narrow pulse driver chip solution: Dedicated narrow pulse driver chips are expensive, and the trigger signal interface uses LVDS, ECL, etc., which is not convenient for low-cost configuration.

[0006] Therefore, how to solve the technical problems of high cost, difficulty in mass production and low reliability in the existing solutions for realizing second narrow pulse lasers is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0007] The invention provides a nanosecond narrow pulse circuit with programmable pulse width adjustment, which is used to solve the technical problems of high cost, difficulty in mass production and low reliability in existing solutions for realizing nanosecond narrow pulse lasers.

[0008] In view of this, the first aspect of the present invention provides a nanosecond narrow pulse circuit with programmable pulse width, comprising a nanosecond narrow pulse signal generating circuit and a signal driving enhancement circuit;

[0009] The nanosecond narrow pulse signal generating circuit comprises a first buffer, a second buffer, a first RC delay circuit, a second RC delay circuit and a first AND gate;

[0010] The signal driving enhancement circuit includes a gate driving chip, a light emitting diode and a current limiting resistor;

[0011] The input end of the first buffer and the input end of the second buffer are connected in parallel and receive the same external trigger signal together, the output end of the first buffer is connected to one end of the first resistor of the first RC delay circuit, the other end of the first resistor is respectively connected to the first input end of the first AND gate and one end of the first capacitor of the first RC delay circuit, the other end of the first capacitor is grounded, the output end of the second buffer is connected to one end of the second resistor of the second RC delay circuit, the other end of the second resistor is respectively connected to the second input end of the first AND gate and one end of the second capacitor of the second RC delay circuit, the other end of the second capacitor is grounded with the first capacitor, and the output end of the first AND gate is connected to the input end of the gate drive chip;

[0012] The high level output pin of the gate drive chip is connected to the cathode of the light emitting diode, the anode of the light emitting diode is connected to one end of the current limiting resistor, the other end of the current limiting resistor is connected to the bias voltage source, and the low level output pin of the gate drive chip is connected to the cathode of the light emitting diode;

[0013] The second resistor is a digital potentiometer.

[0014] Optionally, the gate driving chip includes a third buffer, an inverter, a second AND gate, a PMOS tube and an NMOS tube;

[0015] The input end of the third buffer is connected to the IN+ pin, the output end of the third buffer is connected to the first input end of the second AND gate, the input end of the inverter is connected to the IN- pin, the output end of the inverter is connected to the second input end of the second AND gate, the output end of the second AND gate is respectively connected to the gate of the PMOS tube and the gate of the NMOS tube, the source of the PMOS tube is connected to the VDD pin, the drain of the PMOS tube is connected to the high level output pin, the drain of the NMOS tube is connected to the low level output pin, and the source of the NMOS tube is connected to the GND pin.

[0016] Optionally, an external trigger signal generator is also included;

[0017] The signal output terminal of the external trigger signal generator is connected to the signal input terminal of the nanosecond narrow pulse signal generating circuit;

[0018] The external trigger signal generator is used to generate an external trigger signal.

[0019] Optionally, the external trigger signal generator is further used to adjust the external trigger signal according to a preset repetition frequency of the light emitting diode emitting light.

[0020] Optionally, the digital potentiometer is used to adjust the time constant of the second RC delay circuit so that the signal input to the first input terminal of the first AND gate and the signal input to the second input terminal of the first AND gate have staggered edges.

[0021] Optionally, the bias voltage source is a VCC_5V DC power supply.

[0022] Optionally, the VDD pin is connected to a VCC_5V DC power supply.

[0023] Optionally, the IN+ pin is connected to a VCC_5V DC power supply.

[0024] Optionally, the light emitting diode is a light emitting diode having a turn-on voltage less than VCC_5V.

[0025] The second aspect of the present invention provides a laser, comprising a laser body and any one of the programmable nanosecond narrow pulse circuits with adjustable pulse width provided in the first aspect of the present invention, wherein the programmable nanosecond narrow pulse circuit with adjustable pulse width is installed inside the laser body.

[0026] It can be seen from the above technical solutions that the nanosecond narrow pulse circuit with programmable pulse width provided by the present invention has the following advantages:

[0027] The nanosecond narrow pulse circuit with programmable adjustable pulse width provided by the present invention comprises a nanosecond narrow pulse signal generating circuit and a signal driving enhancement circuit. The nanosecond narrow pulse signal generating circuit comprises a first buffer, a second buffer, a first RC delay circuit, a second RC delay circuit and a first AND gate. An external trigger signal passes through the first buffer and the second buffer respectively to obtain two identical signals, and the signals obtain a certain load carrying capacity. The second resistor of the second RC delay circuit is a digital potentiometer, and the pulse width of the signal can be set by changing the resistance value of the digital potentiometer. After the two identical signals pass through the first AND gate, a narrow pulse signal is obtained. After the narrow pulse signal is input into a gate driving chip, a narrow pulse signal with opposite phase and strong driving capability is obtained. When the narrow pulse signal output by the gate driving chip is at a low level, the bias voltage, the current limiting resistor and the light emitting diode form a current loop through the gate driving chip, and the light emitting diode is stimulated to emit light. The nanosecond narrow pulse circuit with programmable adjustable pulse width provided by the present invention directly connects the gate drive chip to the main excitation circuit, and uses the gate drive chip as an extremely high-speed switching device. It does not need to use traditional high-speed triggers, LNA amplifiers and radio frequency amplifiers, thus avoiding the technical problems of high cost and difficulty in mass production in traditional radio frequency solutions. It does not need to use GaN, will not be affected by parasitic parameters, and has high reliability. At the same time, a first RC delay circuit and a second RC delay circuit are used to obtain a narrow pulse signal, and there is no need to use a dedicated narrow pulse drive chip, which reduces the cost and solves the technical problems of high cost, difficulty in mass production and low reliability in existing solutions for realizing nanosecond narrow pulse lasers. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 A schematic diagram of the structure of a nanosecond narrow pulse circuit with programmable pulse width adjustment provided in an embodiment of the present invention;

[0030] Figure 2 A circuit schematic diagram of a nanosecond narrow pulse signal generating circuit provided in an embodiment of the present invention;

[0031] Figure 3 A schematic diagram of a waveform of a narrow pulse signal TRIGGER_OUT provided in an embodiment of the present invention;

[0032] Figure 4 A circuit schematic diagram of a signal drive enhancement circuit provided in an embodiment of the present invention;

[0033] Figure 5 A schematic diagram of the internal structure of a gate drive chip provided in an embodiment of the present invention;

[0034] Figure 6 Schematic diagram of the waveform of the narrow pulse signal OUT provided in the embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] For easier understanding, see Figure 1 , Figure 2 and Figure 3The present invention provides an embodiment of a nanosecond narrow pulse circuit with programmable pulse width, including a nanosecond narrow pulse signal generating circuit and a signal driving enhancement circuit. The nanosecond narrow pulse signal generating circuit includes a first buffer Buffer1, a second buffer Buffer2, a first RC delay circuit, a second RC delay circuit and a first AND gate Y1. The signal driving enhancement circuit includes a gate driving chip U1, a light emitting diode D1 and a current limiting resistor RL. The input end of the first buffer Buffer1 and the input end of the second buffer Buffer2 are connected in parallel and receive the same external trigger signal TRIGGER_IN. The output end of the first buffer Buffer1 is connected to one end of the first resistor R1 of the first RC delay circuit, and the other end of the first resistor R1 is respectively connected to the first input end of the first AND gate Y1 and one end of the first capacitor C1 of the first RC delay circuit, and the other end of the first capacitor C1 is grounded. The output end of the second buffer Buffer2 is connected to one end of the second resistor R2 of the second RC delay circuit, and the other end of the second resistor R2 is respectively connected to the second input end of the first AND gate Y1 and one end of the second capacitor C2 of the second RC delay circuit, and the other end of the second capacitor C2 is grounded with the first capacitor C1. The output end of the first AND gate Y1 is connected to the input end of the gate driver chip U1. The high-level output pin OUTH of the gate driver chip U1 is connected to the cathode of the light-emitting diode D1, the anode of the light-emitting diode D1 is connected to one end of the current limiting resistor RL, and the other end of the current limiting resistor RL is connected to the bias voltage source VCC. The low-level output pin OUTL of the gate driver chip U1 is connected to the cathode of the light-emitting diode D1. The second resistor R2 is a digital potentiometer.

[0037] It should be noted that the nanosecond narrow pulse signal generation circuit is as follows Figure 2 As shown, the external trigger signal TRIGGER_IN passes through the first buffer Buffer1 and the second buffer Buffer2 respectively to obtain two identical signals with a certain load capacity. The two signals are delayed by the first RC delay circuit and the second RC delay circuit respectively to obtain the signal IN1 and the signal IN2. The signal IN1 and the signal IN2 are respectively input to the first input terminal and the second input terminal of the first AND gate Y1 to obtain the narrow pulse signal TRIGGER_OUT outputted from the output terminal of the first AND gate Y1. The narrowest pulse of the narrow pulse signal TRIGGER_OUT is less than 1ns. Figure 3As shown. The first RC delay circuit is composed of a first resistor R1 and a first capacitor C1, one end of the first resistor R1 is connected to the output end of the first buffer Buffer1, the other end of the first resistor R1 is respectively connected to one end of the first capacitor C1 and the first input end of the first AND gate Y1, and the other end of the first capacitor C1 is grounded. The second RC delay circuit is composed of a second resistor R2 and a second capacitor C2, one end of the second resistor R2 is connected to the output end of the second buffer Buffer2, the other end of the second resistor R2 is respectively connected to one end of the second capacitor C2 and the second input end of the first AND gate Y1, and the other end of the second capacitor C2 is grounded together with the first capacitor C1. The two signals output by the first buffer Buffer1 and the second buffer Buffer2 are delayed by the first RC delay circuit and the second RC delay circuit respectively, and the effective edges of the two signals are staggered. The second resistor R2 is a digital potentiometer. The resistance value of the digital potentiometer can be configured by software to set the time constant of the second RC delay circuit, thereby affecting the signal edge slope, and then setting the pulse width of the narrow pulse signal TRIGGER_OUT, so that the signal input to the first input end of the first AND gate Y1 and the signal input to the second input end of the first AND gate have staggered edges.

[0038] like Figure 4 and Figure 5 As shown, the signal drive enhancement circuit includes a gate drive chip U1, a light emitting diode D1 and a current limiting resistor RL. The high-level output pin OUTH of the gate drive chip U1 is connected to the cathode of the light emitting diode D1, the anode of the light emitting diode D1 is connected to one end of the current limiting resistor RL, the other end of the current limiting resistor RL is connected to the bias voltage source VCC, and the low-level output pin OUTL of the gate drive chip U1 is connected to the cathode of the light emitting diode D1. The bias voltage source is a VCC_5V DC power supply. After the narrow pulse signal TRIGGER_OUT output from the output end of the first AND gate Y1 is sent to the gate drive chip U1, a narrow pulse signal OUT with opposite phase and strong driving capability can be obtained, as shown in FIG. Figure 6As shown. When OUT is at a low level, the bias voltage VCC, the current limiting resistor RL and the light emitting diode D1 form a current loop through the gate driver chip U1, and the light emitting diode D1 is stimulated to emit light. The gate driver chip U1 includes a third buffer Buffer3, an inverter F1, a second AND gate Y2, a PMOS tube MOS1 and an NMOS tube MOS2. The input end of the third buffer Buffer3 is connected to the IN+ pin, the output end of the third buffer Buffer3 is connected to the first input end of the second AND gate Y2, the input end of the inverter F1 is connected to the IN- pin, the output end of the inverter F1 is connected to the second input end of the second AND gate Y2, the output end of the second AND gate Y2 is respectively connected to the gate of the PMOS tube MOS1 and the gate of the NMOS tube MOS2, the source of the PMOS tube MOS1 is connected to the VDD pin, the drain of the PMOS tube MOS1 is connected to the high level output pin OUTH, the drain of the NMOS tube MOS2 is connected to the low level output pin OUTL, and the source of the NMOS tube MOS2 is connected to the GND pin. The VDD pin of the gate driver chip U1 is connected to the VCC_5V DC power supply. The IN+ pin of the gate driver chip U1 is connected to the VCC_5V DC power supply.

[0039] The traditional use of the gate driver chip U1 is to use its fast and strong current pulling and current sinking capabilities to quickly charge and discharge the input capacitance of the driven device (MOSFET / GaN, etc.) to achieve fast switching of the driven device; use its current pulling capability to charge the input capacitance of the driven device to achieve the opening of the driven device; use its current sinking capability to discharge the input capacitance of the driven device through the gate driver chip to achieve the shutdown of the driven device. In the embodiment of the present invention, the fast current sinking capability of the gate driver chip U1 is used. When the lower tube inside the gate driver chip U1 is turned on, a current loop is formed through the bias voltage VCC, the current limiting resistor RL and the light emitting diode D1 through the lower tube of the gate driver chip U1, and the narrow Gaussian pulse current required by the load (light emitting diode D1) is obtained by using the current sinking capability of the gate driver chip U1; when the upper tube inside the gate driver chip U1 is turned on, the current is cut off through the bias voltage VCC, the current limiting resistor RL and the light emitting diode D1 through the upper tube of the gate driver chip U1. In the embodiment of the present invention, the gate driver chip U1 changes its traditional usage (used to drive a switching device, the switching device is connected to the main current loop, and the gate driver chip U1 does not enter the main current loop), and creatively uses it as a part of the main current loop.

[0040] The nanosecond narrow pulse circuit with programmable adjustable pulse width provided by the present invention comprises a nanosecond narrow pulse signal generating circuit and a signal driving enhancement circuit. The nanosecond narrow pulse signal generating circuit comprises a first buffer, a second buffer, a first RC delay circuit, a second RC delay circuit and a first AND gate. An external trigger signal passes through the first buffer and the second buffer respectively to obtain two identical signals, and the signals obtain a certain load carrying capacity. The second resistor of the second RC delay circuit is a digital potentiometer, and the pulse width of the signal can be set by changing the resistance value of the digital potentiometer. After the two identical signals pass through the first AND gate, a narrow pulse signal is obtained. After the narrow pulse signal is input into a gate driving chip, a narrow pulse signal with opposite phase and strong driving capability is obtained. When the narrow pulse signal output by the gate driving chip is at a low level, the bias voltage, the current limiting resistor and the light emitting diode form a current loop through the gate driving chip, and the light emitting diode is stimulated to emit light. The nanosecond narrow pulse circuit with programmable adjustable pulse width provided by the present invention directly connects the gate drive chip to the main excitation circuit, and uses the gate drive chip as an extremely high-speed switching device. It does not need to use traditional high-speed triggers, LNA amplifiers and radio frequency amplifiers, thus avoiding the technical problems of high cost and difficulty in mass production in traditional radio frequency solutions. It does not need to use GaN, will not be affected by parasitic parameters, and has high reliability. At the same time, a first RC delay circuit and a second RC delay circuit are used to obtain a narrow pulse signal, and there is no need to use a dedicated narrow pulse drive chip, which reduces the cost and solves the technical problems of high cost, difficulty in mass production and low reliability in existing solutions for realizing nanosecond narrow pulse lasers.

[0041] In one embodiment, the nanosecond narrow pulse circuit with programmable adjustable pulse width provided in the present invention further includes an external trigger signal generator TRIGGER, and the signal output end of the external trigger signal generator TRIGGER is connected to the signal input end of the nanosecond narrow pulse signal generating circuit. The external trigger signal generator TRIGGER is used to generate an external trigger signal TRIGGER_IN. The external trigger signal generator TRIGGER is also used to adjust the external trigger signal TRIGGER_IN according to the preset repetition frequency of the light emitting diode D1, that is, the external trigger signal TRIGGER_IN signal can be adjusted by the external trigger signal generator TRIGGER to directly set the repetition frequency of the light emitting diode D1.

[0042] In one embodiment, the light emitting diode D1 is a light emitting diode D1 with a conduction voltage less than VCC_5V. The light emitting diode D1 may be a red light emitting diode, a green light emitting diode or an ultraviolet light emitting diode. The specific light emitting color of the light emitting diode D1 may be selected according to the actual application scenario.

[0043] The narrow pulse signal of the nanosecond narrow pulse circuit with programmable adjustable pulse width provided in the present invention can be obtained by using an RC delay circuit in conjunction with an AND gate circuit. Different pulse widths can be configured by adjusting a digital potentiometer. The devices used are all conventional electronic components, and no dedicated chip (such as an expensive dedicated delay chip) is required to obtain the required narrow pulse signal; signal enhancement only requires a single conventional gate drive chip U1 to obtain the excitation intensity required for driving the light-emitting diode D1.

[0044] At the same time, the nanosecond narrow pulse circuit with programmable adjustable pulse width provided in the present invention does not require the setting and adjustment of the bias voltage as required by the RF solution; nor does it need to prominently consider the size of the loop inductive load that is crucial in the GaN solution. After the GaN solution is turned on, the capacitor needs to overcome the obstacle of the inductive load in the loop for discharging the LASER DIODE (the inductive load mainly comes from the distributed inductance of the PCB); therefore, the production consistency of different batches of the nanosecond narrow pulse circuit with programmable adjustable pulse width provided in the present invention after finalization is far better than that of the RF solution and the GaN solution.

[0045] The present invention also provides an embodiment of a laser, which includes a laser body and any implementation of the programmable nanosecond narrow pulse circuit with adjustable pulse width provided in the present invention, and the programmable nanosecond narrow pulse circuit with adjustable pulse width is installed inside the laser body.

[0046] The terms "first", "second", "third", etc. in the present invention are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0047] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A nanosecond narrow pulse circuit with programmable pulse width, characterized in that: It includes a nanosecond narrow pulse signal generating circuit and a signal driving enhancement circuit; The nanosecond narrow pulse signal generating circuit comprises a first buffer, a second buffer, a first RC delay circuit, a second RC delay circuit and a first AND gate; The signal driving enhancement circuit includes a gate driving chip, a light emitting diode and a current limiting resistor; The input end of the first buffer and the input end of the second buffer are connected in parallel and receive the same external trigger signal together, the output end of the first buffer is connected to one end of the first resistor of the first RC delay circuit, the other end of the first resistor is respectively connected to the first input end of the first AND gate and one end of the first capacitor of the first RC delay circuit, the other end of the first capacitor is grounded, the output end of the second buffer is connected to one end of the second resistor of the second RC delay circuit, the other end of the second resistor is respectively connected to the second input end of the first AND gate and one end of the second capacitor of the second RC delay circuit, the other end of the second capacitor is grounded with the first capacitor, and the output end of the first AND gate is connected to the input end of the gate drive chip; The high level output pin of the gate drive chip is connected to the cathode of the light emitting diode, the anode of the light emitting diode is connected to one end of the current limiting resistor, the other end of the current limiting resistor is connected to the bias voltage source, and the low level output pin of the gate drive chip is connected to the cathode of the light emitting diode; The second resistor is a digital potentiometer.

2. The nanosecond narrow pulse circuit with programmable pulse width according to claim 1, characterized in that: The gate driving chip includes a third buffer, an inverter, a second AND gate, a PMOS tube and an NMOS tube; The input end of the third buffer is connected to the IN+ pin, the output end of the third buffer is connected to the first input end of the second AND gate, the input end of the inverter is connected to the IN- pin, the output end of the inverter is connected to the second input end of the second AND gate, the output end of the second AND gate is respectively connected to the gate of the PMOS tube and the gate of the NMOS tube, the source of the PMOS tube is connected to the VDD pin, the drain of the PMOS tube is connected to the high level output pin, the drain of the NMOS tube is connected to the low level output pin, and the source of the NMOS tube is connected to the GND pin.

3. The nanosecond narrow pulse circuit with programmable pulse width according to claim 2, characterized in that: Also includes an external trigger signal generator; The signal output terminal of the external trigger signal generator is connected to the signal input terminal of the nanosecond narrow pulse signal generating circuit; The external trigger signal generator is used to generate an external trigger signal.

4. The nanosecond narrow pulse circuit with programmable pulse width according to claim 3, characterized in that: The external trigger signal generator is also used to adjust the external trigger signal according to the preset repetition frequency of the light emitting diode.

5. The nanosecond narrow pulse circuit with programmable pulse width according to claim 1, characterized in that: The digital potentiometer is used to adjust the time constant of the second RC delay circuit so that the signal input to the first input terminal of the first AND gate and the signal input to the second input terminal of the first AND gate have staggered edges.

6. The nanosecond narrow pulse circuit with programmable pulse width according to claim 1, characterized in that: The bias voltage source is VCC_5V DC power supply.

7. The nanosecond narrow pulse circuit with programmable pulse width according to claim 2, characterized in that: The VDD pin is connected to the VCC_5V DC power supply.

8. The nanosecond narrow pulse circuit with programmable pulse width according to claim 2, characterized in that: The IN+ pin is connected to the VCC_5V DC power supply.

9. The nanosecond narrow pulse circuit with programmable pulse width according to any one of claims 1 to 8, characterized in that: The light emitting diode is a light emitting diode with a turn-on voltage less than VCC_5V.

10. A laser, characterized in that: The invention comprises a laser body and a nanosecond narrow pulse circuit with programmable adjustable pulse width as claimed in any one of claims 1 to 9, wherein the nanosecond narrow pulse circuit with programmable adjustable pulse width is installed inside the laser body.

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