Layout and wiring method and device, electronic equipment and storage medium
By increasing the congestion level of logic units in a specific module area in the target chip before the chip layout, the resource congestion problem caused by the increase in the number of module units is solved, and timing convergence and chip area are achieved.
Patent Information
- Application Number
- CN202510157275.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-12
- Publication Date
- 2025-06-03
AI Technical Summary
Due to the increase in the number of module units, unit resources and trace resources are congested, resulting in insufficient trace resources and crosstalk, which makes the timing difficult to converge.
By obtaining the operating frequency of multiple module areas on the target chip, determining the first module area, and increasing the congestion level of the logic unit in the module area before layout, and updating the chip netlist file to perform chip layout.
It saves chip area resources, avoids insufficient trace resources and crosstalk, thereby meeting the timing convergence requirements.
Smart Images
Figure CN120087290A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit design technology. Specifically, it relates to a placement and routing method, apparatus, electronic device, and storage medium. Background Art
[0002] With the development of integrated circuits, considering factors such as cost and efficiency, chips are designed to be smaller and smaller. However, due to the growth of chip functions, the number of module units integrated inside the chip increases. Therefore, chip area and timing usually need to be considered in a trade-off.
[0003] In the related art, it is hoped to complete the design of timing convergence under the condition of the smallest possible chip area. However, due to the increase in the number of module units, there may be congestion of unit resources and routing resources, resulting in a large shortage of routing resources and crosstalk, making it difficult to converge the timing. Summary of the Invention
[0004] In view of this, the embodiments of this application provide a placement and routing method, apparatus, electronic device, and storage medium to solve the problem that due to the increase in the number of module units, the unit resources and routing resources are congested, resulting in a large shortage of routing resources and crosstalk, making it difficult to converge the timing.
[0005] In a first aspect, the embodiments of this application provide a placement and routing method, including:
[0006] Obtain the operating frequencies of multiple module regions on a target chip according to a chip netlist file;
[0007] Determine a first module region from the multiple module regions according to the operating frequency;
[0008] Increase the congestion degree of the logic units in the first module region and update the chip netlist file to perform chip placement.
[0009] In an optional implementation manner, the determining a first module region from the multiple module regions according to the operating frequency includes:
[0010] Determine the module regions whose operating frequencies are lower than a preset frequency threshold from the multiple module regions as the first module region.
[0011] In an optional implementation manner, the determining a first module region from the multiple module regions according to the operating frequency includes:
[0012] Obtain the operating frequencies of the multiple module regions according to the chip netlist file;
[0013] Determine the module area among the multiple module areas where the operating frequency is higher than the preset frequency threshold but the operating frequency is lower than the preset frequency threshold as the first module area.
[0014] In an alternative embodiment, increasing the congestion degree of the logic units in the first module area includes:
[0015] Reduce the distance between the logic units in the first module area.
[0016] In an alternative embodiment, after increasing the congestion degree of the logic units in the first module area and updating the chip netlist file, the method further includes:
[0017] After chip layout, obtain the number of interface units in each module area according to the chip netlist file;
[0018] Determine a second module area from the multiple module areas according to the number of the interface units;
[0019] Adjust the routing parameters of the second module area to obtain target routing parameters for chip routing.
[0020] In an alternative embodiment, determining the second module area from the multiple module areas according to the number of the interface units includes:
[0021] Determine the congestion degree of the interface units according to the size of the interface units and the size of the layout space where the interface units are located;
[0022] Determine the second module area from the multiple module areas according to the congestion degree of the interface units and the number of the interface units.
[0023] In an alternative embodiment, determining the second module area from the multiple module areas according to the congestion degree of the interface units and the number of the interface units includes:
[0024] Determine a third module area from the multiple module areas according to the congestion degree of the interface units and the number of the interface units;
[0025] Obtain the first voltage drop and / or the first switching rate of the third module area;
[0026] Determine the second module area from the third module area according to the first voltage drop and / or the first switching rate.
[0027] In an alternative embodiment, determining the second module area from the multiple module areas according to the number of the interface units includes:
[0028] Determine, from the multiple module regions, the module regions where the number of interface units exceeds a preset number threshold as the second module regions.
[0029] In an alternative embodiment, adjusting the wiring parameters of the second module region to obtain target wiring parameters includes:
[0030] Obtain the second voltage drop and / or the second switching rate of the second module region;
[0031] If the second voltage drop does not exceed a first voltage drop threshold and / or the second switching rate does not exceed a first switching rate threshold, adjust the wiring parameters of the second module region until the second voltage drop exceeds the first voltage drop threshold and / or the second switching rate exceeds the first switching rate threshold, and determine the wiring parameters determined in the previous adjustment as the target wiring parameters.
[0032] In an alternative embodiment, the method further includes:
[0033] After chip wiring, obtain the third voltage drop and / or the third switching rate of the first module region, and the fourth voltage drop and / or the fourth switching rate of the second module region;
[0034] If the third voltage drop exceeds a second voltage drop threshold and / or the third switching rate exceeds a second switching rate threshold, reduce the congestion degree of the logic units in the first module region;
[0035] If the fourth voltage drop exceeds the second voltage drop threshold and / or the fourth switching rate exceeds the second switching rate threshold, readjust the wiring parameters of the second module region.
[0036] In an alternative embodiment, adjusting the wiring parameters of the second module region includes:
[0037] Reduce the width of the power line in the second module region and / or increase the spacing of the power line in the second module region.
[0038] In a second aspect, an embodiment of the present application further provides a layout and wiring device, including:
[0039] An acquisition module, configured to acquire the operating frequencies of multiple module regions on a target chip according to a chip netlist file;
[0040] A determination module, configured to determine a first module region from the multiple module regions according to the operating frequencies;
[0041] A processing module, configured to increase the congestion degree of logic units in the first module area and update the chip netlist file for chip layout.
[0042] In an optional embodiment, the determining module is specifically configured to:
[0043] Determine, from the multiple module areas, the module area whose operating frequency is lower than a preset frequency threshold as the first module area.
[0044] In an optional embodiment, the determining module is specifically configured to:
[0045] Obtain the operating frequencies of the multiple module areas according to the chip netlist file;
[0046] Determine, as the first module area, the module area in the multiple module areas whose operating frequency is higher than the preset frequency threshold but whose operating frequency is lower than the preset frequency threshold.
[0047] In an optional embodiment, the processing module is specifically configured to:
[0048] Reduce the distance between logic units in the first module area.
[0049] In an optional embodiment, the obtaining module is further configured to:
[0050] After chip layout, obtain the number of interface units of each module area according to the chip netlist file;
[0051] The determining module is further configured to determine a second module area from the multiple module areas according to the number of interface units;
[0052] The processing module is further configured to adjust the wiring parameters of the second module area to obtain target wiring parameters for chip wiring.
[0053] In an optional embodiment, the determining module is specifically configured to:
[0054] Determine the congestion degree of the interface unit according to the size of the interface unit and the size of the layout space where the interface unit is located;
[0055] Determine the second module area from the multiple module areas according to the congestion degree of the interface unit and the number of interface units.
[0056] In an optional embodiment, the determining module is specifically configured to:
[0057] Determine a third module region from the multiple module regions according to the congestion degree of the interface unit and the number of the interface units;
[0058] Obtain a first voltage drop and / or a first switching rate of the third module region;
[0059] Determine the second module region from the third module region according to the first voltage drop and / or the first switching rate.
[0060] In an optional implementation manner, the determining module is specifically configured to:
[0061] Determine, from the multiple module regions, a module region where the number of the interface units exceeds a preset number threshold as the second module region.
[0062] In an optional implementation manner, the processing module is further configured to:
[0063] Obtain a second voltage drop and / or a second switching rate of the second module region;
[0064] If the second voltage drop does not exceed a first voltage drop threshold and / or the second switching rate does not exceed a first switching rate threshold, adjust the wiring parameters of the second module region until the second voltage drop exceeds the first voltage drop threshold and / or the second switching rate exceeds the first switching rate threshold, and determine the wiring parameters determined in the previous adjustment as the target wiring parameters.
[0065] In an optional implementation manner, the obtaining module is further configured to:
[0066] After chip wiring, obtain a third voltage drop and / or a third switching rate of the first module region, and a fourth voltage drop and / or a fourth switching rate of the second module region;
[0067] The processing module is further configured to, if the third voltage drop exceeds a second voltage drop threshold and / or the third switching rate exceeds a second switching rate threshold, reduce the congestion degree of the logic units in the first module region;
[0068] The processing module is further configured to, if the fourth voltage drop exceeds the second voltage drop threshold and / or the fourth switching rate exceeds the second switching rate threshold, readjust the wiring parameters of the second module region.
[0069] In an optional implementation manner, the processing module is specifically configured to:
[0070] Reduce the width of the power line in the second module region and / or increase the spacing of the power lines in the second module region.
[0071] In a third aspect, an embodiment of the present application further provides an electronic device, including: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device runs, the processor communicates with the memory through the bus, and the processor executes the machine-readable instructions to execute the method according to any one of the first aspect.
[0072] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium. A computer program is stored on the computer-readable storage medium, and when the computer program is run by a processor, the method according to any one of the first aspect is executed.
[0073] The present application provides a layout and routing method, apparatus, electronic device, and storage medium. Among them, the method includes: obtaining the working frequencies of multiple module areas on a target chip according to a chip netlist file, determining a first module area from the multiple module areas according to the working frequencies, increasing the congestion degree of logic units in the first module area, and updating the chip netlist file to perform chip layout. Increasing the congestion degree of logic units in the first module area before layout saves chip area resources and avoids the situation of insufficient routing resources and crosstalk, thereby meeting the requirements of timing convergence. BRIEF DESCRIPTION OF THE DRAWINGS
[0074] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required in the embodiments. It should be understood that the following drawings only show some embodiments of the present application and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.
[0075] Figure 1 Flow diagram of the layout and routing method provided by the embodiment of the present application Figure 1 ;
[0076] Figure 2 Flow diagram of the layout and routing method provided by the embodiment of the present application Figure 2 ;
[0077] Figure 3 Flow diagram of the layout and routing method provided by the embodiment of the present application Figure 3 ;
[0078] Figure 4 Flow diagram of the layout and routing method provided by the embodiment of the present application Figure 4 ;
[0079] Figure 5 Flow diagram of the layout and routing method provided by the embodiment of the present application Figure 5 ;
[0080] Figure 6 Schematic diagram of the layout and routing method provided by the embodiment of the present application Figure 6 ;
[0081] Figure 7 Schematic diagram of the structure of the layout and routing device provided by the embodiment of the present application;
[0082] Figure 8 Schematic diagram of the structure of the electronic device provided by the embodiment of the present application. Detailed implementation manners
[0083] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and illustrated herein generally may be arranged and designed in a variety of different configurations. Therefore, the detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application claimed, but merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts fall within the scope of protection of the present application.
[0084] With the design trend of smaller and smaller chips and the increase in the number of module units integrated inside the chips, there may be congestion of unit resources and routing resources, resulting in a large shortage of routing resources and crosstalk, making it difficult to converge the timing, and it is also possible that some timing and voltage drops are easily satisfied with regional dispersion, wasting area.
[0085] Based on this, the present application determines a first module area from multiple module areas of a target chip according to the working frequency, and before layout, increases the congestion degree of the logic units in the first module area, saving chip area resources and avoiding the situation of insufficient routing resources and crosstalk, thereby meeting the timing convergence requirements.
[0086] Figure 1 Schematic diagram of the layout and routing method provided by the embodiment of the present application Figure 1 In this embodiment, the execution subject may be an electronic device.
[0087] As Figure 1 shown, the method may include:
[0088] S101. Obtain the working frequencies of multiple module areas on the target chip according to the chip netlist file.
[0089] Among them, the module area is the area corresponding to the module units integrated inside the target chip. The module units can be obtained by dividing the chip according to a preset division rule for the convenience of logical code design and physical implementation design in physical implementation.
[0090] The chip netlist file may include: the operating frequencies of multiple module areas on the target chip. Among them, each module area may have a corresponding frequency clock, and the frequency of the frequency clock is the operating frequency of the module area. Therefore, the operating frequencies of multiple module areas on the target chip can be obtained from the chip netlist file.
[0091] It can be understood that the operating frequencies of different module areas can be the same or different, which can be specifically determined according to the chip design parameters, and this embodiment does not make special limitations on this.
[0092] S102. Determine a first module area from multiple module areas according to the operating frequency.
[0093] Filter multiple module areas according to the operating frequency to determine a first module area from multiple module areas, where the operating frequency of the first module area meets a preset frequency condition.
[0094] In an optional implementation manner, the above step S102, determining a first module area from multiple module areas according to the operating frequency, may include:
[0095] Determine the module areas with operating frequencies lower than a preset frequency threshold from multiple module areas as the first module area.
[0096] Among them, since the timing and voltage drop of the module areas with operating frequencies lower than the preset frequency threshold are easy to meet (the timing and voltage drop are relatively safe), the module areas with operating frequencies lower than the preset frequency threshold can be determined as the first module area.
[0097] It is worth noting that the voltage drop includes static voltage drop and / or dynamic voltage drop. Static Voltage Drop refers to the phenomenon of power supply voltage drop due to resistive losses or other factors when the circuit or system is in a stable operating state.
[0098] Dynamic Voltage Drop refers to the phenomenon of instantaneous voltage drop of the power supply voltage due to rapid changes in load current. This usually occurs in digital circuits. When a large number of transistors perform state transitions at the same time, it will suddenly increase the demand for power supply, thus causing local or global voltage drops.
[0099] It can be understood that the preset frequency threshold can be a preset working frequency threshold, and the preset frequency threshold can be selected according to actual requirements. This embodiment does not make any special limitations on the specific selection of the preset frequency threshold.
[0100] In an alternative embodiment, step S102 of determining the first module area from multiple module areas according to the working frequency may include:
[0101] Obtain the working frequencies of multiple module areas according to the chip netlist file;
[0102] Determine the module areas among the multiple module areas where the working frequency is higher than the preset frequency threshold but the working frequency is lower than the preset frequency threshold as the first module area.
[0103] The chip netlist file may further include: the working frequencies of multiple module areas on the target chip, where the working frequency refers to the working frequency of the module area per unit time.
[0104] Obtain the working frequencies of multiple module areas from the chip netlist file, and determine the module areas among the multiple module areas where the working frequency is higher than the preset frequency threshold but the working frequency is lower than the preset frequency threshold as the first module area.
[0105] Among them, since the flip rate of the module area where the working frequency is higher than the preset frequency threshold but the working frequency is lower than the preset frequency threshold is relatively low, that is, the timing and voltage drop of this module area are easily satisfied (the timing and voltage drop are relatively safe), the module area where the working frequency is higher than the preset frequency threshold but the working frequency is lower than the preset frequency threshold can be determined as the first module area.
[0106] It should be noted that the flip rate refers to the frequency of voltage level conversion, that is, the change rate from low level to high level or from high level to low level. For a given time period, the flip rate can be understood as the number of signal changes divided by this time period.
[0107] It can be understood that the working frequencies of different module areas can be the same or different, which can be specifically determined according to chip design parameters. This embodiment does not make any special limitations on this.
[0108] S103. Increase the congestion degree of the logic units in the first module area and update the chip netlist file for chip layout.
[0109] Among them, the chip netlist file may further include: the congestion degree of the logic units in each module area.
[0110] The first module area includes multiple logic units, and the logic units can be obtained by dividing the module units according to the logic hierarchy of the corresponding module units in the first module area.
[0111] Increase the congestion degree of the logic cells in the first module area, and update the chip netlist file according to the increased congestion degree, so that the congestion degree of the first module area in the chip netlist file is the updated congestion degree.
[0112] After updating the chip netlist file, the target chip can also be laid out according to the congestion degree of the logic cells in each module area and the working frequencies of multiple module areas in the chip netlist file.
[0113] In an optional embodiment, step S103 above, increasing the congestion degree of the logic cells in the first module area, may include:
[0114] Reduce the distance between the logic cells in the first module area.
[0115] Wherein, the chip netlist file may further include: the distances between the logic cells in each module area.
[0116] Reduce the distance between the logic cells in the first module area, and update the chip netlist file according to the reduced distance, so that the distance between the logic cells in the first module area in the chip netlist file is the reduced distance. For example, a fixed value can be reduced each time, or it can be reduced within a specified range, or the reduced distance can be specified according to the reduction instruction, etc., which is not limited here.
[0117] After updating the chip netlist file, the target chip can also be laid out according to the distances between the logic cells in each module area and the working frequencies of multiple module areas in the chip netlist file.
[0118] It should be noted that the congestion degree is reflected by the distance between the logic cells. The smaller the distance, the higher the congestion degree and the greater the regional density. The larger the distance, the lower the congestion degree and the smaller the regional density. Regarding the specific value of the reduction, it can be selected according to the actual situation, and this embodiment does not make special limitations on this.
[0119] It should be noted that the above steps S101 - S103 can be implemented by a placement and routing tool, and this embodiment does not make special limitations on the placement and routing tool.
[0120] In this embodiment, before placement, starting from a design that meets both timing and voltage drop requirements, the first module area is determined from multiple module areas, and the congestion degree of the logic cells in the first module area is increased, so that characteristic module areas can be predicted and customized in the early stage of placement, enabling the logic cells in the first module area to make full use of the area, saving chip area resources, avoiding situations of insufficient routing resources and crosstalk, and thus meeting the timing convergence requirements.
[0121] Figure 2Flow schematic of the layout and routing method provided by the embodiments of the present application Figure 2 , as Figure 2 shown, in an optional embodiment, after increasing the congestion degree of the logic units in the first module area and updating the chip netlist file in step S103, the method may further include:
[0122] S201. After chip layout, obtain the number of interface units of each module area according to the chip netlist file.
[0123] The chip netlist file may further include: the number of interface units of each module area on the target chip. Among them, the interface unit is the unit for the logic unit in each module area to connect to the logic unit in other module areas, such as port. That is to say, the logic unit in the module area connects to the logic unit in other module areas through the interface unit of the module area.
[0124] After chip layout, obtain the number of interface units of each module area from the chip netlist file.
[0125] S202. Determine a second module area from multiple module areas according to the number of interface units.
[0126] Filter multiple module areas according to the number of interface units to determine the module area that meets the preset quantity condition as the second module area, where the number of interface units of the second module area meets the preset quantity condition.
[0127] S203. Adjust the routing parameters of the second module area to obtain target routing parameters for chip routing.
[0128] Among them, each module area has default routing parameters, such as routing width and routing spacing. After determining the second module area, adjust the routing parameters of the second module area to obtain target routing parameters, so as to perform chip routing according to the target routing parameters of the second module area and the default routing parameters of other module areas. Among them, the routing parameters of the second module area after routing are the target routing parameters, and the routing parameters of other module areas after routing are the default routing parameters.
[0129] In some embodiments, since adjusting the routing parameters of the power supply line has little impact on the target chip, the routing parameters of the second module area may be the routing parameters of the power supply line of the second module area. In addition, since there is less routing on the top layer and the second top layer of the second module area, generally only the power supply line or mainly the power supply line, the routing parameters of the power supply lines on the top layer and the second top layer of the second module area can also be adjusted.
[0130] In an optional embodiment, step S203 of adjusting the routing parameters of the second module area may include:
[0131] Reduce the width of the power line in the second module area and / or increase the spacing between the power lines in the second module area.
[0132] Reduce the width of the power line in the second module area and / or increase the spacing between the power lines in the second module area, so as to adjust the routing density of the power line, thereby releasing the routing resources in the second module area, saving the chip area resources, avoiding the situation of insufficient routing resources and crosstalk, and thus meeting the timing convergence requirements.
[0133] Among them, the width of the power line can be halved and the spacing can be doubled. The adjustment intensity of the width and spacing of the power line is not particularly limited in this embodiment.
[0134] It should be noted that the above steps S201 - S203 can be implemented by a placement and routing tool, and this embodiment does not particularly limit the placement and routing tool.
[0135] In this embodiment, before routing, the routing resources in the second module area where timing and voltage drop are difficult to meet are released, so that the characteristic model area can be predicted and customized before routing.
[0136] Figure 3 Schematic flow of the placement and routing method provided by the embodiment of the present application Figure 4 , such as Figure 3 shown, in an alternative embodiment, the above step S202, determining the second module area from multiple module areas according to the number of interface units, may include:
[0137] S301. Determine the congestion degree of the interface unit according to the size of the interface unit and the size of the layout space where the interface unit is located.
[0138] After chip layout, the chip is divided into layout spaces. For example, a square space of 5 (micrometers) × 5 (micrometers). If the interface unit is deployed in one layout space, the size of the layout space where the interface unit is located is 5 (micrometers) × 5 (micrometers). If the interface unit is deployed in two layout spaces, the size of the layout space where the interface unit is located is 10 (micrometers) × 10 (micrometers).
[0139] In some embodiments, the layout space is usually relatively small, with a range of, for example, 5 - 10 (micrometers) × 5 - 10 (micrometers). Of course, this embodiment is not limited thereto.
[0140] Calculate the congestion degree of the interface unit according to the size of the interface unit and the size of the layout space where the interface unit is located. The congestion degree of the interface unit refers to the density of the interface unit, which is expressed as the ratio of the size of the interface unit to the size of the layout space where the interface unit is located. The ratio of the size of the interface unit to the size of the layout space where the interface unit is located can be understood as the ratio of the area of the interface unit to the area of the layout space where the interface unit is located. Among them, the area of the interface unit can be calculated according to the size of the interface unit, and the area of the layout space can be calculated according to the size of the layout space where the interface unit is located.
[0141] Among them, the module area may include multiple interface units.
[0142] S302. Determine the second module area from multiple module areas according to the congestion degree of the interface unit and the number of interface units.
[0143] Determine, from multiple module areas, the module area where the congestion degree of the interface unit exceeds the preset congestion degree and the number of interface units does not exceed the preset number as the second module area. That is to say, the second module area is the module area with fewer interface units but larger interface unit sizes.
[0144] Among them, the preset congestion degree can be characterized by a preset density. The preset density can be 75% for example. That is to say, the module area with an interface unit density higher than 75% and fewer interface units is used as the second module area.
[0145] Since the number of interface units is small and the flip rate of the module area with a high interface unit density is low, that is, the timing and voltage drop of this module area are difficult to meet, it can be determined that this module area is a safe area for releasing routing resources, that is, the second module area.
[0146] In an optional implementation manner, in step S302 above, determining the second module area from multiple module areas according to the number of interface units may include:
[0147] S303. Determine, from multiple module areas, the module area where the number of interface units exceeds the preset number threshold as the second module area.
[0148] Determine, from multiple module areas, the module area where the number of interface units exceeds the preset number threshold as the second module area. Among them, the number of interface units in the second module area exceeds the preset number threshold.
[0149] Since the more the number of interface units, the fewer the number of logic units between module areas and the lower the flip rate, that is, the timing and voltage drop of this module area are difficult to meet, it can be determined that this module area is a safe area for releasing routing resources, that is, the second module area.
[0150] Figure 4Flow schematic of the layout and routing method provided by the embodiments of the present application Figure 4 , such as Figure 4 shown, in an alternative embodiment, step S302 of determining a second module area from a plurality of module areas according to the congestion degree of the interface unit and the number of interface units may include:
[0151] S401. Determine a third module area from a plurality of module areas according to the congestion degree of the interface unit and the number of interface units.
[0152] Determine, from a plurality of module areas, that the congestion degree of the interface unit exceeds a preset congestion degree and the number of interface units does not exceed a preset number as the third module area.
[0153] S402. Obtain the first voltage drop and / or the first switching rate of the third module area.
[0154] S403. Determine a second module area from the third module area according to the first voltage drop and / or the first switching rate.
[0155] The first voltage drop is the voltage drop of the third module area, and the first switching rate is the switching rate of the third module area.
[0156] Use a layout and routing tool to simulate and obtain the first voltage drop and / or the first switching rate of the third module area, and screen the third module area according to the first voltage drop and / or the first switching rate to determine a second module area from the third module area.
[0157] Among them, the first voltage drop of the second module area may be less than the first voltage drop threshold, and the first switching rate of the second module area may be less than the first switching rate threshold. The first voltage drop threshold may be 6%, for example.
[0158] That is to say, after determining the third module area, further screen out the module area where the first voltage drop may be less than the first voltage drop threshold and the first switching rate may be less than the first switching rate threshold as the second module area.
[0159] Since the timing and voltage drop of the module area where the first voltage drop may be less than the first voltage drop threshold and the first switching rate may be less than the first switching rate threshold are easy to meet (the timing and voltage drop are relatively safe), a second module area can be further determined from the third module area to further reduce the impact on the timing and voltage drop of the second module area when adjusting the wiring parameters.
[0160] Figure 5 Flow schematic of the layout and routing method provided by the embodiments of the present application Figure 5 , such as Figure 5As shown, in an optional embodiment, the above step S203 of adjusting the wiring parameters of the second module area to obtain target wiring parameters may include:
[0161] S501. Obtain the second voltage drop and / or the second switching rate of the second module area.
[0162] The second voltage drop is the voltage drop of the second module area, and the second switching rate is the switching rate of the second module area.
[0163] Use a placement and routing tool to simulate and obtain the second voltage drop and / or the second switching rate of the second module area.
[0164] S502. If the second voltage drop does not exceed the first voltage drop threshold and / or the second switching rate does not exceed the first switching rate threshold, adjust the wiring parameters of the second module area until the second voltage drop exceeds the first voltage drop threshold and / or the second switching rate exceeds the first switching rate threshold, and determine the wiring parameters determined in the previous adjustment as the target wiring parameters.
[0165] If the second voltage drop does not exceed the first voltage drop threshold and / or the second switching rate does not exceed the first switching rate threshold, adjust the wiring parameters of the second module area. For example, reduce the width of the power line in the second module area and / or increase the spacing of the power line in the second module area. After adjusting the wiring parameters of the second module area, continue to obtain the second voltage drop and / or the second switching rate of the second module area. If the second voltage drop does not exceed the first voltage drop threshold and / or the second switching rate does not exceed the first switching rate threshold, continue to adjust the wiring parameters of the second module area. For example, on the basis of the wiring parameters after the previous adjustment, continue to reduce the width of the power line in the second module area and / or increase the spacing of the power line in the second module area.
[0166] Repeat the above iterative process until the second voltage drop exceeds the first voltage drop threshold and / or the second switching rate exceeds the first switching rate threshold, and determine the wiring parameters determined in the previous adjustment when the second voltage drop exceeds the first voltage drop threshold and / or the second switching rate exceeds the first switching rate threshold as the target wiring parameters.
[0167] Among them, during the adjustment process of the wiring parameters of the above power line, the width of the power line can be halved and the spacing can be doubled. Regarding the adjustment intensity of the width and spacing of the power line, this embodiment does not make special limitations.
[0168] In this embodiment, by reducing the routing density to release the routing resources of the second module area, and using the voltage drop and / or switching rate of the second module area as the evaluation criterion, the purpose of fully releasing the routing resources is achieved, so as to ensure that on the basis of reducing the routing density, the performance of the second module area is not greatly affected.
[0169] Figure 6 Flow schematic of the layout and routing method provided by the embodiments of the present application Figure 6 , such as Figure 6 shown, in an optional embodiment, the method may further include:
[0170] S601. After chip routing, obtain the third voltage drop and / or the third switching rate of the first module area, and the fourth voltage drop and / or the fourth switching rate of the second module area.
[0171] After chip routing, use the layout and routing tool to simulate and obtain the third voltage drop and / or the third switching rate of the first module area, and the fourth voltage drop and / or the fourth switching rate of the second module area.
[0172] Among them, the third voltage drop and the third switching rate are the voltage drop and the switching rate of the first module area, and the fourth voltage drop and the fourth switching rate are the voltage drop and the switching rate of the first module area.
[0173] S602. If the third voltage drop exceeds the second voltage drop threshold and / or the third switching rate exceeds the second switching rate threshold, then reduce the congestion degree of the logic cells in the first module area.
[0174] If the third voltage drop exceeds the second voltage drop threshold and / or the third switching rate exceeds the second switching rate threshold, it means that the performance of the first module area is sacrificed when increasing the congestion degree of the logic cells in the first module area. Then, after routing, the congestion degree of the logic cells in the first module area can be reduced. For example, the distance between the logic cells in the first module area can be increased.
[0175] S603. If the fourth voltage drop exceeds the second voltage drop threshold and / or the fourth switching rate exceeds the second switching rate threshold, then adjust the routing parameters of the second module area.
[0176] If the fourth voltage drop exceeds the second voltage drop threshold and / or the fourth switching rate exceeds the second switching rate threshold, it means that the performance of the second module area is sacrificed when reducing the routing resources in the second module area. Then, the routing parameters of the second module area can be readjusted. For example, increase the width of the power line in the second module area and / or reduce the spacing between the power lines in the second module area.
[0177] In some embodiments, the target routing parameters can also be restored to the routing parameters determined by the previous adjustment in the iterative process. For example, restore the halved power line to some resources.
[0178] It should be noted that the first voltage drop threshold and the second voltage drop threshold may be equal. For example, the first voltage drop threshold is 6% and the second voltage drop threshold is 10%, or they may not be equal. The first flip rate and the second flip rate may be equal or may not be equal. This embodiment does not make special limitations on this.
[0179] In this embodiment, after routing, by verifying the voltage drop and / or flip rate of the first module area and the second module area, when the requirements are not met, the congestion degree of the logic units in the first module area and the width and spacing of the power lines in the second module area are readjusted, so as to balance the performance of the first module area and the second module area on the basis of saving chip area resources.
[0180] Figure 7 It is a schematic structural diagram of the placement and routing device provided by the embodiment of the present application, and this device can be integrated in an electronic device.
[0181] As Figure 8 shown, this device may include:
[0182] An obtaining module 701, configured to obtain the operating frequencies of multiple module areas on a target chip according to a chip netlist file;
[0183] A determining module 702, configured to determine a first module area from multiple module areas according to the operating frequencies;
[0184] A processing module 703, configured to increase the congestion degree of the logic units in the first module area and update the chip netlist file for chip placement.
[0185] In an optional implementation manner, the determining module 702 is specifically configured to:
[0186] Determine, from multiple module areas, a module area whose operating frequency is lower than a preset frequency threshold as the first module area.
[0187] In an optional implementation manner, the determining module 702 is specifically configured to:
[0188] Obtain the operating frequencies of multiple module areas according to the chip netlist file;
[0189] Determine, as the first module area, a module area among multiple module areas whose operating frequency is higher than a preset frequency threshold but whose operating frequency is lower than a preset frequency threshold.
[0190] In an optional implementation manner, the processing module 703 is specifically configured to:
[0191] Reduce the distance between the logic units in the first module area.
[0192] In an alternative embodiment, the obtaining module 701 is further configured to:
[0193] After the chip layout, according to the chip netlist file, obtain the number of interface units in each module area;
[0194] The determining module 702 is further configured to determine a second module area from multiple module areas according to the number of interface units;
[0195] The processing module 703 is further configured to adjust the routing parameters of the second module area to obtain target routing parameters for chip routing.
[0196] In an alternative embodiment, the determining module 702 is specifically configured to:
[0197] Determine the congestion degree of the interface unit according to the size of the interface unit and the layout space where the interface unit is located;
[0198] Determine a second module area from multiple module areas according to the congestion degree of the interface unit and the number of interface units.
[0199] In an alternative embodiment, the determining module 702 is specifically configured to:
[0200] Determine a third module area from multiple module areas according to the congestion degree of the interface unit and the number of interface units;
[0201] Obtain the first voltage drop and / or the first switching rate of the third module area;
[0202] Determine a second module area from the third module area according to the first voltage drop and / or the first switching rate.
[0203] In an alternative embodiment, the determining module 702 is specifically configured to:
[0204] Determine, as the second module area, the module area in which the number of interface units exceeds a preset number threshold from multiple module areas.
[0205] In an alternative embodiment, the processing module 703 is further configured to:
[0206] Obtain the second voltage drop and / or the second switching rate of the second module area;
[0207] If the second voltage drop does not exceed the first voltage drop threshold, and / or the second switching rate does not exceed the first switching rate threshold, then adjust the routing parameters of the second module area until the second voltage drop exceeds the first voltage drop threshold, and / or the second switching rate exceeds the first switching rate threshold, and determine the routing parameters determined in the previous adjustment as the target routing parameters.
[0208] In an alternative embodiment, the obtaining module 701 is further configured to:
[0209] After chip wiring, obtain the third voltage drop and / or the third switching rate of the first module area, and the fourth voltage drop and / or the fourth switching rate of the second module area;
[0210] The processing module is further configured to reduce the congestion degree of the logic units in the first module area if the third voltage drop exceeds the second voltage drop threshold and / or the third switching rate exceeds the second switching rate threshold;
[0211] The processing module is further configured to readjust the wiring parameters of the second module area if the fourth voltage drop exceeds the second voltage drop threshold and / or the fourth switching rate exceeds the second switching rate threshold.
[0212] In an alternative embodiment, the processing module 703 is specifically configured to:
[0213] Reduce the width of the power line in the second module area and / or increase the spacing of the power line in the second module area.
[0214] For the description of the processing flow of each module in the device and the interaction flow between modules, reference may be made to the relevant descriptions in the above method embodiments, which will not be elaborated here.
[0215] Figure 8 The following is a schematic structural diagram of the electronic device provided in the embodiment of the present application. As Figure 8 shown, the device may include: a processor 801, a memory 802, and a bus 803. The memory 802 stores machine-readable instructions executable by the processor 801. When the electronic device runs, the processor 801 communicates with the memory 802 through the bus, and the processor 801 executes the machine-readable instructions to execute the above method.
[0216] The embodiment of the present application further provides a computer-readable storage medium. A computer program is stored on the computer-readable storage medium, and when the computer program is run by a processor, the above method is executed.
[0217] In the embodiment of the present application, when the computer program is run by a processor, other machine-readable instructions may also be executed to execute other methods described in the embodiments. For the specific method steps and principles to be executed, refer to the descriptions in the embodiments, which will not be elaborated in detail here.
[0218] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For another example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections between each other can be through some communication interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical or other forms.
[0219] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0220] In addition, each functional unit in the embodiments provided in the present application can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.
[0221] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program codes.
[0222] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. In addition, the terms "first", "second", "third", etc. are only used for descriptive distinction and cannot be understood as indicating or implying relative importance.
[0223] Finally, it should be noted that the above-described embodiments are only specific implementation manners of the present application, used to illustrate the technical solutions of the present application, rather than limiting it. The protection scope of the present application is not limited thereto. Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: Any person skilled in the art within the technical scope disclosed by the present application can still modify the technical solutions described in the foregoing embodiments, or can easily think of changes, or perform equivalent replacements on some of the technical features; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application. All should be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims described.
Claims
1. A layout and routing method, characterized in that: include: According to the chip netlist file, obtain the operating frequencies of multiple module areas on the target chip; determining a first module area from the plurality of module areas according to the operating frequency; The congestion level of the logic cells in the first module area is increased, and the chip netlist file is updated to perform chip layout.
2. The method according to claim 1, characterized in that The step of determining a first module area from the plurality of module areas according to the operating frequency includes: A module area whose operating frequency is lower than a preset frequency threshold is determined from the multiple module areas as the first module area.
3. The method according to claim 1, characterized in that The step of determining a first module area from the plurality of module areas according to the operating frequency includes: According to the chip netlist file, obtaining the working frequencies of the multiple module areas; A module area among the multiple module areas, in which the operating frequency is higher than a preset frequency threshold but the operating frequency is lower than a preset frequency threshold, is determined as the first module area.
4. The method according to claim 1, characterized in that: The increasing the congestion level of the logic unit in the first module area includes: The distance between the logic cells in the first module area is reduced.
5. The method according to claim 1, characterized in that After increasing the congestion level of the logic unit in the first module area and updating the chip netlist file, the method further includes: After chip layout, the number of interface units in each module area is obtained according to the chip netlist file; determining a second module area from the plurality of module areas according to the number of the interface units; The wiring parameters of the second module area are adjusted to obtain target wiring parameters for chip wiring.
6. The method according to claim 5, characterized in that The step of determining a second module area from the plurality of module areas according to the number of the interface units comprises: Determining the congestion degree of the interface unit according to the size of the interface unit and the size of the layout space where the interface unit is located; The second module area is determined from the plurality of module areas according to the congestion level of the interface unit and the number of the interface units.
7. The method according to claim 6, characterized in that The determining the second module area from the plurality of module areas according to the congestion degree of the interface unit and the number of the interface units comprises: determining a third module area from the plurality of module areas according to the congestion level of the interface unit and the number of the interface units; Acquire a first voltage drop and / or a first flip rate of the third module region; The second module area is determined from the third module area according to the first voltage drop and / or the first switching rate.
8. The method according to claim 5, characterized in that The step of determining a second module area from the plurality of module areas according to the number of the interface units comprises: A module area in which the number of the interface units exceeds a preset number threshold is determined from the multiple module areas as the second module area.
9. The method according to claim 5, characterized in that The adjusting the wiring parameters of the second module area to obtain target wiring parameters includes: Acquire a second voltage drop and / or a second flipping rate of the second module region; If the second voltage drop does not exceed the first voltage drop threshold, and / or the second flipping rate does not exceed the first flipping rate threshold, adjust the wiring parameters of the second module area until the second voltage drop exceeds the first voltage drop threshold, and / or the second flipping rate exceeds the first flipping rate threshold, and determine the wiring parameters determined by the last adjustment as the target wiring parameters.
10. The method according to claim 5, characterized in that The method further comprises: After chip wiring, obtaining a third voltage drop and / or a third flipping rate of the first module area, and a fourth voltage drop and / or a fourth flipping rate of the second module area; If the third voltage drop exceeds the second voltage drop threshold, and / or the third flip rate exceeds the second flip rate threshold, reducing the congestion level of the logic unit in the first module area; If the fourth voltage drop exceeds the second voltage drop threshold, and / or the fourth flip rate exceeds the second flip rate threshold, then the wiring parameters of the second module area are readjusted.
11. The method according to claim 5, characterized in that The adjusting the wiring parameters of the second module area includes: The width of the power lines in the second module area is reduced, and / or the spacing between the power lines in the second module area is increased.
12. A layout and routing device, characterized in that: include: An acquisition module is used to acquire the operating frequencies of multiple module areas on a target chip according to a chip netlist file; A determination module, configured to determine a first module area from the plurality of module areas according to the operating frequency; The processing module is used to increase the congestion level of the logic unit in the first module area and update the chip netlist file to perform chip layout.
13. An electronic device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate via the bus, and the processor executes the machine-readable instructions to perform the method described in any one of claims 1 to 11.
14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 11 is executed.