Processor chip verification method, processor chip verification device, electronic equipment, computer storage medium and computer program product

Abstract

The embodiment of the invention provides a processor chip verification method, a processor chip verification device, electronic equipment, a computer storage medium and a computer program product. The processor chip verification method comprises the following steps: configuring a fetch field of a fetch register as a slice entry address of a slice entry instruction in a verification program, and configuring a permission state field of a permission state register as a slice entry privilege state corresponding to the slice entry instruction; responding to the slice entry privileged state, and sending a memory access request of at least one preorder instruction of the slice entry instruction; sending a jump request of an enabling field of the permission state register so as to enable an instruction fetching field of the instruction fetching register; and when a completion response of the memory access request is received, executing a reading operation for the slice entry address.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of chip verification technology, and in particular, to a processor chip verification method, a processor chip verification device, an electronic device, a computer storage medium, and a computer program product. Background Art

[0002] A chip verification platform is a collection of tools and systems used to evaluate and test the performance of processor chips, including but not limited to simulation platforms based on EDA software, simulation platforms based on emulators, prototype verification platforms based on FPGAs, etc. As a software engineering technology, program slicing can simplify and focus on specific aspects of the verification program by extracting partial program fragments related to specific functions or requirements.

[0003] At present, in chip verification schemes, the execution results of program slices of a chip verification program can be used to identify errors in processor chip design. Processor chip verification schemes based on program slicing have been widely used in a variety of chip verification platforms. Due to the functional limitations of different types of chip verification platforms, the entry recovery of the same program slice has different mechanisms, resulting in inconsistent slice entry recovery schemes and the inability to efficiently perform cross-chip platform verification. Summary of the invention

[0004] In view of this, embodiments of the present invention provide a processor chip verification method, a processor chip verification device, an electronic device, a computer storage medium, and a computer program product to solve the above problems.

[0005] According to a first aspect of an embodiment of the present invention, a processor chip verification method is provided, comprising: configuring an instruction fetch field of an instruction fetch register to be a slice entry address of a slice entry instruction in a verification program, and configuring a permission status field of a permission status register to be a slice entry privileged state corresponding to the slice entry instruction; in response to the slice entry privileged state, sending a memory access request for at least one preceding instruction of the slice entry instruction; sending a jump request for an enable field of the permission status register to enable the instruction fetch field of the instruction fetch register; and upon receiving a completion response to the memory access request, performing a read operation on the slice entry address.

[0006] In another implementation of the present invention, a jump request for the enable field of the permission status register is sent to enable the instruction fetch field of the instruction fetch register, including: in response to the slice entry privileged state, after sending the memory access request, a jump request for the enable field of the permission status register is sent, wherein the jump request indicates that the enable field jumps to a field value that enables the instruction fetch field of the instruction fetch register.

[0007] In another implementation of the present invention, in response to the slice entry privileged state, a memory access request for at least one preceding instruction of the slice entry instruction is sent, including: in response to the slice entry privileged state, determining at least one previous operand of at least one preceding instruction of the slice entry instruction; sending an address page table conversion request for the at least one previous operand for the memory to be accessed; and obtaining the physical address of the address page table conversion request as a completion response to the memory access request.

[0008] In another implementation of the present invention, in response to the slice entry privileged state, sending a memory access request for at least one preceding instruction of the slice entry instruction also includes: sending an address page table traversal request for the at least one previous operand for the memory to be accessed, so as to perform address page table conversion according to the request result of the address page table traversal request.

[0009] In another implementation of the present invention, the instruction fetch field of the instruction fetch register is configured as the slice entry address of the slice entry instruction in the verification program, including: parsing the previous instruction of the slice entry instruction in the verification program to obtain the physical address of the slice entry instruction; configuring the slice entry address as the physical address of the slice entry instruction to the instruction fetch field of the instruction fetch register.

[0010] In another implementation of the present invention, the processor chip verification method also includes: configuring the permission status field of the permission status register to be a non-slice entry privileged state of the subsequent instructions of the slice entry instruction in the verification program; in response to the non-slice entry privileged state, sending a jump request for the enable field of the permission status register to enable the instruction fetch field of the instruction fetch register.

[0011] In another implementation of the present invention, in response to the slice entry privileged state, after sending the memory access request, sending a jump request for the enable field of the permission status register, including: sending a jump request for the enable field of the permission status register according to the post-write barrier information of the slice entry privileged state, the post-write barrier information indicating that the jump request for the enable field is sent after sending the memory access request; upon receiving a completion response to the memory access request, performing a read operation on the slice entry address, including: performing a read operation on the slice entry address according to the pre-write barrier information of the slice entry privileged state, the pre-write barrier information indicating that the read operation is performed after receiving the completion response to the memory access request.

[0012] According to a second aspect of an embodiment of the present invention, a processor chip verification device is provided, comprising: a configuration unit, configured to configure an instruction fetch register and a permission status register in a processor chip, the instruction fetch register comprising an instruction fetch address, the permission status register comprising a permission status field and an enable field, the enable field being used to enable the instruction fetch field of the instruction fetch register; a verification unit, configured to configure the instruction fetch field of the instruction fetch register as a slice entry address of a slice entry instruction in a verification program, and to configure the permission status field of the permission status register as a slice entry privileged state corresponding to the slice entry instruction. The processor chip is used to respond to the slice entry privileged state, send a memory access request of at least one preceding instruction of the slice entry instruction, send a jump request of the enable field of the permission status register, and perform a read operation on the slice entry address when receiving a completion response to the memory access request.

[0013] According to a third aspect of an embodiment of the present invention, there is provided an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the method described in the first aspect.

[0014] According to a fourth aspect of an embodiment of the present invention, there is provided a computer storage medium on which a computer program is stored. When the program is executed by a processor, the method described in the first aspect is implemented.

[0015] According to a fifth aspect of an embodiment of the present invention, there is provided a computer program product, comprising computer instructions, which, when executed by a processor, implement the method as described in the first aspect.

[0016] In the scheme of the embodiment of the present invention, the instruction fetch field of the instruction fetch register can configure the slice entry address of the slice entry instruction, and is compatible with the instruction fetch processes of different chip verification platforms. In addition, the permission status field of the permission status register can be used to configure the slice entry privileged state of the slice entry instruction, and the enable field of the permission status register can enable the instruction fetch field of the instruction fetch register, thereby decoupling the entry recovery process and the subsequent process through the instruction fetch register and the permission status register, unifying the entry recovery schemes of different chip verification platforms, and efficiently performing cross-chip platform verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0018] Figure 1 Schematic diagram of some example chip verification platforms.

[0019] Figure 2 The figure is a flowchart of the steps of a processor chip verification method according to some embodiments of the present invention.

[0020] Figure 3 for Figure 2 A schematic interactive diagram of some example processor chip verification processes of the embodiments.

[0021] Figure 4 is a structural block diagram of a processor chip verification device according to some other embodiments of the present invention.

[0022] Figure 5 Based on Figure 4 A structural block diagram of a processor chip configuration of an embodiment.

[0023] Figure 6 Schematic diagram of the structure of electronic devices according to other embodiments of the present invention. DETAILED DESCRIPTION

[0024] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in the field based on the embodiments in the embodiments of the present invention should fall within the scope of protection of the embodiments of the present invention.

[0025] The specific implementation of the embodiment of the present invention is further described below in conjunction with the accompanying drawings of the embodiment of the present invention.

[0026] Generally speaking, processor chip verification schemes that use program slicing of verification programs have been widely used in a variety of chip verification platforms. Due to the functional limitations of different types of chip verification platforms, the entry recovery of the same program slice has different mechanisms, resulting in inconsistent slice entry recovery schemes and the inability to efficiently perform cross-chip platform verification.

[0027] In addition, when the verification program returns to the slice entry through the exception return instruction, for example, in the RISC-V (Fifth Generation Reduced Instruction Set Computing, Fifth Generation) chip simulation verification, if the exception return instruction is executed in the system kernel state of the processor chip, the exception return instruction will rewrite the register xEPC in the processor chip and change the state of xEPC. In addition, the exception return instruction may also change the permission status of the xSTATUS register. In other words, when the exception return instruction is executed in the system kernel state of the processor chip, the reliability of slice entry recovery is poor.

[0028] Figure 1 Schematic diagram of some example chip verification platforms. Figure 1 As shown, the chip verification platform 100 includes a processor chip 110 and a chip verification logic 120. The processor chip 110 includes an instruction fetch unit 10, an instruction translation unit 20, an instruction reordering unit 30, a memory access unit 40, a memory management unit 50 and a register maintenance unit 60 as instruction function units.

[0029] Specifically, the instruction fetch unit 10 is used to obtain an instruction stream from the memory of the verification program, read the instruction according to the address specified by the program counter (PC), and send it to the subsequent stage of the processor chip 110. The instruction translation unit 20 is used to convert the instruction obtained by the instruction fetch unit 10 from a machine code into an internal form that can be recognized by the processor chip 110. The instruction translation unit 20 parses the opcode used to determine the type of instruction and the operands used for the execution unit to execute. The instruction reordering unit 30 is used for out-of-order execution and reordering of instructions, ensuring that the instructions are executed in the correct order without violating the semantics of the program to maintain the correctness of the program. The memory access unit 40 is used to load data from the memory or other storage medium for execution by the processor chip 110. The memory management unit 50 is used for virtual memory management, including address translation, page table management, cache consistency, etc. The memory management unit 50 converts virtual addresses into physical addresses, processes memory access requests, and manages memory protection and permissions. The register maintenance unit 60 is used to manage the registers in the processor chip 110, including register read and write operations, data transfer between registers, etc., to ensure that the data in the registers is the latest data and to correctly and timely update the register values ​​during instruction execution.

[0030] In addition, the chip verification logic 120 based on program slicing is used in the chip verification platform 100 to verify the function and performance of the processor chip by analyzing the execution results of the verification program.

[0031] Specifically, the chip verification logic 120 can link the program slice (for example, the slice assembly code) with the test firmware to generate an executable file, and the processor chip executes the executable file to reproduce the entire execution process of the program slice. In other words, the chip verification logic 120 verifies the chip through the verification program to ensure that it can correctly execute key functions in actual operation, while reducing the time and resources required for verification. During the verification process, the processor chip 110, through the various instruction function units included in it, records the executed instruction code and the state of the memory and registers in the simulator at that time during the execution phase of the program slice to help identify the behavior of the processor chip when executing the verification program.

[0032] For example, the simulation model can be used to select specific parts with higher weights in a specified program to generate feature fragments that characterize the key execution path of the verification program. Sliced ​​assembly code can be generated as program slices based on the feature fragments. The sliced ​​assembly code contains the field information of the processor (for example, the process of restoring the context register, the memory read and written by the sliced ​​program, memory loading instructions, and all recorded function symbol information).

[0033] Further, Figure 2 The processor chip verification method according to some embodiments of the present invention is shown. Specifically, the processor chip verification method can be executed using a chip verification platform, and the processor chip verification method includes:

[0034] Step S210: configure the instruction fetch field of the instruction fetch register to the slice entry address of the slice entry instruction in the verification program, and configure the permission status field of the permission status register to the slice entry privileged state corresponding to the slice entry instruction.

[0035] It should be understood that the instruction fetch register can be used to store the address of the instruction currently to be executed. By configuring the instruction fetch field as the slice entry address, it can ensure that the processor chip can obtain the machine code of the slice entry instruction in the next instruction fetch to start executing the slice entry instruction.

[0036] It should also be understood that the permission status register is used to control the privilege level of the processor chip, and by configuring the permission status field to the slice entry privilege state, it ensures that the slice entry instruction can be executed at the correct privilege level to access the required resources and perform the required operations.

[0037] Step S220: In response to the slice entry privileged state, a memory access request of at least one preceding instruction of the slice entry instruction is sent.

[0038] It should be understood that the processor chip can perform some special operations when in the slice entry privileged state. For example, in the slice entry privileged state, the processor chip can suspend the decoding of subsequent instructions of the slice entry instruction and send a memory access request for the preceding instruction of the slice entry instruction.

[0039] It should also be understood that the preamble instruction refers to the instruction that needs to be executed before the slice entry instruction. Sending the memory access request for these instructions can ensure that before executing the slice entry instruction, the necessary data and instructions have been loaded into the cache or register of the processor chip to ensure that the slice entry instruction can be executed smoothly.

[0040] Step S230: Send a jump request of the enable field of the permission status register to enable the instruction fetch field of the instruction fetch register.

[0041] It should be understood that the enable field of the permission status register is used to control whether the instruction fetch field of the instruction fetch register can be activated. Sending a jump request can activate the instruction fetch field of the instruction fetch register so that it can perform an instruction fetch operation according to the configured slice entry address.

[0042] In addition, by enabling the instruction fetch field of the instruction fetch register, the processor chip can obtain the machine code of the slice entry instruction according to the slice entry address stored in the instruction fetch register to start executing the slice entry instruction.

[0043] Step S240: When a completion response to the memory access request is received, a read operation is performed on the slice entry address.

[0044] It should be understood that after sending the memory access request of the preceding instruction, the processor chip can wait for the completion response of the memory access request, and the completion response indicates that the memory access operation has been successfully completed, that is, the data and instructions required for the memory access process have been loaded into the processor's cache or register.

[0045] In addition, after confirming that the memory access request has been completed and the required data and instructions are ready, the processor chip can perform a read operation for the slice entry address, that is, read the machine code of the slice entry instruction from the memory to start executing the slice entry instruction as the correct instruction code.

[0046] In the scheme of the embodiment of the present invention, the instruction fetch field of the instruction fetch register can configure the slice entry address of the slice entry instruction, and is compatible with the instruction fetch processes of different chip verification platforms. In addition, the permission status field of the permission status register can be used to configure the slice entry privileged state of the slice entry instruction, and the enable field of the permission status register can enable the instruction fetch field of the instruction fetch register, thereby decoupling the entry recovery process and the subsequent process through the instruction fetch register and the permission status register, unifying the entry recovery schemes of different chip verification platforms, and efficiently executing cross-processor chip platform verification.

[0047] In some embodiments, the field attributes of the instruction fetch register are shown in Table 1:

[0048] Table 1

[0049]

[0050] That is, the instruction fetch register includes an instruction fetch field (e.g., [0]), the field attributes of the instruction fetch field include speculative read, speculative write, out-of-order read, and out-of-order write, and do not include a write barrier before, a write barrier after, and a re-fetch instruction.

[0051] Specifically, speculative reads allow instruction registers to be read without guaranteeing data validity. That is, a read operation may return an uncertain value. Speculative writes do not allow instruction registers to be written without guaranteeing data validity to ensure data correctness and consistency. Out-of-order reads allow read operations to be performed out of the original order of instructions to improve the parallelism and performance of the processor while ensuring data consistency. Out-of-order writes do not allow write operations to be performed out of the original order of instructions to ensure the sequentiality of write operations. A pre-write barrier is None, indicating that a memory barrier does not need to be set before a write operation to ensure sequentiality. A post-write barrier is None, indicating that a memory barrier does not need to be set after a write operation to ensure sequentiality. Re-fetch is None, indicating that re-fetching is not required after executing an instruction register operation.

[0052] Furthermore, the field attributes of the permission status register are shown in Table 2:

[0053] Table 2

[0054]

[0055] That is, the permission status register includes a permission status field (e.g., [3:1]) and an enable field (e.g., [0]). The field attributes of the permission status field include speculative read, speculative write, out-of-order read, and out-of-order write, and do not include write barrier before, write barrier after, and re-fetch instruction. The field attributes of the enable field include speculative read, speculative write, out-of-order read, out-of-order write, write barrier before, write barrier after, and re-fetch instruction.

[0056] For example, the various state modes of the permission status field can be determined by the bit combination of the permission status field, and can be divided into a slice entry privileged state and a non-slice entry privileged state. For example, the various state modes include UMode (user mode), HSMode (hardware supervisor mode), MMode (machine mode), VUMode (virtual user mode), VSMode (virtual supervisor mode), etc. Among them, the slice entry privileged state can be any one of the hardware supervisor mode or the machine mode. The non-slice entry privileged state can be any one of the user mode, the virtual user mode, and the virtual supervisor mode.

[0057] Specifically, user mode may have the lowest privilege level and is used to run user applications. In user mode, programs cannot directly access hardware resources or execute some privileged instructions. Machine mode has the highest privilege level and has access to all resources. It is usually used to run firmware and operating system kernels. The privilege level of hardware manager mode is higher than that of user mode and lower than that of machine mode. It is used to manage hardware resources and perform some management tasks. Hardware manager mode can be used for hardware managers or certain specific hardware drivers. Virtual user mode is a user mode in a virtualized environment, which allows user programs in virtual machines to run and is equivalent to user mode on a physical machine. Virtual manager mode is a manager mode in a virtualized environment, which is used to manage the operating environment of virtual machines and is equivalent to manager mode on a physical machine.

[0058] Specifically, for the permission status field, speculative read allows the permission status field to be read without guaranteeing the validity of the data. That is, the read operation may return an uncertain value. Speculative write does not allow the permission status field to be written without guaranteeing the validity of the data to ensure the correctness and consistency of the data. Out-of-order read allows the read operation to be performed out of the original order of the instructions to improve the parallelism and performance of the processor while ensuring the consistency of the data. Out-of-order write does not allow the write operation to be performed out of the original order of the instructions to ensure the sequentiality of the write operation. The pre-write barrier is none, indicating that a memory barrier does not need to be set before the write operation to ensure sequentiality. The post-write barrier is none, indicating that a memory barrier does not need to be set after the write operation to ensure sequentiality. Re-instruction fetch is none, indicating that re-instruction fetch is not required after executing the permission status field operation.

[0059] In addition, for the enable field, speculative read is not allowed. The enable field is not allowed to be read under uncertain circumstances. Speculative write is not allowed. The enable field is not allowed to be written under uncertain circumstances. The read operation of the out-of-order read is not allowed. The read operation of the enable field must be performed in the order of instructions. The write operation of the out-of-order write is not allowed. The write operation of the enable field must be performed in the order of instructions. The write-before barrier is yes, indicating that a memory barrier needs to be set before the write operation to ensure that the previous write operation has been completed. The write-after barrier is yes, indicating that a memory barrier needs to be set after the write operation to ensure that the result of the write operation has been stable. Re-instruction fetch is yes, indicating that the instruction needs to be re-fetched after executing the register operation to ensure the correct execution of the instruction.

[0060] In other embodiments, as an example of sending a jump request for the enable field of the permission status register, the instruction reordering unit may respond to the slice entry privilege state, and after sending a memory access request, send a jump request for the enable field of the permission status register, wherein the jump request indicates that the enable field jumps to the field value of the instruction fetch field of the instruction fetch enable register. In other words, the jump request for the enable field is sent after the memory access request of at least one preceding instruction, thereby avoiding the execution error of the slice entry instruction caused by the incomplete memory access process of at least one preceding instruction, and then when the enable field jumps to the field value of the instruction fetch field of the instruction fetch enable register, the read operation for the slice entry address is reliably performed.

[0061] In other embodiments, as an example of sending a memory access request for at least one predecessor instruction of a slice entry instruction in response to a slice entry privileged state, the instruction reordering unit can obtain the slice entry privileged state from the permission status register, determine at least one previous operand of at least one predecessor instruction of the slice entry instruction in response to the slice entry privileged state, and then, send an address page table conversion request for the at least one previous operand to the memory to be accessed, and then, obtain the physical address of the address page table conversion request as a completion response to the memory access request.

[0062] It should be understood that the address page table conversion is used to map the virtual address to the physical address, and the address page table conversion can be initiated by the memory access unit and executed via the operation of the memory management unit (MMU). When the prologue instruction accesses the memory, the memory access unit initiates an address page table conversion request to convert the virtual address to a physical address.

[0063] That is, the jump request of the enable field is sent after the address page table conversion request of at least one previous operand, thereby avoiding the execution error of the slice entry instruction caused by the incomplete address page table conversion process of at least one previous operand.

[0064] Further, as a parallel operation with sending an address page table conversion request, or in response to an address page table conversion request, the instruction reordering unit may send an address page table traversal request for at least one previous operand for the memory to be accessed, so as to perform the address page table conversion according to the request result of the address page table traversal request.

[0065] It should be understood that the address page table traversal operation (TableWalk) can be performed by the memory management unit. During the page table conversion process, the address page table traversal can be performed.

[0066] That is to say, the address page table conversion process is executed according to the address page table traversal requested by the address page table traversal request, further avoiding the execution error of the slice entry instruction caused by the incomplete address page table conversion process.

[0067] In other embodiments, as an example of configuring the instruction fetch field of the instruction fetch register as the slice entry address of the slice entry instruction in the verification program, the decoding unit can parse the previous instruction of the slice entry instruction in the verification program to obtain the physical address of the slice entry instruction, and then configure the slice entry address as the physical address of the slice entry instruction to the instruction fetch field of the instruction fetch register through the register maintenance unit. In other words, configuring the slice entry address to the instruction fetch field of the instruction fetch register is compatible with the function of the instruction fetch field of the instruction fetch register.

[0068] Alternatively, the instruction reorder unit may configure the permission status field of the permission status register to be a non-slice entry privileged state for subsequent instructions of the slice entry instruction in the verification program, and accordingly, the instruction reorder unit responds to the non-slice entry privileged state by sending a jump request for the enable field of the permission status register to enable the instruction fetch field of the instruction fetch register.

[0069] Without loss of generality, in the case of a subsequent instruction of the slice entry instruction, the instruction reordering unit may notify the register maintenance unit to configure the permission status field of the permission status register to a non-slice entry privileged state of the subsequent instruction of the slice entry instruction in the verification program. In the case of a slice entry instruction, the instruction reordering unit may notify the register maintenance unit to configure the permission status field of the permission status register to a slice entry privileged state of the slice entry instruction in the verification program.

[0070] That is to say, in the non-slice entry privileged state, there is no need to send a memory access request for the predecessor instruction of the subsequent instruction before the jump request of the enable field. By directly sending the jump request of the enable field, the execution efficiency of the processor chip program is improved.

[0071] Furthermore, as an example of sending a jump request for the enable field of the permission status register, a jump request for the enable field of the permission status register can be sent according to the post-write barrier information of the slice entry privilege state, and the post-write barrier information indicates that the jump request for the enable field is sent after the memory access request is sent. Accordingly, as an example of performing a read operation on the slice entry address, a read operation on the slice entry address can be performed according to the pre-write barrier information of the slice entry privilege state, and the pre-write barrier information indicates that the read operation is performed after receiving the completion response of the memory access request.

[0072] The following will be combined Figure 3 To describe in detail Figure 2 A schematic interactive diagram of some example processor chip verification processes of the embodiments. Figure 3 The processor chip verification process includes:

[0073] Step S310: Suspend decoding of subsequent instructions of the slice entry instruction. It should be understood that when processing the slice entry instruction, the processor chip (for example, through the suspend / resume module in the decoding unit) can suspend decoding of other instructions after the slice entry instruction so that the system kernel can correctly process the slice entry instruction and avoid conflicts with other preceding instructions or instruction execution errors. For example, the instruction reordering unit can control the instruction translation unit to suspend decoding of subsequent instructions of the slice entry instruction based on the write-behind barrier information of the slice entry privileged state.

[0074] Step S320: Sending an address page table conversion request for at least one previous operand for the memory to be accessed. It should be understood that the address page table conversion is used to map the virtual address to the physical address, and the address page table conversion can be initiated by the memory access unit and performed via the operation of the memory management unit (MMU). When the preceding instruction accesses the memory, the memory access unit initiates an address page table conversion request to convert the virtual address to the physical address.

[0075] Step S330: Sending an address page table traversal request for at least one previous operand for the memory to be accessed. The address page table traversal operation (TableWalk) may be performed by the memory management unit. During the page table conversion process, the address page table traversal may be performed.

[0076] Step S340: Send a jump request for the enable field of the permission status register, wherein the jump request indicates that the enable field jumps to the field value of the instruction fetch field of the instruction fetch register. It should be understood that in the permission status register, the permission status field is associated with the enable field. When the permission status field indicates the slice entry privileged state, the jump of the enable field instructs the permission status register to update the field value of the instruction fetch field of the instruction fetch register to be compatible with the instruction execution rules of the instruction fetch register. For example, a jump request for the enable field of the permission status register can be sent based on the post-write barrier information of the slice entry privileged state, and the post-write barrier information indicates that a jump request for the enable field is sent after sending a memory access request.

[0077] Step S350: receiving a jump response to the enable field sent by the permission status register. It should be understood that the instruction reordering unit receives the jump response sent by the permission status register, and after receiving the jump response, the life cycle of the write-behind barrier information in the slice entry privileged state ends.

[0078] Step S360: receiving an address page table conversion completion response of the address page table conversion request. It should be understood that the memory access unit executes the address page table conversion request, obtains the previous operand by accessing the memory, and generates an address page table conversion completion response when the previous operand is obtained. For example, the memory access unit sends the virtual address of the previous operand to the memory management unit, obtains the physical address of the previous operand, and then reads the previous operand from the memory to be accessed according to the physical address.

[0079] Step S370: Receive an address page table traversal completion response of the address page table traversal request. It should be understood that the address page table traversal completion response can be obtained before the address page table conversion completion response, or it can be obtained after the address page table conversion completion response. Through the address page table traversal request, the address page table traversal can be performed on the previous operands that have not been processed in the memory management unit, or the address page table traversal can be performed according to the address page table traversal request sent by the memory access unit in response to the address page table conversion request, and then the address page table traversal completion response is returned to the instruction reordering unit.

[0080] Step S380: Resume decoding of subsequent instructions of the slice entry instruction. It should be understood that after the life cycle of the post-write barrier information ends, the instruction reordering unit resumes decoding of subsequent instructions of the slice entry instruction (for example, through a suspend / resume module in the decoding unit), and the system kernel will continue to process the previously suspended slice entry instruction and subsequent instructions of the verification program.

[0081] Step S390: Execute a read operation for the slice entry address. It should be understood that the instruction reordering unit accesses the instruction fetch unit so that the instruction fetch unit obtains the slice entry instruction from the memory according to the slice entry address. The system kernel will perform a read operation according to the slice entry address to obtain the required data. This is the ultimate purpose of the slice operation, that is, to obtain data at a specific address for subsequent processing. For example, according to the write-before barrier information of the slice entry privileged state, a read operation is performed on the slice entry address, and the write-before barrier information indicates that the read operation is performed after receiving the completion response of the memory access request.

[0082] The following will be combined Figure 4 1 and 2 are used to describe a structural block diagram of a processor chip verification device according to another embodiment of the present invention. Specifically, the processor chip verification device may be configured with Figure 1 The chip verification logic 120 includes:

[0083] The configuration unit 410 is used to configure an instruction fetch register and a permission status register in the processor chip, wherein the instruction fetch register includes an instruction fetch address, and the permission status register includes a permission status field and an enable field, wherein the enable field is used to enable the instruction fetch field of the instruction fetch register.

[0084] The verification unit 420 is used to configure the instruction fetch field of the instruction fetch register to the slice entry address of the slice entry instruction in the verification program, and configure the permission status field of the permission status register to the slice entry privileged state corresponding to the slice entry instruction.

[0085] The processor chip is used to respond to the slice entry privileged state, send a memory access request for at least one preceding instruction of the slice entry instruction, send a jump request for the enable field of the permission status register, and upon receiving a completion response to the memory access request, perform a read operation on the slice entry address.

[0086] Specifically, Figure 5 In the processor chip shown, the instruction fetch unit 10 is used to obtain the instruction stream from the memory of the verification program, read the instruction according to the address specified by the program counter (PC), and send it to the subsequent stage of the processor chip 110. The instruction translation unit 20 is used to convert the instruction fetched by the instruction fetch unit 10 from the machine code to the internal form that the processor chip 110 can recognize. The instruction translation unit 20 parses the opcode used to determine the type of instruction and the operands used for the execution unit to execute. The instruction reordering unit 30 is used for out-of-order execution and reordering of instructions, ensuring that the instructions are executed in the correct order without violating the semantics of the program to maintain the correctness of the program. The memory access unit 40 is used to load data from the memory or other storage medium for execution by the processor chip 110. The memory management unit 50 is used for virtual memory management, including address translation, page table management, cache consistency, etc. The memory management unit 50 converts virtual addresses into physical addresses, processes memory access requests, and manages memory protection and permissions. The register maintenance unit 60 is used to manage the registers in the processor chip 110, including register read and write operations, data transfer between registers, etc., to ensure that the data in the registers is the latest data and to correctly and timely update the register values ​​during instruction execution.

[0087] In the scheme of the embodiment of the present invention, the instruction fetch field of the instruction fetch register can configure the slice entry address of the slice entry instruction, and is compatible with the instruction fetch processes of different chip verification platforms. In addition, the permission status field of the permission status register can be used to configure the slice entry privileged state of the slice entry instruction, and the enable field of the permission status register can enable the instruction fetch field of the instruction fetch register, thereby decoupling the entry recovery process and the subsequent process through the instruction fetch register and the permission status register, unifying the entry recovery schemes of different chip verification platforms, and efficiently executing cross-processor chip platform verification.

[0088] In other embodiments, the instruction reordering unit is specifically used to: respond to the slice entry privileged state, after sending the memory access request, send a jump request for the enable field of the permission status register, wherein the jump request indicates that the enable field jumps to enable the field value of the instruction fetch field of the instruction fetch register.

[0089] In some other embodiments, the instruction reordering unit is specifically used to: respond to the slice entry privileged state, determine at least one previous operand of at least one preceding instruction of the slice entry instruction; send an address page table conversion request for the at least one previous operand to the memory to be accessed; and obtain the physical address of the address page table conversion request as a completion response to the memory access request.

[0090] In some other embodiments, the instruction reordering unit is further used to: send an address page table traversal request for the at least one previous operand to the memory to be accessed, so as to perform address page table conversion according to a request result of the address page table traversal request.

[0091] In some other embodiments, the configuration unit is specifically used to: parse the previous instruction of the slice entry instruction in the verification program to obtain the physical address of the slice entry instruction; and configure the slice entry address as the physical address of the slice entry instruction to the instruction fetch field of the instruction fetch register.

[0092] In other embodiments, the register maintenance unit is also used to: configure the permission status field of the permission status register to a non-slice entry privileged state for subsequent instructions of the slice entry instruction in the verification program; and in response to the non-slice entry privileged state, send a jump request for the enable field of the permission status register to enable the instruction fetch field of the instruction fetch register.

[0093] In some other embodiments, the instruction reordering unit is specifically used to: send a jump request for the enable field of the permission status register according to the post-write barrier information of the privileged state of the slice entry, and the post-write barrier information indicates that the jump request for the enable field is sent after the memory access request is sent; and perform a read operation on the slice entry address according to the pre-write barrier information of the privileged state of the slice entry, and the pre-write barrier information indicates that the read operation is performed after receiving a completion response to the memory access request.

[0094] It should be understood that the specific implementation of each module in the chip verification device can refer to the corresponding description of the corresponding steps in the above-mentioned chip verification method embodiment, and has corresponding beneficial effects, which will not be repeated here. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the chip verification device and module described above can refer to the corresponding process description in the chip verification method embodiment, which will not be repeated here.

[0095] Reference Figure 6 , shows a schematic structural diagram of an electronic device according to another embodiment of the present invention. The specific embodiment of the present invention does not limit the specific implementation of the electronic device.

[0096] like Figure 6 As shown, the electronic device may include: a processor (processor) 602 for executing a program 610 , a communication interface (Communications Interface) 604 , a memory (memory) 606 , and a communication bus 608 .

[0097] The processor, the communication interface, and the memory communicate with each other via a communication bus.

[0098] Communication interface, used to communicate with other electronic devices or servers.

[0099] The processor is used to execute the program, and specifically can execute the relevant steps in the above method embodiment.

[0100] Specifically, the program may include program codes including computer operation instructions.

[0101] The processor may be a CPU, or an application specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present invention. The one or more processors included in the smart device may be processors of the same type, such as one or more CPUs; or processors of different types, such as one or more CPUs and one or more ASICs.

[0102] The memory is used to store programs. The memory may include a high-speed RAM memory, and may also include a non-volatile memory, such as at least one disk memory.

[0103] The program may include multiple computer instructions. Specifically, the program may enable a processor to execute the chip verification method described in any one of the aforementioned method embodiments through the multiple computer instructions.

[0104] The specific implementation of each step in the program can refer to the corresponding description of the corresponding steps, modules or units in the above method embodiments, and has corresponding beneficial effects, which will not be repeated here. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the above-described device, equipment or module can refer to the corresponding process description in the above method embodiments, which will not be repeated here.

[0105] The embodiment of the present invention further provides a computer storage medium on which a computer program is stored, and when the program is executed by a processor, the method described in any of the above-mentioned multiple method embodiments is implemented. The computer storage medium includes, but is not limited to: a compact disc read-only memory (CD-ROM), a random access memory (RAM), a floppy disk, a hard disk or a magneto-optical disk, etc.

[0106] An embodiment of the present invention further provides a computer program product, including computer instructions, which instruct a computing device to execute the chip verification method in the above-mentioned multiple method embodiments.

[0107] In addition, it should be noted that the user-related information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data used to train the model, data used for analysis, stored data, displayed data, etc.) involved in the embodiments of the present invention are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with relevant regulations and standards, and corresponding operation entrances are provided for users to choose to authorize or refuse.

[0108] It should be pointed out that, according to the needs of implementation, the various components / steps described in the embodiments of the present invention can be split into more components / steps, or two or more components / steps or partial operations of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of the present invention.

[0109] The above-mentioned method according to the embodiment of the present invention can be implemented in hardware, firmware, or implemented as software or computer code that can be stored in a recording medium (such as a CD-ROM, RAM, floppy disk, hard disk or magneto-optical disk), or implemented as a computer code originally stored in a remote recording medium or a non-temporary machine-readable medium downloaded through a network and to be stored in a local recording medium, so that the method described herein can be stored in such software processing on a recording medium using a general-purpose computer, a dedicated processor or programmable or dedicated hardware (such as an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA)). It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component (e.g., a random access memory (RAM), a read-only memory (ROM), a flash memory, etc.) that can store or receive software or computer code, and when the software or computer code is accessed and executed by a computer, a processor or hardware, the method described herein is implemented. In addition, when a general-purpose computer accesses the code for implementing the method shown here, the execution of the code converts the general-purpose computer into a dedicated computer for executing the method shown here.

[0110] Those of ordinary skill in the art will appreciate that the units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present invention.

[0111] The above implementation methods are only used to illustrate the embodiments of the present invention, and are not limitations of the embodiments of the present invention. Ordinary technicians in the relevant technical field may make various changes and modifications without departing from the spirit and scope of the embodiments of the present invention. Therefore, all equivalent technical solutions also belong to the scope of the embodiments of the present invention. The patent protection scope of the embodiments of the present invention should be defined by the claims.

Claims

1. A processor chip verification method, comprising: The instruction fetch field of the instruction fetch register is configured as a slice entry address of a slice entry instruction in the verification program, and the permission status field of the permission status register is configured as a slice entry privilege state corresponding to the slice entry instruction; In response to the slice entry privileged state, sending a memory access request of at least one preceding instruction of the slice entry instruction; Sending a jump request of the enable field of the permission status register to enable the instruction fetch field of the instruction fetch register; When a completion response to the memory access request is received, a read operation is performed on the slice entry address.

2. The method according to claim 1, wherein: Sending a jump request of the enable field of the permission status register to enable the instruction fetch field of the instruction fetch register includes: In response to the slice entry privileged state, after sending the memory access request, a jump request for the enable field of the permission status register is sent, wherein the jump request indicates that the enable field jumps to a field value that enables the instruction fetch field of the instruction fetch register.

3. The method according to claim 1, wherein: In response to the slice entry privileged state, sending a memory access request of at least one preceding instruction of the slice entry instruction includes: In response to the slice entry privileged state, determining at least one previous operand of at least one predecessor instruction of the slice entry instruction; Sending a page table translation request for the at least one previous operand to the address of the memory to be accessed; The physical address of the address page table conversion request is obtained as a completion response of the memory access request.

4. The method according to claim 3, wherein: In response to the slice entry privileged state, sending a memory access request of at least one preceding instruction of the slice entry instruction also includes: An address page table traversal request for the at least one previous operand to the memory to be accessed is sent to perform address page table conversion according to a request result of the address page table traversal request.

5. The method according to claim 1, wherein: The instruction fetch field of the instruction fetch register is configured as the slice entry address of the slice entry instruction in the verification program, including: Parsing the previous instruction of the slice entry instruction in the verification program to obtain the physical address of the slice entry instruction; The slice entry address is configured as the physical address of the slice entry instruction to the instruction fetch field of the instruction fetch register.

6. The method according to claim 5, wherein: The method further comprises: configuring a privilege status field of a privilege status register to a non-slice entry privileged state of a subsequent instruction of the slice entry instruction in the verification program; In response to the non-slice entry privileged state, a jump request for the enable field of the permission status register is sent to enable the instruction fetch field of the instruction fetch register.

7. The processing device according to claim 2, wherein: In response to the slice entry privileged state, after sending the memory access request, sending a jump request of the enable field of the permission status register, comprising: Sending a jump request for an enable field of the permission status register according to the post-write barrier information of the slice entry privileged state, wherein the post-write barrier information indicates that the jump request for the enable field is sent after the memory access request is sent; Upon receiving a completion response to the memory access request, performing a read operation on the slice entry address, including: According to the write-before barrier information of the slice entry privileged state, a read operation is performed on the slice entry address, and the write-before barrier information indicates that the read operation is performed after receiving a completion response to the memory access request.

8. A processor chip verification device, comprising: A configuration unit, configured to configure an instruction fetch register and a permission status register in a processor chip, wherein the instruction fetch register includes an instruction fetch address, and the permission status register includes a permission status field and an enable field, wherein the enable field is used to enable the instruction fetch field of the instruction fetch register; a verification unit, configured to configure the instruction fetch field of the instruction fetch register as a slice entry address of a slice entry instruction in a verification program, and to configure the permission status field of the permission status register as a slice entry privileged state corresponding to the slice entry instruction; Among them, the processor chip is used to respond to the slice entry privileged state, send a memory access request for at least one preceding instruction of the slice entry instruction, send a jump request for the enable field of the permission status register, and upon receiving a completion response to the memory access request, perform a read operation on the slice entry address.

9. An electronic device, comprising: A processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the method according to any one of claims 1-7.

10. A computer storage medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the method according to any one of claims 1 to 7.

11. A computer program product, comprising computer instructions, which implement the method according to any one of claims 1 to 7 when executed by a processor.

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