AI chip architecture design method based on protein network and AI chip

Abstract

The invention provides an AI chip architecture design method based on a protein network and an AI chip. The method comprises the steps of obtaining protein structure data of human brain neuron connection, simulating the human brain neuron connection, constructing to obtain a protein network model, and calculating to obtain connection strength and a signal transmission mechanism between neurons; mapping connection strength and a signal transmission mechanism to a programmable resource of the FPGA, and dynamically adjusting a chip architecture through a configuration file updating mechanism of the FPGA; the protein network model is divided into a plurality of sub-networks, and the sub-networks are distributed to different calculation units for parallel processing; and dynamically adjusting the connection strength between neurons and a signal transmission mechanism according to input data and constraint conditions by adopting an adaptive learning algorithm, and carrying out performance evaluation on the adjusted chip architecture to obtain an AI chip architecture which passes the evaluation. According to the method, energy consumption can be reduced, the energy efficiency ratio and parallelism can be improved, and the architecture and functions can be dynamically adjusted through adaptive learning.

Description

Technical Field

[0001] The present invention relates to the technical field of artificial intelligence chip design, and particularly to an AI chip architecture design method based on a protein network. Background Art

[0002] With the rapid development of artificial intelligence technology, its applications in various fields are becoming increasingly widespread, including but not limited to intelligent transportation, medical diagnosis, smart home, industrial automation, natural language processing, image recognition, etc. These applications pose extremely high requirements for computing power, energy efficiency, and real-time performance. Traditional computing architectures, such as CPUs and GPUs based on the von Neumann architecture, gradually expose the following problems when dealing with complex artificial intelligence tasks:

[0003] First, the energy efficiency problem: Traditional chips face problems of excessive power consumption and difficult heat dissipation when executing large-scale parallel computing tasks. For example, the training and inference of deep learning models require a large amount of computing resources, and the energy efficiency ratio of traditional chips is difficult to meet the needs of actual applications.

[0004] Second, insufficient parallelism: Traditional computing architectures are difficult to fully utilize the advantages of parallel computing when dealing with complex neural network models. The calculations of neural networks usually involve a large number of matrix operations and non-linear activation functions, and the serial processing method of traditional architectures limits the improvement of computing efficiency.

[0005] Third, poor flexibility and reconfigurability: Once the design of traditional chips is completed, it is difficult to dynamically adjust their functions and architectures according to different application scenarios. This makes it difficult for chips to achieve efficient resource utilization and performance optimization when facing changing artificial intelligence tasks.

[0006] Therefore, there is an urgent need for an AI chip architecture design method that can perform adaptive learning, reduce power consumption, and dynamically adjust the architecture and functions according to different task requirements. Summary of the Invention

[0007] Based on this, it is necessary to provide an AI chip architecture design method and an AI chip based on a protein network for the above technical problems.

[0008] A method for designing an AI chip architecture based on a protein network, comprising the following steps: obtaining protein structure data of human brain neuron connections, simulating human brain neuron connections based on the protein structure data, and constructing a protein network model; obtaining the connection strength and signal transmission mechanism between neurons based on the protein network model; mapping the connection strength and signal transmission mechanism of the neurons to the programmable resources of an FPGA, and performing dynamic adjustment of the chip architecture through the configuration file update mechanism of the FPGA; dividing the protein network model into multiple sub-networks, and allocating each sub-network to different computing units for parallel processing; adopting an adaptive learning algorithm to dynamically adjust the connection strength and signal transmission mechanism between neurons according to input data and constraint conditions, and performing performance evaluation on the adjusted chip architecture to obtain an AI chip architecture that passes the evaluation.

[0009] In one embodiment, the obtaining protein structure data of human brain neuron connections, simulating human brain neuron connections based on the protein structure data, and constructing a protein network model includes: collecting protein structure data of human brain neuron connections; generating a protein network topology structure for simulating human brain neuron connections through a computational simulation method according to the protein structure data; optimizing the protein network topology structure to obtain a protein network model, and the formula is:

[0010]

[0011] In the formula, E represents an energy function, w ij represents the connection strength between neuron i and neuron j, and y i and y j represent the outputs of neuron i and neuron j respectively.

[0012] In one embodiment, the obtaining the connection strength and signal transmission mechanism between neurons based on the protein network model includes: obtaining the connection strength between neurons based on the protein network model, and it is:

[0013]

[0014] In the formula, w ij represents the connection strength between neuron i and neuron j, s i and s j represent the activation states of neuron i and neuron j respectively, and k is a regulation parameter; the signal transmission mechanism is:

[0015]

[0016] In the formula, y i represents the output of neuron i, and x jDenotes the input of neuron j, b i Denotes the bias of neuron i, and f is the activation function.

[0017] In one embodiment, the protein network model is divided into multiple sub-networks, and each sub-network is assigned to a different computing unit for parallel processing. The formula for parallel processing is:

[0018]

[0019] In the formula, C represents the parallel computing result.

[0020] In one embodiment, the calculation formula of the adaptive learning algorithm is:

[0021] Δw ij = η·(y i - t i )·x j ;

[0022] In the formula, Δw ij Denotes the adjustment amount of the connection strength, η denotes the learning rate, and t i Denotes the target output.

[0023] In one embodiment, the performance evaluation of the adjusted chip architecture is carried out according to the formula:

[0024]

[0025] In the formula, P represents the performance index, T represents the time step, C t Denotes the amount of computation at the t-th time step, and E t Denotes the energy consumption at the t-th time step.

[0026] An AI chip based on a protein network, designed by using an AI chip architecture design method as described above, includes: a protein network model construction module, configured to obtain protein structure data of human brain neuron connections, simulate human brain neuron connections based on the protein structure data, and construct a protein network model; a neuron information acquisition module, configured to obtain connection strengths and signal transmission mechanisms between neurons based on the protein network model; a chip architecture adjustment module, configured to map the connection strengths and signal transmission mechanisms of neurons to programmable resources of an FPGA, and perform dynamic adjustment of the chip architecture through a configuration file update mechanism of the FPGA; a parallel processing module, configured to divide the protein network model into multiple sub-networks and allocate each sub-network to different computing units for parallel processing; and an adaptive learning module, configured to adopt an adaptive learning algorithm, dynamically adjust connection strengths and signal transmission mechanisms between neurons according to input data and constraint conditions, and perform performance evaluation on the adjusted chip architecture to obtain an AI chip architecture that passes the evaluation.

[0027] Compared with the prior art, the advantages and beneficial effects of the present invention are as follows: By obtaining protein structure data of human brain neuron connections and simulating human brain neuron connections based on it, a protein network model is constructed, so that the chip obtains high-efficient information processing capabilities; Based on the protein network model, connection strengths and signal transmission mechanisms between neurons are obtained, the connection strengths and signal transmission mechanisms are mapped to programmable resources of the FPGA, and dynamic adjustment of the chip architecture is performed through the configuration file update mechanism of the FPGA. The programmable characteristics of the FPGA allow the chip to dynamically adjust its internal structure according to different application scenarios, thereby achieving efficient utilization of resources and flexible expansion of functions; The protein network model is divided into multiple sub-networks, and each sub-network is allocated to different computing units for parallel processing to improve the parallelism of the AI chip; At the same time, an adaptive learning algorithm is adopted to dynamically adjust connection strengths and signal transmission mechanisms between neurons according to input data and constraint conditions, and perform performance evaluation on the adjusted chip architecture to obtain an AI chip architecture that passes the evaluation, optimizing the learning efficiency and adaptability of the chip. By simulating the low-power consumption characteristics of biological neural networks, the obtained AI chip architecture can reduce chip power consumption and improve the energy efficiency ratio, and is applicable to power-sensitive application scenarios such as mobile devices and edge computing. Brief Description of the Drawings

[0028] Figure 1 It is a schematic flow chart of an AI chip architecture design method based on a protein network in an embodiment;

[0029] Figure 2 It is a schematic structural diagram of an AI chip based on a protein network in an embodiment;

[0030] Figure 3 It is a schematic diagram of the architecture of an AI chip in an embodiment. Specific implementation manners

[0031] Before describing the specific implementation manners of the present invention, the overall concept of the present invention will be described as follows:

[0032] The present invention is mainly developed in the process of AI chip architecture design. At present, there are problems such as too high power consumption, insufficient parallelism, poor flexibility and reconfigurability in AI architecture design when dealing with complex artificial intelligence tasks.

[0033] The inventors found through analysis that the protein network is an important part of the biological neural network, and its structural and functional characteristics have the following significant advantages:

[0034] Efficient information processing ability: Neurons in the protein network transmit and process information through a complex connection structure, enabling efficient parallel computing. This structure is similar to the neuron network of the human brain and can process a large amount of information in a short time.

[0035] Adaptive learning ability: The protein network has the ability to dynamically adjust the connection strength and can perform adaptive learning according to the changes in the input signal. This characteristic enables the chip to optimize its performance in a changing environment, improving the learning efficiency and adaptability.

[0036] Low power consumption characteristic: The signal transmission mechanism of the protein network is based on a bioelectrochemical process, and its power consumption is much lower than that of traditional electronic devices. Simulating this mechanism can significantly reduce the power consumption of the AI chip and improve the energy efficiency ratio.

[0037] Reconfigurability: The structure of the protein network can be dynamically adjusted through a biochemical process, and this characteristic provides a theoretical basis for the reconfigurability of the chip. By simulating the reconfigurability of the protein network, the AI chip can dynamically adjust its architecture and function according to different task requirements.

[0038] Therefore, the present invention proposes a method for designing an AI chip architecture based on a protein network. By obtaining the protein structure data of human brain neuron connections and simulating the human brain neuron connections based on it, a protein network model is constructed to enable the chip to obtain efficient information processing capabilities. Based on the protein network model, the connection strength and signal transmission mechanism between neurons are obtained, and the connection strength and signal transmission mechanism are mapped to the programmable resources of the FPGA. Through the configuration file update mechanism of the FPGA, dynamic adjustment of the chip architecture is performed. The programmable characteristics of the FPGA allow the chip to dynamically adjust its internal structure according to different application scenarios, thereby achieving efficient utilization of resources and flexible expansion of functions. The protein network model is divided into multiple sub-networks, and each sub-network is assigned to different computing units for parallel processing to improve the parallelism of the AI chip. At the same time, an adaptive learning algorithm is adopted to dynamically adjust the connection strength and signal transmission mechanism between neurons according to the input data and constraint conditions, and perform performance evaluation on the adjusted chip architecture to obtain an AI chip architecture that passes the evaluation, optimizing the learning efficiency and adaptability of the chip. By simulating the low-power characteristics of the biological neural network, the obtained AI chip architecture can reduce the chip power consumption and improve the energy efficiency ratio, and is suitable for power-sensitive application scenarios such as mobile devices and edge computing.

[0039] After introducing the overall concept of the present invention, in order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the following further elaborates on the present invention in detail through specific embodiments in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0040] In one embodiment, as Figure 1 shown, a method for designing an AI chip architecture based on a protein network is provided, including the following steps:

[0041] Step S110, obtain the protein structure data of human brain neuron connections, simulate the human brain neuron connections based on the protein structure data, and construct a protein network model.

[0042] Specifically, collect and obtain the protein structure data of human brain neuron connections, simulate the human brain neuron connections according to the protein structure data, and construct a protein network model. The model includes multiple neuron nodes and connections. Each node represents a neuron, and each edge represents the connection between neurons.

[0043] The protein network model has high parallelism and dynamic adjustment capabilities, and can significantly improve the performance of the chip when processing complex tasks, such as deep learning, image recognition, natural language processing, etc. By simulating the low-power characteristics of the biological neural network, it can first reduce the chip power consumption and improve the energy efficiency ratio, making it more suitable for power-sensitive application scenarios.

[0044] Among them, step S110 includes: collecting protein structure data of human brain neuron connections; generating a protein network topology structure simulating human brain neuron connections through a computational simulation method; optimizing the protein network topology structure to obtain a protein network model, and the formula is:

[0045]

[0046] In the formula, E represents the energy function, w ij represents the connection strength between neuron i and neuron j, y i and y j respectively represent the outputs of neuron i and neuron j.

[0047] Specifically, collect the protein structure data of human brain neuron connections, perform computational simulation based on the collected protein structure data to generate a protein network topology solution structure similar to human brain neuron connections, and optimize the obtained protein network topology structure to obtain a protein network model, improve its matching degree with human brain neuron connections, ensure that the model can efficiently simulate the behavior of biological neural networks, and through the protein network model simulating human brain neuron connections, efficient information processing can be achieved and it has extremely strong learning ability.

[0048] Step S120, based on the protein network model, obtain the connection strength and signal transmission mechanism between neurons.

[0049] Specifically, according to the constructed protein network model, calculate the connection strength and signal transmission mechanism between neurons. The connection strength and signal transmission mechanism can be calculated respectively using a connection strength model based on weights and a non-linear signal transmission function.

[0050] Among them, step S120 includes: based on the protein network model, obtain the connection strength between neurons, which is:

[0051]

[0052] In the formula, w ij represents the connection strength between neuron i and neuron j, s i and s j respectively represent the activation states of neuron i and neuron j, and k is a regulation parameter; the signal transmission mechanism is:

[0053]

[0054] In the formula, y i represents the output of neuron i, x jDenotes the input of neuron j, b i Denotes the bias of neuron i, and f is the activation function.

[0055] Specifically, according to the obtained protein network model, a suitable mathematical model is selected to describe the connection strength between neurons, such as a connection strength model based on weights; at the same time, a non-linear function or a difference equation is used to describe the signal transmission mechanism to simulate the dynamic signal transmission process between neurons; in addition, the above mathematical formulas can be parameter-adjusted and optimized to ensure that they can accurately reflect the connection and signal transmission characteristics between neurons.

[0056] Step S130: Map the connection strength and signal transmission mechanism of neurons to the programmable resources of the FPGA, and perform dynamic adjustment of the chip architecture through the configuration file update mechanism of the FPGA.

[0057] Specifically, map the obtained connection strength and signal transmission mechanism of neurons to the programmable resources of the FPGA, and use FPGA technology to make the chip reconfigurable and capable of dynamically adjusting its internal structure according to different application scenarios.

[0058] In actual operation, an FPGA architecture applicable to the protein network model can be designed, including programmable logic units, storage units, and interconnection units; at the same time, a reconfigurable mapping algorithm is developed to map the neurons and connections in the protein network model to the programmable resources of the FPGA; thus, dynamic reconfiguration of the chip architecture can be achieved through the configuration file update mechanism of the FPGA to adapt to different computing tasks and learning requirements.

[0059] Step S140: Divide the protein network model into multiple sub-networks and allocate each sub-network to different computing units for parallel processing.

[0060] Specifically, to improve the processing efficiency of the AI chip, the protein network model is divided into multiple sub-networks, and each sub-network is allocated to different computing units for parallel processing, so that the protein network can have high parallelism and can significantly improve the performance of the chip when processing complex tasks.

[0061] Among them, step S140 includes: The formula for parallel processing is:

[0062]

[0063] In the formula, C represents the parallel computing result.

[0064] Specifically, the parallel processing result is calculated through the connection strength between neurons and the input of neurons, improving the parallel processing ability of the AI chip to facilitate the rapid processing of complex tasks.

[0065] Step S150: Using an adaptive learning algorithm, according to the input data and constraint conditions, dynamically adjust the connection strength between neurons and the signal transmission mechanism, and evaluate the performance of the adjusted chip architecture to obtain an AI chip architecture that passes the evaluation.

[0066] Specifically, using an adaptive learning algorithm, according to the characteristics of the input data and the constraint conditions of the learning task, dynamically adjust the connection strength between neurons and the signal transmission mechanism. At the same time, use a feedback mechanism to evaluate the performance of the adjusted chip architecture, and make further adjustments according to the evaluation. Finally, obtain an AI chip architecture that passes the evaluation, improving the learning efficiency and information processing efficiency of the chip.

[0067] Among them, the calculation formula of the adaptive learning algorithm is:

[0068] Δw ij =η·(y i -t i )·x j ;

[0069] In the formula, Δw ij represents the adjustment amount of the connection strength, η represents the learning rate, and t i represents the target output.

[0070] Specifically, in order to improve the learning ability of the AI chip, dynamically adjust the connection strength through the adaptive algorithm, so as to be able to dynamically adjust the connection strength between neurons and the signal transmission mechanism according to the characteristics of the input data and the requirements of the learning task, ensuring the learning ability of the AI chip.

[0071] Among them, the formula for evaluating the performance of the chip architecture is:

[0072]

[0073] In the formula, P represents the performance index, T represents the time step, and C t represents the computational amount at the t-th time step, and E t represents the energy consumption at the t-th time step.

[0074] Specifically, after constructing the AI chip architecture, its performance can also be evaluated. Comprehensively evaluate the performance of the AI chip architecture according to its computational amount and energy consumption, and make corresponding adjustments to the learning results according to the evaluation results, further improving the learning ability and information processing efficiency of the chip.

[0075] In this embodiment, by obtaining the protein structure data of human brain neuron connections and simulating human brain neuron connections based on it, a protein network model is constructed to enable the chip to obtain efficient information processing capabilities; based on the protein network model, the connection strength and signal transmission mechanism between neurons are obtained, and the connection strength and signal transmission mechanism are mapped to the programmable resources of the FPGA. Through the configuration file update mechanism of the FPGA, dynamic adjustment of the chip architecture is performed. The programmable characteristics of the FPGA allow the chip to dynamically adjust its internal structure according to different application scenarios, thereby achieving efficient utilization of resources and flexible expansion of functions; the protein network model is divided into multiple sub-networks, and each sub-network is assigned to different computing units for parallel processing to improve the parallelism of the AI chip; at the same time, an adaptive learning algorithm is adopted to dynamically adjust the connection strength and signal transmission mechanism between neurons according to the input data and constraint conditions, and perform performance evaluation on the adjusted chip architecture to obtain an AI chip architecture that passes the evaluation, optimizing the learning efficiency and adaptability of the chip. By simulating the low-power characteristics of the biological neural network, the obtained AI chip architecture can reduce the chip power consumption and improve the energy efficiency ratio, and is suitable for power-sensitive application scenarios such as mobile devices and edge computing.

[0076] As Figure 2 shown, an AI chip 20 based on a protein network is provided, which is designed by using an AI chip architecture design method based on a protein network as described above, and includes: a protein network model construction module 21, a neuron information acquisition module 22, a chip architecture adjustment module 23, a parallel processing module 24, and an adaptive learning module 25, wherein:

[0077] The protein network model construction module 21 is configured to obtain the protein structure data of human brain neuron connections, simulate human brain neuron connections based on the protein structure data, and construct a protein network model;

[0078] The neuron information acquisition module 22 is configured to obtain the connection strength and signal transmission mechanism between neurons based on the protein network model;

[0079] The chip architecture adjustment module 23 is configured to map the connection strength and signal transmission mechanism of neurons to the programmable resources of the FPGA, and perform dynamic adjustment of the chip architecture through the configuration file update mechanism of the FPGA;

[0080] The parallel processing module 24 is configured to divide the protein network model into multiple sub-networks, and assign each sub-network to different computing units for parallel processing;

[0081] The adaptive learning module 25 is used to adopt an adaptive learning algorithm to dynamically adjust the connection strength and signal transmission mechanism between neurons according to the input data and constraint conditions, and perform performance evaluation on the adjusted chip architecture to obtain an AI chip architecture that passes the evaluation.

[0082] In practical applications, the AI chip architecture of the present invention can monitor the internal environment of the working area, as well as the efficiency and accuracy of the chip in processing data, calculate the environmental interference index and the change value of data processing quality, and then calculate the chip performance index in combination with the environmental interference index and the change value of data processing quality. According to the chip performance index, it is judged whether the current chip needs to be optimized and adjusted. In the case where optimization and adjustment are required, an optimization signal is sent to the system for dynamic reconstruction of the chip structure. Through the changes in environmental factors and data processing quality, the probability of pre-judging the decline of chip performance can be intuitively found, so as to optimize and adjust the chip performance in time, avoiding the cumbersome manual inspection, reducing misjudgment and missed judgment at the same time, increasing the sensitivity of the chip operation, effectively solving the problem of chip performance decline, and improving the working efficiency and data processing quality of the chip. The AI chip architecture of the present invention has high energy efficiency, high parallelism and high reconfigurability, and is suitable for a variety of artificial intelligence application scenarios.

[0083] As Figure 3 shown, it is an AI chip architecture obtained by adopting the above-mentioned AI chip architecture design scheme based on the protein network.

[0084] Among them, PCIE Gen4 (ARM) is the main interface of the chip, which is used for high-speed data transmission with external devices.

[0085] Scheduler is a scheduler responsible for managing the allocation and execution order of computing tasks.

[0086] Compute Unit 0 and Compute Unit 1 are two computing units, which are the core processing parts of the chip. Each unit contains multiple APU-SDNN and APU-cluster modules.

[0087] APU-SDNN is a dedicated neural network processing unit used to execute deep neural network (DNN) calculations.

[0088] APU-cluster is a general computing unit that can execute various computing tasks.

[0089] On-chip Shared Memory is on-chip shared memory, which is used to quickly share data inside the computing unit to reduce data transmission latency.

[0090] NOC0 and NOC1 are network switching units used for data exchange between computing units and between computing units and external storage. The network switching unit can ensure efficient data transmission between different modules.

[0091] HB MIF and HB MO are high-bandwidth storage interfaces used to connect external storage devices and provide high-speed data reading and writing capabilities.

[0092] HB MIF and HB M1 are data interfaces that further enhance the data transmission capacity between the chip and external storage devices.

[0093] After obtaining the AI chip using the above chip architecture, data enters the chip from the outside through the PCIE Gen4 interface and is allocated to different computing units by the scheduler. The computing units exchange data through the NOC, execute computing tasks, and the computing results are output to the external storage device through the HB interface.

[0094] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above methods. Among them, the storage medium can be a magnetic disk, an optical disc, a read-only memory (ROM), or a random access memory (RAM), etc.

[0095] Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general-purpose computing device. They can be concentrated on a single computing device or distributed on a network composed of multiple computing devices. Optionally, they can be implemented by program codes executable by the computing device. Thus, they can be stored in a computer storage medium (ROM / RAM, magnetic disk, optical disc) and executed by the computing device. And in some cases, the steps shown or described can be executed in a different order from here, or they can be made into individual integrated circuit modules respectively, or multiple modules or steps among them can be made into a single integrated circuit module to implement. Therefore, the present invention is not limited to any specific combination of hardware and software.

[0096] The above content is a further detailed description of the present invention in combination with specific implementation manners. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, without departing from the concept of the present invention, several simple deductions or substitutions can be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A protein network-based AI chip architecture design method, characterized in that: The following steps are involved: Acquiring protein structure data of human brain neuron connections, simulating human brain neuron connections based on the protein structure data, and constructing a protein network model; Based on the protein network model, the connection strength and signal transmission mechanism between neurons are obtained; Mapping the connection strength and signal transmission mechanism of neurons to the programmable resources of the FPGA, and dynamically adjusting the chip architecture through the configuration file update mechanism of the FPGA; The protein network model is divided into multiple sub-networks, and each sub-network is assigned to a different computing unit for parallel processing; An adaptive learning algorithm is used to dynamically adjust the connection strength and signal transmission mechanism between neurons according to input data and constraints, and a performance evaluation is performed on the adjusted chip architecture to obtain an AI chip architecture that passes the evaluation.

2. The protein network-based AI chip architecture design method according to claim 1, characterized in that: The step of obtaining protein structure data of human brain neuron connections, simulating human brain neuron connections based on the protein structure data, and constructing a protein network model comprises: Collect protein structure data on the connections between neurons in the human brain; Based on the protein structure data, a protein network topology simulating the connection of neurons in the human brain is generated by computational simulation methods; The protein network topology is optimized to obtain a protein network model, the formula is: Where E represents the energy function, w ij represents the connection strength between neuron i and neuron j, y i and j Represent the outputs of neuron i and neuron j respectively.

3. The protein network-based AI chip architecture design method according to claim 2, characterized in that: The method of obtaining the connection strength and signal transmission mechanism between neurons based on the protein network model includes: Based on the protein network model, the connection strength between neurons is obtained as: In the formula, w ij represents the connection strength between neuron i and neuron j, s i and j They represent the activation states of neuron i and neuron j respectively, and k is the adjustment parameter; The signal transmission mechanism is: In the formula, y i represents the output of neuron i, x j represents the input of neuron j, b i represents the bias of neuron i, and f is the activation function.

4. The protein network-based AI chip architecture design method according to claim 3, characterized in that: The protein network model is divided into multiple sub-networks, and each sub-network is assigned to a different computing unit for parallel processing. The formula for parallel processing is: Where C represents the parallel computing result.

5. The protein network-based AI chip architecture design method according to claim 4, characterized in that: The calculation formula of the adaptive learning algorithm is: Δw ij =η·(y i -t i )x j ; In the formula, Δw ij represents the adjustment amount of the connection strength, η represents the learning rate, and t i Indicates the target output.

6. The protein network-based AI chip architecture design method according to claim 5, characterized in that: The performance evaluation of the adjusted chip architecture is performed using the formula: In the formula, P represents the performance index, T represents the time step, and C t represents the amount of computation at the t-th time step, E t represents the energy consumption at the tth time step.

7. An AI chip based on protein network, characterized in that: The method for designing an AI chip architecture based on a protein network as claimed in any one of claims 1 to 6 is adopted, comprising: A protein network model building module is used to obtain protein structure data of human brain neuron connections, simulate human brain neuron connections based on the protein structure data, and build a protein network model; A neuron information acquisition module, used to obtain the connection strength and signal transmission mechanism between neurons based on the protein network model; A chip architecture adjustment module, used to map the connection strength and signal transmission mechanism of neurons to the programmable resources of the FPGA, and dynamically adjust the chip architecture through the configuration file update mechanism of the FPGA; A parallel processing module, used to divide the protein network model into multiple sub-networks, and assign each sub-network to a different computing unit for parallel processing; The adaptive learning module is used to adopt an adaptive learning algorithm to dynamically adjust the connection strength and signal transmission mechanism between neurons according to input data and constraints, and to perform performance evaluation on the adjusted chip architecture to obtain an AI chip architecture that passes the evaluation.

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