Chip parameter optimization method and device, medium and product

Abstract

The invention discloses a chip parameter optimization method and device, a medium and a product, and relates to the technical field of logic circuit design verification, and the method comprises the steps: inputting register parameters into a prototype verification environment of a target chip module, and executing a preset verification task; calculating parameter fitness values according to the task execution time, and taking a chip parameter group corresponding to a target parameter fitness value meeting a preset fitness threshold condition as a target chip parameter group; adjusting a parameter crossover probability and a parameter mutation probability based on the parameter fitness value of the target chip parameter group; and performing register parameter crossover and register parameter variation on the register parameters in the target chip parameter group according to the adjusted parameter crossover probability and parameter variation probability, outputting new register parameters, and skipping to execute the step of inputting the register parameters into the prototype verification environment of the target chip module. And outputting a target chip parameter group formed by the current register parameters until the register parameters meet the parameter adjustment conditions. And chip parameter optimization is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of logic circuit design verification, and particularly relates to a method, device, medium and product for optimizing chip parameters. Background Art

[0002] In recent years, with the rapid development of large-scale integrated circuit development and manufacturing technologies, various indicators of chip simulation modules have increasingly become key factors in measuring the performance of certain specific chips. High integration and complex functions are also the design characteristics of such chips, which are used to meet the needs of different industries. Therefore, while confirming the logic function of the functional module, the performance screening and verification of the chip module is a key link after the chip is taped out. Processing, packaging and other factors will cause individual deviations. Configuration parameters need to be reserved for the chip, and through adjustment, the optimal performance can be ensured in different environments. Time is cost. How to effectively find appropriate parameters and the stable working environment of the chip in a short time poses high requirements for the design of test vectors.

[0003] Currently, in the verification process of existing chip simulation modules, conventional test vectors use design standard values for testing, and it is difficult to achieve good coverage and accurate diagnosis ability in the full threshold range for high-precision and complex circuits. For the relevant tests using non-self-learning algorithm libraries, the debugging takes a long time, and there are misjudgments of error symptoms and confusion of symptoms in most test items. At the same time, the test script and instrument program control excitation are generally not integrated for the entire verification system. Most verification work needs to be manually configured, wasting a large amount of human costs and debugging time, increasing the risk of errors in manual debugging operations, and thus affecting the test quality and results. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a method, device, medium and product for optimizing chip parameters, which can automatically accelerate the optimization process of chip parameters. The specific solutions are as follows: In the first aspect, the present application discloses a method for optimizing chip parameters, including: Inputting register parameters into the prototype verification environment of the target chip module, executing a preset verification task, and recording the task execution time; wherein, the register parameters are register values corresponding to several chip parameter groups; Calculating the corresponding parameter fitness value according to the task execution time, and screening the target parameter fitness value that meets the preset fitness threshold condition, so as to use the chip parameter group corresponding to the target parameter fitness value as the target chip parameter group; Adjusting the parameter crossover probability and parameter mutation probability based on the fitness distribution of the parameter fitness values of each target chip parameter group; Perform register parameter crossover and register parameter mutation on the register parameters in the target chip parameter group respectively according to the adjusted parameter crossover probability and the adjusted parameter mutation probability to output new register parameters, and jump to execute the step of inputting the register parameters into the prototype verification environment of the target chip module until the new register parameters meet the parameter adjustment conditions, and output the target chip parameter group composed of the current register parameters to the chip configuration interface.

[0005] Optionally, the chip parameter optimization method further includes: Randomly generate several groups of register parameter combinations within the feasible domain of register values based on the physical configuration constraints of the target chip module; Respectively form several chip parameter groups based on the register parameters in each register parameter combination.

[0006] Optionally, before randomly generating several groups of register parameter combinations within the feasible domain of register values based on the physical configuration constraints of the target chip module, it further includes: Obtain the physical configuration constraints of each register in the target chip module; Among them, the physical configuration constraints include the value range constraints of each register and the value association constraints between registers.

[0007] Optionally, randomly generating several groups of register parameter combinations within the feasible domain of register values based on the physical configuration constraints of the target chip module includes: Generate several groups of initial register parameter combinations within the feasible domain of register values based on the Monte Carlo random sampling method; Perform physical configuration constraint verification on each initial register parameter combination respectively to obtain several groups of register parameter combinations that meet the physical configuration constraint verification.

[0008] Optionally, performing register parameter mutation on the register parameters in the target chip parameter group according to the adjusted parameter mutation probability to output new register parameters includes: Determine the register parameters to be mutated in the register parameters of the target chip parameter group according to the adjusted parameter mutation probability; Perform parameter mutation on the register parameters to be mutated to obtain new register parameters that meet the physical configuration constraints and are within the feasible domain.

[0009] Optionally, adjusting the parameter crossover probability and the parameter mutation probability based on the fitness distribution of the parameter fitness values of each target chip parameter group includes: If the parameter fitness value of the current target chip parameter group is greater than or equal to the average parameter fitness value, the parameter crossover probability of the current target chip parameter group is dynamically reduced according to the crossover probability calculation equation to obtain the adjusted parameter crossover probability; the parameter mutation probability of the current target chip parameter group is dynamically reduced according to the mutation probability calculation equation to obtain the adjusted parameter mutation probability; If the parameter fitness value of the current target chip parameter group is less than the average parameter fitness value, the parameter crossover probability of the current target chip parameter group is adjusted to the preset maximum parameter crossover probability, and the parameter mutation probability of the current target chip parameter group is adjusted to the preset maximum parameter mutation probability; Among them, the average parameter fitness value is the average of the parameter fitness values of all target chip parameter groups.

[0010] Optionally, the crossover probability calculation equation is: ; Among them, represents the preset maximum parameter crossover probability, represents the maximum parameter fitness value among all target chip parameter groups, represents the average parameter fitness value, represents the fitness value of the larger party of the target chip parameter group participating in parameter crossover, and the value range is , represents the preset minimum parameter crossover probability.

[0011] Optionally, the mutation probability calculation equation is: ; Among them, represents the preset maximum parameter mutation probability, represents the maximum parameter fitness value among all target chip parameter groups, represents the average parameter fitness value, represents the fitness value of the target chip parameter group participating in parameter mutation.

[0012] Optionally, according to the adjusted parameter crossover probability, register parameter crossover is performed on the register parameters in the target chip parameter group to output new register parameters, including: The target chip parameter groups are grouped according to the parameter fitness value to obtain the first target chip parameter group and the second target chip parameter group; among them, the first target chip parameter group is the target chip parameter group whose fitness value ranking meets the preset fitness ranking condition, and the second target chip parameter group is the other target chip parameter groups except the first target chip parameter group; Use the multi-point crossover method and based on the adjusted parameter crossover probability, exchange some of the register parameters in the first target chip parameter group to output new register parameters; Based on the adjusted parameter crossover probability, determine the target register parameter sites in the register parameters of the second target chip parameter group, and use the single-point crossover method to exchange all the register parameters after the target register parameter sites to output new register parameters.

[0013] Optionally, after outputting the new register parameters, it further includes: Perform constraint verification on the physical configuration constraints of the new register parameters after the exchange process; If the constraint verification is passed, jump to execute the step of inputting the register parameters into the prototype verification environment of the target chip module; If the constraint verification fails, jump to execute the step of performing register parameter crossover on the register parameters in the target chip parameter group according to the adjusted parameter crossover probability.

[0014] Optionally, outputting the target chip parameter group composed of the current register parameters to the chip configuration interface includes: Convert the target chip parameter group composed of the current register parameters into a binary configuration code stream; Write the configuration code stream into the physical register of the target chip through a preset communication interface; Verify whether the actual performance indicators of the target chip are consistent with the simulation results; If they are inconsistent, re-trigger the chip parameter optimization process.

[0015] Optionally, the prototype verification environment is an FPGA-based hardware simulation platform; wherein, the hardware simulation platform includes a parameter loading unit for configuring the register parameters to the FPGA logic unit through a hardware description language to simulate the physical behavior of the target chip module, a real-time monitoring unit for collecting the signal indicators of the target chip module executing a preset verification task, and a dynamic feedback module for adjusting the voltage and temperature conditions of the preset verification task according to the real-time monitoring data during the execution of the preset verification task to approach the actual prototype verification environment; Among them, the signal indicators include clock jitter indicators, signal delay indicators, and dynamic power consumption indicators.

[0016] In a second aspect, the present application discloses an electronic device, including: A memory for storing a computer program; A processor for executing the computer program to implement the steps of the chip parameter optimization method disclosed above.

[0017] In a third aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the steps of the chip parameter optimization method disclosed above are implemented.

[0018] In a fourth aspect, the present application discloses a computer program product, including a computer program / instructions, which implement the steps of the chip parameter optimization method disclosed above when executed by a processor.

[0019] It can be seen that the present application discloses a chip parameter optimization method, including: inputting register parameters into the prototype verification environment of a target chip module, executing a preset verification task, and recording the task execution time; wherein, the register parameters are register values corresponding to several chip parameter groups; calculating corresponding parameter fitness values according to the task execution time, and screening target parameter fitness values that meet the preset fitness threshold condition, so as to use the chip parameter group corresponding to the target parameter fitness value as the target chip parameter group; adjusting the parameter crossover probability and parameter mutation probability based on the fitness distribution of the parameter fitness values of each target chip parameter group; performing register parameter crossover and register parameter mutation on the register parameters in the target chip parameter group respectively according to the adjusted parameter crossover probability and the adjusted parameter mutation probability, so as to output new register parameters, and jumping to execute the step of inputting the register parameters into the prototype verification environment of the target chip module until the new register parameters meet the parameter adjustment condition, and outputting the target chip parameter group composed of the current register parameters to the chip configuration interface.

[0020] Thus, by dynamically adjusting the crossover and mutation probabilities based on the fitness distribution, it can quickly jump out of the local optimum in the initial stage and converge precisely in the later stage. Compared with the traditional genetic algorithm, the convergence speed is improved. By automatically executing the closed-loop process of parameter generation, verification test, fitness evaluation, crossover and mutation, it replaces the traditional manual debugging and avoids repeated testing and parameter omission caused by insufficient human experience. Through the above overall process, the manual debugging operation in the chip parameter configuration process is reduced, the labor cost and debugging time are reduced, and the parameter optimization efficiency of the chip module is increased. Description of the Drawings

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0022] Figure 1 It is a flowchart of a chip parameter optimization method disclosed in the present application; Figure 2Schematic diagram of constraint conditions for physical configuration constraints disclosed in this application; Figure 3 Schematic diagram of parameter crossover disclosed in this application; Figure 4 Flowchart of a specific chip parameter optimization method disclosed in this application; Figure 5 Structural diagram of an electronic device disclosed in this application. Detailed implementation manners

[0023] Next, the technical solutions in the embodiments of this application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0024] In recent years, with the rapid development of large-scale integrated circuit development and manufacturing technologies, various indicators of chip simulation modules have increasingly become key factors in measuring the performance of certain specific chips. High integration and complex functions are also the design characteristics of such chips to meet the needs of different industries. Therefore, while confirming the logical functions of functional modules, the performance screening and verification of chip modules are a crucial step after chip tape-out. Factors such as processing and packaging will cause individual deviations, and it is necessary to reserve configuration parameters for the chip, which can be adjusted to ensure optimal performance in different environments. Time is cost. How to effectively find suitable parameters and a stable working environment for the chip in a short time poses high requirements for the design of test vectors.

[0025] Currently, in the verification process of existing chip simulation modules, conventional test vectors use design standard values for testing, and it is difficult to achieve good coverage and accurate diagnostic capabilities within the full threshold range for high-precision and complex circuits. The relevant tests using non-self-learning algorithm libraries are time-consuming for debugging, and most test items have misjudgments of error symptoms and confusion of symptoms. At the same time, test scripts and instrument program control incentives are generally not integrated for the entire verification system, and most verification work requires manual configuration, wasting a large amount of human costs and debugging time, increasing the risk of errors in manual debugging operations, and thus affecting test quality and results.

[0026] For this reason, the present invention provides a chip parameter optimization scheme that can automatically accelerate the optimization process of chip parameters.

[0027] Referring to Figure 1 As shown, the embodiments of the present invention disclose a chip parameter optimization method, including: Step S11: Input the register parameters into the prototype verification environment of the target chip module, execute the preset verification tasks, and record the task execution time; wherein, the register parameters are the register values corresponding to several chip parameter groups.

[0028] In this embodiment, obtain the physical configuration constraints of each register in the target chip module; wherein, the physical configuration constraints include the value range constraints of each register and the value association constraints between registers. It can be understood that since the valid values of registers are within a certain range, there is no verification significance if it exceeds this range. Therefore, the value range of each register needs to be used as one of the constraint conditions. For example, Figure 2 as shown: the value range of register A is from 2 to 6, then in the algorithm, the value of register A cannot be less than 2 or greater than 6, and there are also certain constraint conditions between registers. For example: the value of register A must be less than the value of register B. Based on the above physical configuration constraints, several chip parameter groups are further generated within the feasible domain of register values, specifically as follows: Randomly generate several groups of register parameter combinations within the feasible domain of register values based on the physical configuration constraints of the target chip module; form several chip parameter groups respectively based on the register parameters in each register parameter combination. Specifically, generate several groups of initial register parameter combinations within the feasible domain of register values based on the Monte Carlo random sampling method; verify the physical configuration constraints for each group of initial register parameter combinations respectively to obtain several groups of register parameter combinations that meet the physical configuration constraint verification.

[0029] It can be understood that several solutions are randomly generated within the feasible domain based on the physical configuration constraints, which are called the initial population. In the initial population, several groups of initial register parameter combinations are generated based on the Monte Carlo random sampling method, and then the physical configuration constraints are verified for each group of initial register parameter combinations respectively to obtain several groups of register parameter combinations that all meet the physical configuration constraints in the initial register parameter combinations.

[0030] Taking the example that a certain function of an IP module needs to configure 3 registers, namely register A, register B, and register C, with value ranges of A1 to A5, B1 to B4, and C1 to C7 respectively. Then, randomly select A1 to A5 as the value of register A2, B1 to B4 as the value of register B3, and C1 to C7 as the value of register C4 based on the Monte Carlo random sampling, and satisfy the constraint condition that the value of register A is less than the value of register B. Call one of the registers a gene, and call the combination of registers (chip parameter group) a chromosome. The chromosome is one of the solutions. In this embodiment, a chromosome is also an individual. For example, [A2, B3, C4] is one of the solutions. The number of chromosomes for population initialization is selected according to the actual situation. The population size should not be too large or too small. When it is too small, the genetic optimization performance is generally not very good. When it is too large, it is easy to fall into the local optimal solution.

[0031] In this embodiment, the intra-group register parameters in the above-mentioned several chip parameter groups are input into the prototype verification environment of the target chip module, a preset verification task is executed, and the task execution time is recorded. That is, the fitness of the performance output parameters obtained after each solution in the population is run as the chip input parameters in the prototype verification environment is evaluated to evaluate the adaptability of each individual to the environment. Taking the example that a certain function of the IP module requires 3 registers, namely register A, register B, and register C, randomly select individual 1 [A2, B3, C4], individual 2 [A3, B4, C5], and individual 3 [A3, B3, C4]. The time required to run the same task with individual 1, individual 2, and individual 3 as the chip input in the prototype verification environment is t1, t2, and t3 respectively. That is, the task execution time.

[0032] In addition, the prototype verification environment is an FPGA-based hardware simulation platform; among them, the hardware simulation platform includes a parameter loading unit for configuring register parameters to the FPGA logic unit through a hardware description language to simulate the physical behavior of the target chip module, a real-time monitoring unit for collecting signal indicators of the target chip module executing the preset verification task, and a dynamic feedback module for adjusting the voltage and temperature conditions of the preset verification task according to the real-time monitoring data during the execution of the preset verification task to approach the actual prototype verification environment; among them, the signal indicators include clock jitter indicators, signal delay indicators, and dynamic power consumption indicators. It can be understood that the prototype verification environment is an FPGA (Field-Programmable Gate Array)-based hardware simulation platform, and the preset verification tasks include workload tests, maximum frequency tests, and power consumption tests. Among them, the workload test is to run the daily business scenarios of the chip module (such as video encoding, AI (Artificial Intelligence) inference); the maximum frequency test is to execute stress tasks at the highest operating frequency of the chip; the power consumption test is to record the average power consumption during the task execution process; the task execution time is the weighted average of the three test times (weights are 0.5, 0.3, and 0.2) to comprehensively evaluate the performance, robustness, and energy efficiency ratio of the parameter group.

[0033] Step S12: Calculate the corresponding parameter fitness value according to the task execution time, and screen the target parameter fitness value that meets the preset fitness threshold condition, so as to use the chip parameter group corresponding to the target parameter fitness value as the target chip parameter group.

[0034] In this embodiment, the fitness function is f(t) = 1 / t, where t is the time taken for an individual to perform the same task on the prototype verification environment with the chip input parameters, that is, the task execution time. The better the individual fitness, the larger the parameter fitness value f(t); the worse the individual fitness, the smaller the parameter fitness value f(t). Sort according to the parameter fitness value, eliminate the unfit individuals, and retain the fit ones. The selection operation selects a part of the excellent individuals through the evaluation and sorting of individual fitness, so that they have a greater chance to participate in the reproduction process. In this way, the genetic information of excellent individuals can be inherited and developed in the offspring, thereby improving the fitness of the entire population. However, too large a selection probability may lead to premature convergence. The preset fitness threshold condition is that the selection probability range is 0.2 < p s < 0.5. In this embodiment, the selected selection probability p s is 0.4. The number of retained individuals Res = selection probability p s × Initialize the chromosome, that is, the target chip parameter group. Further, calculate the fitness of the individual, that is, the chromosome, sort the individuals, that is, the chromosomes, according to the size of the fitness value, and retain several chromosomes with smaller individual, that is, chromosome fitness, that is, obtain the supplement of the target chip parameter group, and eliminate other individuals, that is, chromosomes.

[0035] Step S13: Adjust the parameter crossover probability and the parameter mutation probability based on the fitness distribution of the parameter fitness values of each target chip parameter group.

[0036] In this embodiment, adjusting the parameter crossover probability and the parameter mutation probability based on the fitness distribution of the parameter fitness values of each target chip parameter group includes: if the parameter fitness value of the current target chip parameter group is greater than or equal to the average parameter fitness value, dynamically reducing the parameter crossover probability of the current target chip parameter group according to the crossover probability calculation equation to obtain the adjusted parameter crossover probability; dynamically reducing the parameter mutation probability of the current target chip parameter group according to the mutation probability calculation equation to obtain the adjusted parameter mutation probability; if the parameter fitness value of the current target chip parameter group is less than the average parameter fitness value, adjusting the parameter crossover probability of the current target chip parameter group to the preset maximum parameter crossover probability and adjusting the parameter mutation probability of the current target chip parameter group to the preset maximum parameter mutation probability; wherein, the average parameter fitness value is the average of the parameter fitness values of all target chip parameter groups. It can be understood that in the prior art, in the adaptive crossover and mutation operators, when the fitness is close to the maximum fitness, the crossover and mutation probabilities become very small, and when the fitness is equal to the maximum fitness, the crossover and mutation probabilities become zero. When using the existing adaptive genetic algorithm for chip module parameters, it is not ideal in the initial stage. In the initial stage of the algorithm, the better individuals hardly change, and at this time, the excellent individuals are not necessarily the global optimal solution, which increases the possibility of the algorithm obtaining the local optimal solution. Therefore, in the present invention, an improved adaptive genetic operator is used, where, when is greater than or equal to the average parameter fitness value, the crossover probability calculation equation is: ; When is less than the average parameter fitness value, the adjusted parameter crossover probability is: ; Wherein, represents the adjusted parameter crossover probability, , respectively represent the preset maximum parameter crossover probability and the preset minimum parameter crossover probability, represents the maximum parameter fitness value in the target chip parameter group, represents the average parameter fitness value, represents the fitness value of the larger one of the target chip parameter group fitness values participating in the parameter crossover, and the value range is . The parameter crossover probability generally takes values from 0.4 to 0.99. In the present invention, the selected crossover probability is 0.7, is 0.4. That is, in two individuals, each gene has a crossover probability Perform crossover, and randomly select all gene sequences after the gene for exchange. By improving the adaptive genetic operator, increase the crossover and mutation probabilities in the initial stage of the algorithm to accelerate the convergence speed of the algorithm. In the later stage, as the algorithm gradually approaches the optimal solution, reduce the crossover and mutation probabilities to protect the obtained excellent genotypes from being destroyed, and obtain the optimal solution through a small-range search. The improved adaptive genetic operator can control the crossover probability and mutation probability more precisely than the adaptive genetic operator during the crossover and mutation processes, thus achieving a faster convergence speed.

[0037] As Figure 3 shown, through the adjusted parameter crossover algorithm scheme of the present invention, gene 3, gene 4, and gene 5 can be respectively crossed with gene 3', gene 4', and gene 5', rather than only crossing gene 3 with gene 3'.

[0038] In this embodiment, during the evolution process, randomly change the genes in the chromosome to generate new individuals. The mutation process plays an important role in the evolutionary algorithm, which can increase the search space and avoid falling into local optimal solutions. Generally speaking, a lower mutation probability can maintain the stability of the population, and a higher mutation probability can increase the exploration space. The present invention adopts an improved adaptive genetic operator. When is greater than or equal to the average parameter fitness value, the mutation probability calculation equation is: ; When is less than the average parameter fitness value, the adjusted parameter mutation probability is: ; Among them, represents the adjusted parameter mutation probability, , respectively represent the preset maximum parameter mutation probability and the preset minimum parameter mutation probability, represents the maximum parameter fitness value in all target chip parameter groups, represents the average parameter fitness value, represents the fitness value of the target chip parameter group participating in parameter mutation. Among them, in the present invention, is the same as , and different symbols are used to distinguish parameter crossover and parameter mutation.

[0039] When , the function is a monotonically decreasing function, and the value range is . The original mutation probability should not be too large or too small either. Generally, the value is from 0.0001 to 0.2. The present invention selects the original mutation probability to be 0.1, is 0.0001, that is, a certain value of a certain gene in an individual mutates with a mutation probability to mutate. The range of gene mutation must also be within the register value range and must satisfy the constraint that the value of register A is less than the value of register B.

[0040] Step S14: Perform register parameter crossover and register parameter mutation on the register parameters in the target chip parameter group according to the adjusted parameter crossover probability and the adjusted parameter mutation probability, so as to output new register parameters, and jump to execute the step of inputting the register parameters into the prototype verification environment of the target chip module until the new register parameters meet the parameter adjustment conditions, and output the target chip parameter group composed of the current register parameters to the chip configuration interface.

[0041] In this embodiment, the register parameter to be mutated of the register parameters in the target chip parameter group is determined according to the adjusted parameter mutation probability; parameter mutation is performed on the register parameter to be mutated to obtain new register parameters that meet the physical configuration constraints and are within the feasible region. It can be understood that the register parameter to be mutated of the register parameters in the target chip parameter group is determined according to the adjusted parameter mutation probability as follows Figure 4 shown. Taking the example that the IP module has 3 registers, namely register D, register E, and register F, with value ranges of 2 to 6, 5 to 8, and 11 to 17 respectively, the specific steps of the improved genetic algorithm for coverage prototype verification are as follows. First, initialize the population. The number of individuals m is 3, the number of genes G in each chromosome is 3, the selection probability p s is 0.4, the crossover probability is 0.7, is 0.4, the mutation probability is 0.1, is 0.0001, the maximum value of the fitness value is 1, the maximum number of iterations is 1000, and the fitness value is 0.1 second. Initialize 3 chromosomes as x1 = [2, 5, 11], x2 = [6, 8, 17], and x3 = [4, 6, 14]. Calculate the fitness value according to the fitness function, sort according to the fitness value, and select with the selection probability p s to retain the excellent individuals (i.e., chromosomes). According to chromosomes x1, x2, and x3 as input parameters respectively, the time required to execute the same task in the prototype verification environment is t1, t2, and t3, and the fitness sorting is performed according to the time used . Each gene in an individual, that is, a chromosome, mutates with Since the fitness in the population is relatively large Since Less than 1, but the mutated gene must be an integer. Therefore, a gene in an individual, i.e., a chromosome, is randomly selected for mutation. After mutation, the value of register D must satisfy 2 to 6, the value of register E must satisfy 5 to 8, and the value of register F must satisfy 11 to 17.

[0042] In this embodiment, according to the adjusted parameter crossover probability, register parameter crossover is performed on the register parameters in the target chip parameter group to output new register parameters, including: dividing the target chip parameter group according to the parameter fitness value to obtain a first target chip parameter group and a second target chip parameter group; wherein, the first target chip parameter group is the target chip parameter group whose fitness value ranking meets the preset fitness ranking condition, and the second target chip parameter group is the other target chip parameter groups except the first target chip parameter group; using the multi-point crossover method and based on the adjusted parameter crossover probability, exchange processing is performed on some of the register parameters in the register parameters of the first target chip parameter group to output new register parameters; based on the adjusted parameter crossover probability, determine the target register parameter sites in the register parameters of the second target chip parameter group, and use the single-point crossover method to perform exchange processing on all the register parameters after the target register parameter sites to output new register parameters. It can be understood that for the individuals with the top 20% fitness value ranking, the multi-point crossover method is adopted, and only some gene sites in the chromosome (such as the values of register D and register E) are exchanged to retain the high-performance parameter combination; for the individuals with the bottom 80% fitness value ranking, the single-point crossover method is adopted, and all the gene sequences after a certain gene site in the chromosome (such as register F and subsequent registers) are exchanged to introduce diversity; for example: for the individuals with the bottom 80% fitness value ranking, two chromosomes are randomly selected for crossover, and each gene in the individual, i.e., the chromosome, is crossed with a probability to perform crossover. Since the with a larger fitness value in the population is greater than 2, but the crossover must be an integer. Therefore, 2 genes are selected for crossover, and all the genes after one gene in two randomly selected chromosomes are exchanged. In this way, the individuals with the top 20% fitness value ranking already have a relatively good parameter combination. Through multi-point crossover (exchanging multiple gene sites), while retaining the core high-quality genes, the secondary parameters are finely tuned to accelerate the refined search for the local optimal solution. Avoiding the destruction of excellent genes ensures that the algorithm quickly converges to the high-performance parameter combination in the later stage. For the individuals with the bottom 80% low fitness value, single-point crossover is adopted. The individuals with lower fitness values introduce a larger range of parameter changes through single-point crossover (only exchanging all the sequences after a certain gene site), expanding the search space and exploring potential new solutions. Preventing the premature loss of population diversity and avoiding the algorithm falling into local optimality.

[0043] In this embodiment, after outputting the new register parameters, the following steps are further included: performing constraint verification on the physical configuration constraints of the new register parameters after the exchange process; if the constraint verification is passed, jumping to execute the step of inputting the register parameters into the prototype verification environment of the target chip module; if the constraint verification is not passed, jumping to execute the step of performing register parameter crossover on the register parameters in the target chip parameter group according to the adjusted parameter crossover probability. It can be understood that the generated offspring parameters after crossover need to pass the constraint verification of the physical configuration constraints, and if the constraints are violated, the crossover operation is performed again.

[0044] After obtaining the new register parameters, it is determined whether the new register parameters reach the ideal performance output parameters, that is, reach the maximum number of iterations or the fitness value reaches 10 seconds, then stop the iteration and output the actually completed coverage rate, otherwise jump to the step of calculating the fitness value according to the fitness function and sorting according to the fitness value.

[0045] In this embodiment, outputting the target chip parameter group composed of the current register parameters to the chip configuration interface includes: converting the target chip parameter group composed of the current register parameters into a binary configuration code stream; writing the configuration code stream into the physical register of the target chip through a preset communication interface; verifying whether the actual performance index of the target chip is consistent with the simulation result; if not, triggering the chip parameter optimization process again. It can be understood that since the purpose of the parameter optimization process of the present invention is completed before the target chip parameter group is input into the physical register of the target chip for multiple actual optimization tests, therefore, the current target chip parameter group is obtained from the performance screening and verification process of the chip module. Therefore, before complete encapsulation, the optimal register parameter combination can be converted into a binary configuration code stream; the configuration code stream is written into the physical register of the target chip through a JTAG (Joint Test Action Group, an international standard test protocol) or I2C (Inter-Integrated Circuit) interface; verifying whether the actual performance index of the chip after writing is consistent with the simulation result, and if not, triggering the optimization process again.

[0046] It can be seen that the present application discloses a method for optimizing chip parameters, including: inputting register parameters into the prototype verification environment of a target chip module, executing a preset verification task, and recording the task execution time; wherein, the register parameters are register values corresponding to several chip parameter groups; calculating corresponding parameter fitness values according to the task execution time, and screening target parameter fitness values that meet the preset fitness threshold condition, so as to use the chip parameter group corresponding to the target parameter fitness value as the target chip parameter group; adjusting the parameter crossover probability and the parameter mutation probability based on the fitness distribution of the parameter fitness values of each target chip parameter group; respectively performing register parameter crossover and register parameter mutation on the register parameters in the target chip parameter group according to the adjusted parameter crossover probability and the adjusted parameter mutation probability, so as to output new register parameters, and jumping to execute the step of inputting the register parameters into the prototype verification environment of the target chip module until the new register parameters meet the parameter adjustment condition, and outputting the target chip parameter group composed of the current register parameters to the chip configuration interface.

[0047] It can be seen that by dynamically adjusting the crossover and mutation probabilities based on the fitness distribution, it can quickly jump out of the local optimum in the initial stage and converge precisely in the later stage, with the convergence speed improved compared to the traditional genetic algorithm. By automatically executing the closed-loop process of parameter generation, verification testing, fitness evaluation, crossover and mutation, it replaces the traditional manual debugging and avoids repeated testing and parameter omission caused by insufficient human experience. Through the above overall process, the manual debugging operation in the chip parameter configuration process is reduced, the labor cost and debugging time are reduced, and the optimization efficiency of the chip module parameters is increased.

[0048] Figure 5 It is a schematic structural diagram of an electronic device provided by an embodiment of the present application. Specifically, it may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the chip parameter optimization method executed by the electronic device disclosed in any of the foregoing embodiments.

[0049] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows is any communication protocol applicable to the technical solution of the present application, and no specific limitation is made here; the input / output interface 25 is used to obtain external input data or output data to the outside, and its specific interface type can be selected according to specific application needs, and no specific limitation is made here.

[0050] Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), or PLA (Programmable Logic Array). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor used to process data in the wake state, also known as the CPU (Central Processing Unit); the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may be integrated with a GPU (Graphics Processing Unit), and the GPU is responsible for the rendering and drawing of the content to be displayed on the display screen. In some embodiments, the processor 21 may further include an AI (Artificial Intelligence) processor, and the AI processor is used to process computational operations related to machine learning.

[0051] In addition, as a carrier for resource storage, the memory 22 may be a read-only memory, a random access memory, a magnetic disk, or an optical disc, etc. The resources stored thereon include an operating system 221, a computer program 222, data 223, etc., and the storage method may be temporary storage or permanent storage.

[0052] Among them, the operating system 221 is used to manage and control each hardware device and the computer program 222 on the electronic device 20 to enable the processor 21 to perform operations and processing on the massive data 223 in the memory 22. It may be Windows, Unix, Linux, etc. In addition to the computer program that can be used to complete the chip parameter optimization method executed by the electronic device 20 disclosed in any of the foregoing embodiments, the computer program 222 may further include a computer program that can be used to complete other specific tasks. The data 223 may include not only the data transmitted by external devices received by the electronic device, but also the data collected by its own input / output interface 25, etc.

[0053] Furthermore, the embodiments of the present application also disclose a computer-readable storage medium. When the computer program stored in the storage medium is loaded and executed by a processor, the steps of the chip parameter optimization method disclosed in any of the foregoing embodiments are implemented.

[0054] An embodiment of the present invention also discloses a computer program product, including a computer program / instructions, which when executed by a processor, implement the steps of the chip parameter optimization method disclosed in any of the foregoing embodiments.

[0055] In this specification, the various embodiments are described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and reference can be made to the description of the method part for related parts.

[0056] Those skilled in the art can further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0057] The steps of the method or algorithm described in combination with the embodiments disclosed in this article can be directly implemented by hardware, a software module executed by a processor, or a combination of the two. The software module can be placed in a random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, register, hard disk, removable disk, compact disc read-only memory (CD-ROM), or any other form of storage medium well-known in the technical field.

[0058] Finally, it should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, the element defined by the statement "including an..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0059] The above has introduced the solution provided by the present invention in detail. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A method for optimizing chip parameters, characterized in that, Including: Input the register parameters into the prototype verification environment of the target chip module, execute the preset verification tasks, and record the task execution time; wherein, the register parameters are the register values corresponding to several chip parameter groups; Calculate the corresponding parameter fitness values according to the task execution time, and screen the target parameter fitness values that meet the preset fitness threshold conditions, so as to use the chip parameter group corresponding to the target parameter fitness value as the target chip parameter group; Adjust the parameter crossover probability and parameter mutation probability based on the fitness distribution of the parameter fitness values of each target chip parameter group; Perform register parameter crossover and register parameter mutation on the register parameters in the target chip parameter group according to the adjusted parameter crossover probability and the adjusted parameter mutation probability, so as to output new register parameters, and jump to execute the step of inputting the register parameters into the prototype verification environment of the target chip module until the new register parameters meet the parameter adjustment conditions, and output the target chip parameter group composed of the current register parameters to the chip configuration interface.

2. The chip parameter optimization method according to claim 1, wherein Also including: Randomly generate several groups of register parameter combinations within the feasible range of register values based on the physical configuration constraints of the target chip module; Respectively form several chip parameter groups based on the register parameters in each register parameter combination.

3. The chip parameter optimization method according to claim 2, wherein Before randomly generating several groups of register parameter combinations within the feasible range of register values based on the physical configuration constraints of the target chip module, it also includes: Obtain the physical configuration constraints of each register in the target chip module; Wherein, the physical configuration constraints include the value range constraints of each register and the value association constraints between the registers.

4. The chip parameter optimization method according to claim 2, wherein Randomly generating several groups of register parameter combinations within the feasible range of register values based on the physical configuration constraints of the target chip module includes: Generate several groups of initial register parameter combinations within the feasible range of register values based on the Monte Carlo random sampling method; Perform physical configuration constraint verification on each initial register parameter combination respectively to obtain several groups of register parameter combinations that meet the physical configuration constraint verification.

5. The chip parameter optimization method according to claim 2, wherein Performing register parameter mutation on the register parameters in the target chip parameter group according to the adjusted parameter mutation probability to output new register parameters includes: Determine the register parameters to be mutated in the register parameters of the target chip parameter group according to the adjusted parameter mutation probability; Perform parameter mutation on the register parameters to be mutated to obtain new register parameters that meet the physical configuration constraints and are within the feasible range.

6. The chip parameter optimization method according to any one of claims 1 to 5, characterized in that, Adjusting the parameter crossover probability and parameter mutation probability based on the fitness distribution of the parameter fitness values of each target chip parameter group includes: If the parameter fitness value of the current target chip parameter group is greater than or equal to the average parameter fitness value, dynamically reduce the parameter crossover probability of the current target chip parameter group according to the crossover probability calculation equation to obtain the adjusted parameter crossover probability; dynamically reduce the parameter mutation probability of the current target chip parameter group according to the mutation probability calculation equation to obtain the adjusted parameter mutation probability; If the parameter fitness value of the current target chip parameter group is less than the average parameter fitness value, then adjust the parameter crossover probability of the current target chip parameter group to the maximum preset parameter crossover probability and adjust the parameter mutation probability of the current target chip parameter group to the maximum preset parameter mutation probability; Wherein, the average parameter fitness value is the average of the parameter fitness values of all the target chip parameter groups.

7. The chip parameter optimization method according to claim 6, wherein The crossover probability calculation equation is: ； Among them, represents the maximum value of the preset parameter crossover probability, represents the maximum parameter fitness value among all target chip parameter groups, represents the average parameter fitness value, represents the fitness value of the larger one of the target chip parameter groups participating in parameter crossover, and the value range is , represents the minimum value of the preset parameter crossover probability.

8. The chip parameter optimization method according to claim 6, wherein The mutation probability calculation equation is: ； Among them, represents the maximum value of the preset parameter mutation probability, represents the maximum parameter fitness value among all target chip parameter groups, represents the average parameter fitness value, represents the fitness value of the target chip parameter group participating in parameter mutation.

9. The chip parameter optimization method according to claim 1, wherein According to the adjusted parameter crossover probability, perform register parameter crossover on the register parameters in the target chip parameter group to output new register parameters, including: Group the target chip parameter groups according to the parameter fitness value to obtain a first target chip parameter group and a second target chip parameter group; wherein, the first target chip parameter group is the target chip parameter group whose fitness value ranking meets the preset fitness ranking condition, and the second target chip parameter group is other target chip groups except the first target chip parameter group; Use the multi-point crossover method and based on the adjusted parameter crossover probability, perform exchange processing on some of the register parameters in the register parameters of the first target chip parameter group to output new register parameters; Based on the adjusted parameter crossover probability, determine the target register parameter sites in the register parameters of the second target chip parameter group, and use the single-point crossover method to perform exchange processing on all the register parameters after the target register parameter sites to output new register parameters.

10. The chip parameter optimization method according to claim 9, wherein, After outputting the new register parameters, it further includes: Perform constraint verification on the physical configuration constraints of the exchanged new register parameters; If the constraint verification is passed, jump to execute the step of inputting the register parameters into the prototype verification environment of the target chip module; If the constraint verification fails, jump to execute the step of performing register parameter crossover on the register parameters in the target chip parameter group according to the adjusted parameter crossover probability.

11. The chip parameter optimization method according to claim 1, wherein Output the target chip parameter group composed of the current register parameters to the chip configuration interface, including: Convert the target chip parameter group composed of the current register parameters into a binary configuration code stream; Write the configuration code stream into the physical register of the target chip through a preset communication interface; Verify whether the actual performance indicators of the target chip are consistent with the simulation results; If they are inconsistent, re-trigger the chip parameter optimization process.

12. The chip parameter optimization method according to claim 1, wherein, The prototype verification environment is an FPGA-based hardware simulation platform; wherein, the hardware simulation platform includes a parameter loading unit for configuring register parameters to the FPGA logic unit through a hardware description language to simulate the physical behavior of the target chip module, a real-time monitoring unit for collecting signal indicators of the target chip module executing a preset verification task, and a dynamic feedback module for adjusting the voltage and temperature conditions of the preset verification task according to the real-time monitoring data during the execution of the preset verification task to approach the actual prototype verification environment; Wherein, the signal indicators include a clock jitter indicator, a signal delay indicator, and a dynamic power consumption indicator.

13. An electronic device, characterized in that, Comprising: A memory for storing a computer program; A processor for executing the computer program to implement the steps of the chip parameter optimization method according to any one of claims 1 to 12.

14. A computer-readable storage medium, characterized in that, For storing a computer program; wherein, when the computer program is executed by a processor, the steps of the chip parameter optimization method according to any one of claims 1 to 12 are implemented.

15. A computer program product, comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by a processor, the steps of the chip parameter optimization method according to any one of claims 1 to 12 are implemented.

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