Pass gate switch gate driver control to prevent no overshoot at switching

Abstract

A pass-gate gate driver control system is presented that includes a gate driver control (110) and a pass-gate switch (106, 108). The pass gate switch includes a P-channel metal oxide semiconductor (PMOS) transistor and an N-channel metal oxide semiconductor (NMOS) transistor. The gate driver control includes a through-gate charge injector (112) arranged to vary a charging speed and / or a discharging speed of charge at the gate of the PMOS transistor and / or the NMOS transistor.

Description

Technical Field

[0001] The present disclosure relates to a pass gate driver control system, a gate driver control for such a pass gate driver control system, a pass gate charge injector for such a gate driver control, and an input voltage sensing timer for such a pass gate driver control system. Background Art

[0002] A passgate switch is a component in digital circuit systems for switching signals or controlling the data flow within a circuit. It functions in integrated circuits, especially in complementary metal oxide semiconductor (CMOS) technology. A passgate switch typically includes two transistors, namely a P-channel metal oxide semiconductor (PMOS) and an N-channel metal oxide semiconductor (NMOS), which work together to form a transmission gate. When the input signal at the gate terminal of the PMOS transistor is at a low voltage level (logic 0), the PMOS transistor can operate as a switch, and when the input signal at the gate of the NMOS transistor is at a high voltage level (logic 1), the NMOS transistor can be used as a switch. When the control signals (i.e., input signals) of these transistors are appropriately manipulated, the passgate switch allows a signal to pass through or be blocked, essentially acting as an on / off switch for the flow of data or electrical signals.

[0003] Passgate switches are used in various digital circuit applications such as multiplexers, logic gates, flip-flops, and more complex circuits. They enable efficient routing of signals, data transfer, and manipulation within these circuits, thus contributing to the overall functionality and operation of electronic devices.

[0004] Overshoot and undershoot voltages during switching of passgate switches can damage the system due to overvoltage stress. External resistor-inductor-capacitor (RLC) components of a printed circuit board (PCB), and passgate capacitance mismatch caused by size differences between NMOS and PMOS are the key problem sources leading to overshoot voltage. Summary of the Invention

[0005] An overview of aspects of specific examples disclosed herein is set forth below. It should be understood that presenting these aspects is merely to provide a brief overview of these specific embodiments to the reader, and these aspects are not intended to limit the scope of the present disclosure. Indeed, the present disclosure may cover various aspects and / or combinations of aspects that may not be set forth.

[0006] The present disclosure aims to overcome the disadvantages identified in the background art section.

[0007] The present application proposes a gate driver control scheme for controlling a through-gate switch such that no overshoot will be observed at the output during switching. An improved gate driver control is proposed, which includes a through-gate charge injector. The gate driver control may further include an input voltage sensing timer. The gate driver control may further include an output voltage sensing timer. This solution of the present disclosure enables fast switching through the gate while achieving no overshoot within a wide supply voltage range without consuming active current.

[0008] According to one aspect of the present disclosure, a through-gate gate driver control system is proposed. The through-gate gate driver control system may include a gate driver control. The through-gate gate driver control system may further include a through-gate switch, which includes a PMOS transistor and an NMOS transistor. The gate driver control may include a through-gate charge injector, which is arranged to change the charging speed and / or discharging speed of the charge at the gates of the PMOS transistor and / or the NMOS transistor of the through-gate switch.

[0009] In an embodiment, the through-gate gate driver control system may include two through-gate switches, each driven by a separate gate driver control.

[0010] In an embodiment, the first gate driver control may linearly control the on and off states of the first through-gate switch. The second gate driver control may linearly control the on and off states of the second through-gate switch.

[0011] According to one aspect of the present disclosure, a gate driver control is proposed. The gate driver control may be part of a through-gate gate driver control system having one or more of the above features. The gate driver control may include a through-gate charge injector, which is arranged to change the charging speed and / or discharging speed of the charge at the gates of the PMOS transistor and / or the NMOS transistor of the through-gate switch.

[0012] In an embodiment, the gate driver control may further include an input voltage sensing timer, which is arranged to provide a first single trigger signal to the through-gate charge injector for accelerating the turn-on duration of the through-gate switch. The duration may be determined by the input voltage of the input voltage sensing timer.

[0013] In an embodiment, the gate driver control may further include an output voltage sensing timer, which is arranged to provide a second single trigger signal to the through-gate charge injector to slow down the acceleration of the turn-on of the through-gate switch after accelerating the turn-on duration of the through-gate switch.

[0014] According to one aspect of the present disclosure, a through-gate charge injector is proposed. The through-gate charge injector can be part of a gate driver control having one or more of the above characteristics. The through-gate charge injector can be arranged to change the charging speed and / or discharging speed of the charge at the gates of the PMOS transistor and / or NMOS transistor of the through-gate switch.

[0015] In an embodiment, the through-gate charge injector can be arranged to receive a first single trigger signal from an input voltage sensing timer of the gate driver control for accelerating the conduction duration of the through-gate switch. The duration can be determined by the input voltage of the input voltage sensing timer.

[0016] In an embodiment, the through-gate charge injector can be arranged to receive a second single trigger signal from an output voltage sensing timer of the gate driver control to slow down the acceleration of the conduction of the through-gate switch after accelerating the conduction duration of the through-gate switch.

[0017] According to one aspect of the present disclosure, an input voltage sensing timer for a through-gate driver control system having one or more of the above characteristics is proposed. The input voltage sensing timer can be arranged to provide a first single trigger signal to the through-gate charge injector for accelerating the conduction duration of the through-gate switch of the through-gate driver control system. The duration can be determined by the input voltage of the input voltage sensing timer. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Embodiments of the present disclosure will now be described by way of example only with reference to the accompanying drawings, in which corresponding reference numerals indicate corresponding parts, in the drawings:

[0019] Figure 1 An example through-gate driver control system architecture for achieving no overshoot when switching through-gates according to one aspect of the present disclosure is shown;

[0020] Figure 2 A schematic diagram of an example gate driver control circuit according to one aspect of the present disclosure is shown;

[0021] Figure 3 A graph showing an example node voltage response during system activation is shown;

[0022] Figure 4 A schematic diagram of an example input voltage sensing timer according to one aspect of the present disclosure is shown;

[0023] Figure 5 A graph showing an example single trigger pulse duration tracking with an input is shown;

[0024] Figure 6 Shows an exemplary output voltage sense timer schematic according to one aspect of the present disclosure;

[0025] Figure 7 Shows an exemplary comparator circuit of an output voltage sense timer according to one aspect of the present disclosure; and

[0026] Figure 8 Shows various non-limiting examples of equivalent resistor elements of input and output sense voltage timers.

[0027] The drawings are only intended for illustrative purposes and are not used as a limitation on the scope of protection as defined by the claims. Detailed Description

[0028] It will be readily understood that the components of the embodiments generally described herein and illustrated in the drawings can be arranged and designed in a variety of different configurations. Accordingly, the following more detailed description of the various embodiments as represented in the drawings is not intended to limit the scope of the present disclosure, but merely represents various embodiments. Although various aspects of the embodiments are presented in the drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0029] The described embodiments are considered to be illustrative in all respects and not restrictive. Accordingly, the scope of the present disclosure is indicated by the appended claims rather than by this detailed description. All changes within the meaning and scope of the equivalents of the claims will be included within their scope.

[0030] Throughout this specification, references to features, advantages, or similar language do not imply that all features and advantages that can be realized by the present disclosure should be present in any single example of the present disclosure or in any single example of the present disclosure. Rather, the language referring to features and advantages is understood to mean that a particular feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the discussions of features and advantages and similar language throughout this specification may, but do not necessarily, refer to the same example.

[0031] Furthermore, the described features, advantages, and characteristics of the present disclosure can be combined in any suitable manner in one or more embodiments. Based on the description herein, those skilled in the relevant art will recognize that the present disclosure can be practiced without one or more of the specific features or advantages of a particular embodiment. In other cases, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments of the present disclosure. Throughout this specification, references to "one embodiment", "an embodiment", or similar language mean that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases "in one embodiment", "in an embodiment", and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

[0032] As described in the background art, overshoot and undershoot voltages during switching through a gate switch can be detrimental. The overshoot voltage can manifest as voltage ringing during switching. Reducing the slew rate of the gate voltage during switching mitigates the overshoot, but reduces the switching transition time, thus slowing down the system. The limitation of low supply current and the requirement for large supply variations from, for example, 1.08 to 5.5 V are key challenges to overcome.

[0033] To overcome the problem of having an overshoot voltage at OUTPUT, the present disclosure proposes an electrical mechanism for creating a "fast start, then slow down" response, which can accelerate the transition time in a linear manner. The solution of the present disclosure includes a new gate driver control system for generating such a response. As will be explained in more detail below, the gate driver control receives signals from various pin sources such as the SELECT pin, the INPUT net, and the OUTPUT net. These signals can then regulate the charge injection through the gate charge injector to accelerate or slow down the charging and discharging through the gate switch, thereby controlling the overshoot and undershoot phenomena. Additionally, the electrical mechanism has no active current and is adaptable to power supply, input voltage, and output voltage variations.

[0034] The solution of the present disclosure advantageously implements a low-power, wide-supply through-gate switch gate driver control for a "fast start, then slow down" response to prevent overshoot during switching.

[0035] Figure 1Shows the through-gate driver control system architecture 100 of an example implementation of the present disclosure. System 100 may include input control logic 102, a break-before-make circuit 104, two through-gate switches 106, 108, also referred to hereinafter as through-gate switch 0 (106) and through-gate switch 1 (108). The two through-gate switches 106, 108 are generally similar or identical in internal design. System 100 may also include two gate driver controls 110, one for each through-gate switch 106, 108. Signal lines are between the components of system 100. The markings along the lines and arrows indicate various signals.

[0036] In an implementation of the present disclosure, the gate driver control 110 includes a through-gate charge injector 112, an input voltage sense timer 114, and an output voltage sense timer 116, which will be further explained hereinafter.

[0037] The proposed through-gate driver control system architecture 100 achieves no overshoot when switching the through-gates 106, 108.

[0038] The overall function of the proposed gate driver (i.e., the through-gate driver control 110) is to linearly control the on and off states of the through-gate switches 106, 108, which are the Figure 1 through-gate switch 0 (106) and through-gate switch 1 (108) in

[0039] The through-gate charge injector 112 can change the charging and discharging speeds of the charges to the gates of the NMOS 106B transistor and the PMOS 106A transistor of the through-gate switches 106, 108 during switching.

[0040] Advantageously, system 100 and in particular the gate driver control as an implementation of the through-gate driver control 110 of the present disclosure ensures adaptability to a wide supply voltage while consuming substantially no direct current (DC).

[0041] Figure 2A schematic diagram of a complete top - level gate driver control circuit 110 of an example implementation of the present disclosure is shown. The "rise fast, then slow down" response is reflected at nets VN and VP. The output nets VN and VP drive the NMOS gate and PMOS gate through gate switches 106, 108 respectively. When the SEL_IN signal is in the high state, the selection through gate switches 106, 108 is turned on. Thus, when SEL_IN is high and the VN and VP voltages are low and high respectively, devices MN2 and MP4 are turned on during the initial state.

[0042] When SEL_IN changes from high to low, MN2 and MP4 turn off and MN3 and MP3 turn on. At the same time, during the transition state, MN1 is triggered by a single - trigger signal Spulse_a. When MN1 turns on, net Vb1 will be pulled to ground and MP1, MP2, MP5, and MN4 will turn on, which generates a bias current Ibias through this network circuit. During the turn - on transition state, this bias network will dominate MN3 and MP3 first. The activated Ibias through MP1 is mirrored to MP2 and MN4 as Ibias2 and Ibias4 respectively. MP2 and MP4 inject large charges into the NMOS gate and PMOS gate quickly respectively. Thus, a "rise fast" response will be observed at VN and VP, where the voltage VN changes from low to high quickly and VP changes from high to low.

[0043] The single - trigger of Spulse_a through MP1, MP2, MP5, and MN4 is to accelerate the turn - on of the gate switches within a short duration. The duration of Spulse_a will be determined by the input voltage VIN through the input voltage timer 114. This is to ensure that the correct amount of charge is injected so as not to cause overshoot at the output while still maintaining a fast turn - on time. Once the single - trigger signal ends, the gate driver control will start to slow down the turn - on of the gate switches 106, 108 through the conduction of MN3 and MP3. The purpose of the RC elements R1 and C1 and R2 is to slow down the rising and falling voltages of VN and VP respectively during the transition time of the turn - on of the gate switches 106, 108. The "then slow down" response is further performed by the output voltage sensing timer circuit 116. When the voltage is lower than a Vth, which is lower than the power supply voltage and the output voltage sensing timer 116, the output voltage VOUT is detected by biasing MP6. The output voltage sensing timer 116 will be activated and generate a single - trigger signal Spulse_b to turn on this network and further perform the "then slow down" response. When the voltages at VN and VP are stable and the gate switches are turned on, MN3 and MP3 are the main pull - down device for net VP and the pull - up device for net VN respectively. This network branch will be turned on throughout the turn - on time of the gate switches.

[0044] Figure 3A graph showing various node voltage responses 300 during system activation is presented. The x-axis represents time (in milliseconds), and the Y-axis represents the voltage between 0V and 5V. From top to bottom, the SEL_IN signal, the Spulse_a output signal from the input voltage sense timer 114, the Spulse_b output signal from the output voltage sense timer 116, VP and VN, and the OUTPUT signal through the gate switches 106, 108 ( Figure 1 OUT in

[0045] It can be seen that the OUTPUT curve exhibits a "fast start, then slow down" response to prevent overshoot during switching (the fast start is depicted as 302; the subsequent slowdown is depicted as 304). VP and VN show the gate voltages through the gate switches 106, 108 controlled by the gate driver control 110. When the gate driver control 110 is activated by SEL_IN changing from high to low, we can observe the activation of the single-shot signal Spulse_a and the subsequent Spulse_b.

[0046] The pulse width of the single-shot signal Spulse_a can be determined by the voltage level of VIN through the input voltage sense timer 114, as shown in Figure 4 the example implementation such as. The circuit of the input voltage sense timer 114 can ensure the correct timing of the single-shot duration for the "fast start". The voltage at the input provides information to the input voltage sense timer 114 to change the pulse width of the single-shot through MP7, MN7, R3, and C2. The equivalent resistors of MP7, MN7, and R3 will be dominated by the INPUT voltage to change the time of the single-shot duration. When SEL_IN changes from high to low, a single-shot signal is generated. In the steady state, when SEL_IN is high or low, Spulse_a will be low, as shown in Table 1.

[0047] SEL_IN x y Spulse_a 0 0 1 0 1 1 0 0

[0048] Table 1: Input Voltage Sense Timer Truth Table

[0049] As shown in Table 2, when both nodes x and y are instantaneously high, the single-shot Spulse_a is generated. Figure 5 An example of the pulse width varying with the detected INPUT voltage is shown. When the input voltage is high, a longer pulse width may be required because the OUTPUT voltage takes more time to rise. If the OUTPUT voltage does not need to rise too high, a shorter pulse may be sufficient.

[0050] x y Spulse_a SEL_IN status 0 0 0 low to high 1 0 0 static 0 1 0 static 1 1 1 high to low

[0051] Table 2: AND Gate Truth Table

[0052] The Spulse_b signal of the output voltage sensing timer 116 can be determined, such as Figure 6 as shown in the example implementation of Figure 6 In the example of

[0053] Figure 6 , Spulse_b will be generated only when VOUT is lower than Vth. This is to detect the OUTPUT voltage of the gate driver to know from what voltage the rise occurs through the gate switches 106, 108. Similar to the input voltage sensing timer 114, the one-shot delay elements MP8, MN8 and R4 and C3 dominate the width of Spulse_b. The equivalent resistance of MP8, MN8 and R4 is dominated by the output voltage. Therefore, with this gate control mechanism, a fast switching time without overshoot voltage at the output can be achieved during the switching through the gate switches 106, 108. Additionally, the "slow down later" response is further enforced by the output voltage sensing timer 116. Figure 7 In Figure 1 an example implementation of the comparator 602 is shown, which has an example implementation of the gate driver control circuit 110 for the gate switch 0 (106) in

[0054] When the voltages at both nets IN0 and IN1 are high at least one Vth, net_c1 and net_c2 will be high and low respectively. The states of net_c1 and net_c2 are set by the level shifters (MP10, MP11, MN10, MN11) and MP9 and MN9. During this time, the AND-gate will disable the second one-shot signal to the gate charge injector 112 through the output voltage sensing timer 116 so as not to propagate to Spulse_b. When IN0 is low and IN1 is high, IN0_b will be high. Therefore, net_c1 and net_c2 will be low and high respectively, allowing the one-shot signal from the output voltage sensing timer 116 to the gate charge injector 112 to better enhance the "slow down later" state and prevent overshoot at the OUTPUT during switching. Figure 8 The input voltage sensing timer 114 and the output voltage sensing timer 116 can each include an equivalent resistor element 800, such as

[0055] The solution of the present disclosure advantageously enables a wide power supply and input / output voltage range. The power supply can be, for example, in the range from 1.08V to 5.5V. The OUTPUT range can be, for example, in the range from 0V to 5.5V.

[0056] The solution of the present disclosure advantageously allows for low power supply current. The gate driver control 110 does not require any active circuitry that consumes current.

[0057] Those skilled in the art can understand and realize other variations of the disclosed embodiments by studying the drawings, the disclosure, and the appended claims when practicing the claimed invention. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting their scope.

Claims

1. A through-gate driver control system (100) comprising: A gate driver control (110); And A through-gate switch (106, 108), the through-gate switch comprising a P-channel metal-oxide-semiconductor (PMOS) transistor and an N-channel metal-oxide-semiconductor (NMOS) transistor, Wherein the gate driver control includes a through-gate charge injector (112) arranged to change a charging rate and / or a discharging rate of charge at a gate of the PMOS transistor and / or the NMOS transistor.

2. The through-gate driver control system according to claim 1, comprising two through-gate switches (106, 108), each through-gate switch being driven by a separate gate driver control (110).

3. The through-gate driver control system according to claim 2, wherein a first gate driver control linearly controls an on and off state of a first through-gate switch (106), and a second gate driver control linearly controls an on and off state of a second through-gate switch (108).

4. The through-gate driver control system according to any one of the preceding claims, wherein the gate driver control further comprises: An input voltage sensing timer (114) arranged to provide a first single trigger signal (Spulse_a) to the through-gate charge injector for accelerating turn-on of the through-gate switch for a duration, Wherein the duration is determined by an input voltage (VIN) through the input voltage sensing timer.

5. The through-gate driver control system according to any one of the preceding claims, wherein the gate driver control further comprises: An output voltage sensing timer (116) arranged to provide a second single trigger signal (Spulse_b) to the through-gate charge injector to slow down the acceleration of the turn-on of the through-gate switch after the turn-on of the through-gate switch has been accelerated for the duration.

6. A gate driver control (110) for a through-gate driver control system (100) according to any one of claims 1 to 5, Wherein the gate driver control includes a through-gate charge injector (112) arranged to change a charging rate and / or a discharging rate of charge at a gate of a PMOS transistor and / or an NMOS transistor of a through-gate switch (106, 108).

7. The gate driver control according to claim 6, further comprising: An input voltage sensing timer (114) arranged to provide a first single trigger signal (Spulse_a) to the through-gate charge injector for accelerating turn-on of the through-gate switch for a duration, Wherein the duration is determined by an input voltage (VIN) through the input voltage sensing timer.

8. The gate driver control according to claim 6 or claim 7, further comprising: An output voltage sensing timer (116) arranged to provide a second single trigger signal (Spulse_b) to the through-gate charge injector to slow down the acceleration of the conduction of the through-gate switch after the conduction of the through-gate switch has been accelerated for the duration.

9. A through-gate charge injector (112) for a gate driver control (110) according to any one of claims 6 to 8, wherein the through-gate charge injector is arranged to change the charging rate and / or discharging rate of the charge at the gates of the PMOS transistor and / or NMOS transistor of the through-gate switch (106, 108).

10. The through-gate charge injector according to claim 9, wherein the through-gate charge injector is arranged to receive a first single trigger signal (Spulse_a) from an input voltage sensing timer (114) of the gate driver control for accelerating the conduction of the through-gate switch for a duration, wherein the duration is determined by an input voltage (VIN) through the input voltage sensing timer.

11. The through-gate charge injector according to claim 9 or claim 10, wherein the through-gate charge injector is arranged to receive a second single trigger signal (Spulse_b) from an output voltage sensing timer (116) of the gate driver control to slow down the acceleration of the conduction of the through-gate switch after the conduction of the through-gate switch has been accelerated for the duration.

12. An input voltage sensing timer (114) for a through-gate gate driver control system (100) according to any one of claims 1 to 5, wherein the input voltage sensing timer is arranged to provide a first single trigger signal (Spulse_a) to a through-gate charge injector for accelerating the conduction of a through-gate switch of the through-gate gate driver control system for a duration, wherein the duration is determined by an input voltage (VIN) through the input voltage sensing timer.

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