Method and apparatus to construct waveguide for delay

Abstract

The invention relates to a method and apparatus to construct a waveguide for delay. An example apparatus includes: a first metal layer (520, 715, 910) including a first delay line (305, 615, 810) having a surface region; and a second metal layer (560, 725, 930) comprising a second delay line (320, 640, 820) having a surface region overlapping the surface region of the first delay line; and an insulating layer (540, 720, 920) coupled between the first metal layer and the second metal layer.

Description

Technical Field

[0001] This description relates generally to waveguides, and in particular, to methods and apparatus to construct waveguides for delay. Background Art

[0002] As electronic devices continue to become more complex, circuit systems have become capable of operating at faster speeds while reducing package size. The transmission speeds of communication systems continue to increase as electronic devices continue to evolve. Consequently, receiver circuit systems must accurately sample received signals at faster speeds. Receiver circuit systems include timing circuitry to sequence the sample transmissions using multiple relatively slow analog-to-digital converters (ADCs). The timing circuitry delays the edges of a clock signal to generate multiple delayed clock signals that are supplied to the ADCs, thereby sequencing the sampling of the received signals. Summary of the Invention

[0003] An example method and apparatus for constructing a waveguide for delay includes: a first metal layer including a first delay line having a surface area; a second metal layer including a second delay line having a surface area overlapping the surface area of ​​the first delay line; and an insulating layer coupled between the first and second metal layers. Other examples are described.

[0004] An example apparatus for constructing a waveguide for delay includes a first waveguide having a surface; a second waveguide having a surface overlapping the surface of the first waveguide; a first layer having the first waveguide; a second layer having the second waveguide; a third layer coupled between the first and second layers; first delay circuitry including the first waveguide; and second delay circuitry including the second waveguide. Other examples are described.

[0005] An example apparatus for a method and apparatus for constructing a waveguide for delay includes: a first layer including a first electrical trace having a surface area; a second layer including a second electrical trace having a surface area overlapping the surface area of ​​the first electrical trace; a third layer coupled between the first and second layers; a first analog-to-digital converter (ADC); and a second ADC coupled to the first ADC via the first and second electrical traces. Other examples are described. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a block diagram of example receiver circuitry including example timing circuitry that uses a waveguide configured as delay circuitry to delay a clock signal.

[0007] Figure 2is a block diagram of an example analog-to-digital converter (ADC) that includes a waveguide configured as delay circuitry to delay an analog input signal.

[0008] Figure 3 for Figure 1 and 2 A perspective view of an example implementation of a waveguide.

[0009] Figure 4 for Figure 3 A top view of an example implementation of a waveguide.

[0010] Figures 5A to 5C for Figure 3 and 4 Cross-sectional view of an example implementation of a waveguide.

[0011] Figure 6 for Figure 1 and 2 A top view of an alternative example embodiment of a waveguide.

[0012] Figures 7A to 7F for Figure 6 Cross-sectional view of an example implementation of a waveguide.

[0013] Figure 8 for Figure 1 and 2 A top view of an alternative example embodiment of a waveguide.

[0014] Figure 9A and 9B for Figure 8 Cross-sectional view of an example implementation of a waveguide.

[0015] The drawings are not necessarily drawn to scale. In general, like reference numerals in one or more of the drawings and this description refer to identical or similar features and / or parts (functionally and / or structurally). Although the drawings show regions with distinct lines and boundaries, some or all of these lines and boundaries may be idealized. In practice, boundaries or lines may be invisible, blended, or irregular. DETAILED DESCRIPTION

[0016] As electronic devices continue to become more complex, circuit systems have become capable of operating at faster speeds while reducing package size. The transmission speeds of communication systems continue to increase as electronic devices continue to evolve. Consequently, receiver circuit systems must accurately sample received signals at faster speeds. Receiver circuit systems include timing circuitry to sequence the sample transmissions using multiple relatively slow analog-to-digital converters (ADCs). The timing circuitry delays the edges of a clock signal to generate multiple delayed clock signals that are supplied to the ADCs, thereby sequencing the sampling of the received signals.

[0017] Some timing circuit systems use the properties of waveguides (e.g., also known as electrical traces, delay lines, etc.) to slow down the propagation of continuous signals, thereby delaying the continuous signals. Each waveguide has parasitic inductance and capacitance, which adjust the propagation speed of the continuous signal over the length of the waveguide. Most designers implement design techniques to reduce the parasitic inductance and capacitance of the waveguide to prevent non-ideal performance. In some instances, designers reduce the length of the waveguide to reduce parasitic inductance. In other instances, designers position traces with currents propagating in opposite directions close to each other to reduce the magnetic field generated by the signal.

[0018] Some designers use the parasitic inductance of waveguides to slow signal propagation, delaying continuous signals over shorter lengths. However, in some designs, extending the waveguide to increase the parasitic impedance is not possible due to size limitations. In some such designs, designers attempt to increase the parasitic impedance of the waveguide without increasing its length.

[0019] As described herein, one method for increasing the parasitic impedance per waveguide length is to supply a differential signal to parallel waveguides in opposite directions. In this instance, the currents of the differential signal propagate through the parallel waveguides in the same direction. The propagation of the currents in the same direction causes the waveguides to have overlapping magnetic fields. This resulting magnetic field increases the parasitic inductance of the parallel waveguides. By increasing the parasitic inductance of the parallel waveguides, the length of the electrical trace required to generate the delay duration is reduced.

[0020] Examples described herein include methods and apparatus for constructing a waveguide for delay. In some described examples, the waveguide is constructed across multiple layers (e.g., also referred to as metal layers) and has overlapping surface areas to increase the parasitic capacitance of the waveguide. In such described examples, an example arrangement includes a first waveguide and a second waveguide. The first waveguide has a first surface and is located in a first layer of the arrangement. The second waveguide has a second surface and is located in a second layer of the arrangement. The package further includes a third layer that is non-conductive to separate the first and second layers of the arrangement. The waveguide is constructed so that the surface areas of the first and second surfaces overlap.

[0021] Advantageously, this positioning of the waveguide increases capacitance by forming two parallel plates in different layers of the arrangement. Advantageously, increasing the capacitance of the waveguide reduces the propagation speed of the signal through the waveguide. Advantageously, reducing the propagation speed of the signal through the waveguide increases the delay per length of the waveguide. Advantageously, this positioning of the waveguide in the arrangement reduces the footprint of the timing circuitry that includes the waveguide.

[0022] Figure 1FIG1 is a block diagram of an example communication system 100 including an antenna 103 and receiver circuitry 106. In some examples, communication system 100 is part of an analog front end (AFE), which may further include transmitter circuitry. In such examples, communication system 100 receives signals from the transmitter circuitry. In other examples, communication system 100 receives signals from the transmitter circuitry at another location. Figure 1 In the example of , receiver circuitry 106 includes clock circuitry 109, timing circuitry 112, first ADC 115, second ADC 118, third ADC 121, fourth ADC 124, and digital signal processing circuitry 127. Alternatively, receiver circuitry 106 may be modified to include any plurality of ADCs.

[0023] exist Figure 1 In the example of , timing circuitry 112 includes a first delay circuitry 130 , a second delay circuitry 133 , a third delay circuitry 136 , a fourth delay circuitry 139 , a fifth delay circuitry 142 , and a sixth delay circuitry 145 . Figure 1 In the example, the delay circuit system 130 includes a first waveguide 148 and a second waveguide 151, the delay circuit system 133 includes a third waveguide 154 and a fourth waveguide 157, the delay circuit system 136 includes a fifth waveguide 160 and a sixth waveguide 163, the delay circuit system 139 includes a seventh waveguide 166 and an eighth waveguide 169, the delay circuit system 142 includes a ninth waveguide 172 and a tenth waveguide 175, and the delay circuit system 145 includes an eleventh waveguide 178 and a twelfth waveguide 181.

[0024] Antenna 103 has terminals coupled to receiver circuitry 106. Antenna 103 can be communicatively coupled to transmitter circuitry, which supplies electromagnetic signals to receiver circuitry 106 through antenna 103. In some examples, a connector, such as a coaxial cable, couples antenna 103 to receiver circuitry 106. In such instances, the connector allows antenna 103 and receiver circuitry 106 to be located in different locations.

[0025] Receiver circuitry 106 has a terminal coupled to antenna 103. Receiver circuitry 106 may have another terminal coupled to external circuitry, thereby allowing an external device to receive data from a received transmission. In some examples, receiver circuitry 106 is a component of analog front-end (AFE) circuitry, which may also include transmitter circuitry. In such examples, digital signal processing circuitry 127 may be shown external to receiver circuitry 106.

[0026] Clock circuitry 109 has a first terminal and a second terminal. The first terminal of clock circuitry 109 is coupled to timing circuitry 112 and ADC 115. The second terminal of clock circuitry 109 is coupled to timing circuitry 112. In some examples, clock circuitry 109 is a crystal oscillator. In such examples, clock circuitry 109 is coupled to an external crystal component. In other examples, clock circuitry 109 is a resistor-capacitor oscillator, or an alternative form of oscillator circuitry.

[0027] Timing circuitry 112 has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first terminal of timing circuitry 112 is coupled to clock circuitry 109 and ADC 115. The second terminal of timing circuitry 112 is coupled to clock circuitry 109. The third terminal of timing circuitry 112 is coupled to ADC 118. The fourth terminal of timing circuitry 112 is coupled to ADC 121. The fifth terminal of timing circuitry 112 is coupled to ADC 124. Alternatively, timing circuitry 112 can be modified to include any number of terminals to be coupled to any number of ADCs of receiver circuitry 106.

[0028] ADC 115 has a first terminal, a second terminal, and a third terminal. The first terminal of ADC 115 is coupled to antenna 103 and ADCs 118, 121, 124. The second terminal of ADC 115 is coupled to timing circuitry 112. The third terminal of ADC 115 is coupled to digital signal processing circuitry 127.

[0029] ADC 118 has a first terminal, a second terminal, and a third terminal. The first terminal of ADC 118 is coupled to antenna 103 and ADCs 115, 121, 124. The second terminal of ADC 118 is coupled to timing circuitry 112. The third terminal of ADC 118 is coupled to digital signal processing circuitry 127.

[0030] ADC 121 has a first terminal, a second terminal, and a third terminal. The first terminal of ADC 121 is coupled to antenna 103 and ADCs 115, 118, 124. The second terminal of ADC 121 is coupled to timing circuitry 112. The third terminal of ADC 121 is coupled to digital signal processing circuitry 127.

[0031] ADC 124 has a first terminal, a second terminal, and a third terminal. The first terminal of ADC 124 is coupled to antenna 103 and ADCs 115, 118, 121. The second terminal of ADC 124 is coupled to timing circuitry 112. The third terminal of ADC 124 is coupled to digital signal processing circuitry 127.

[0032] Digital signal processing circuitry 127 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of digital signal processing circuitry 127 is coupled to ADC 115. The second terminal of digital signal processing circuitry 127 is coupled to ADC 118. The third terminal of digital signal processing circuitry 127 is coupled to ADC 121. The fourth terminal of digital signal processing circuitry 127 is coupled to ADC 124. In some examples, digital signal processing circuitry 127 is coupled to external circuitry. In such examples, digital signal processing circuitry 127 allows the external circuitry to receive data from ADCs 115, 118, 121, and 124.

[0033] Delay circuitry 130 has a first terminal and a second terminal. The first terminal of delay circuitry 130 is coupled to clock circuitry 109 and ADC 115. The second terminal of delay circuitry 130 is coupled to ADC 118 and delay circuitry 136. Delay circuitry 133 has a first terminal and a second terminal. The first terminal of delay circuitry 133 is coupled to clock circuitry 109. The second terminal of delay circuitry 133 is coupled to delay circuitry 139.

[0034] Delay circuitry 136 has a first terminal and a second terminal. The first terminal of delay circuitry 136 is coupled to ADC 118 and delay circuitry 130. The second terminal of delay circuitry 136 is coupled to ADC 121 and delay circuitry 142. Alternatively, the second terminal of delay circuitry 136 may be coupled to delay circuitry 142 via one or more additional instances of delay circuitry. Delay circuitry 139 has a first terminal and a second terminal. The first terminal of delay circuitry 139 is coupled to delay circuitry 133. The second terminal of delay circuitry 139 is coupled to delay circuitry 145. Alternatively, the second terminal of delay circuitry 139 may be coupled to delay circuitry 145 via one or more additional instances of delay circuitry.

[0035] Delay circuitry 142 has a first terminal and a second terminal. The first terminal of delay circuitry 142 is coupled to ADC 121 and delay circuitry 136. The second terminal of delay circuitry 142 is coupled to ADC 124. Alternatively, the first terminal of delay circuitry 142 may be coupled to delay circuitry 136 via one or more additional instances of delay circuitry. Delay circuitry 145 has a terminal coupled to delay circuitry 139. Alternatively, the terminal of delay circuitry 145 may be coupled to delay circuitry 139 via one or more additional instances of delay circuitry.

[0036] Waveguide 148 (e.g., also referred to as an electrical trace, delay line, etc.) has a first terminal and a second terminal. The first terminal of waveguide 148 is coupled to clock circuitry 109 and ADC 115. The second terminal of waveguide 148 is coupled to waveguide 151. Waveguide 151 has a first terminal and a second terminal. The first terminal of waveguide 151 is coupled to waveguide 148. The second terminal of waveguide 151 is coupled to ADC 118 and delay circuitry 136.

[0037] Waveguide 154 has a first terminal and a second terminal. The first terminal of waveguide 154 is coupled to clock circuitry 109. The second terminal of waveguide 154 is coupled to waveguide 157. Waveguide 157 has a first terminal and a second terminal. The first terminal of waveguide 157 is coupled to waveguide 154. The second terminal of waveguide 157 is coupled to delay circuitry 139.

[0038] Waveguide 160 has a first terminal and a second terminal. The first terminal of waveguide 160 is coupled to ADC 118 and delay circuitry 130. The second terminal of waveguide 160 is coupled to waveguide 163. Waveguide 163 has a first terminal and a second terminal. The first terminal of waveguide 163 is coupled to waveguide 160. The second terminal of waveguide 163 is coupled to ADC 121 and delay circuitry 142.

[0039] Waveguide 166 has a first terminal and a second terminal. The first terminal of waveguide 166 is coupled to delay circuitry 133. The second terminal of waveguide 166 is coupled to waveguide 169. Waveguide 169 has a first terminal and a second terminal. The first terminal of waveguide 169 is coupled to waveguide 166. The second terminal of waveguide 169 is coupled to delay circuitry 145.

[0040] Waveguide 172 has a first terminal and a second terminal. The first terminal of waveguide 172 is coupled to ADC 121 and delay circuitry 136. The second terminal of waveguide 172 is coupled to waveguide 175. Waveguide 175 has a first terminal and a second terminal. The first terminal of waveguide 175 is coupled to delay circuitry 136. The second terminal of waveguide 175 is coupled to ADC 124.

[0041] Waveguide 178 has a first terminal and a second terminal. The first terminal of waveguide 178 is coupled to delay circuitry 139. The second terminal of waveguide 178 is coupled to waveguide 181. Waveguide 181 has a terminal coupled to waveguide 178. In some examples, waveguide 181 is coupled to additional circuitry.

[0042] exist Figure 1In the examples of FIG. 1 , waveguides 148, 151, 154, 157, 160, 163, 166, 169, 172, 175, 178, 181 are described as having terminals. Alternatively, the terminals of waveguides 148, 151, 154, 157, 160, 163, 166, 169, 172, 175, 178, 181 may be described as endpoints. In some examples, one or more terminals of waveguides 148, 151, 154, 157, 160, 163, 166, 169, 172, 175, 178, 181 are directly coupled. In other examples, one or more terminals of waveguides 148, 151, 154, 157, 160, 163, 166, 169, 172, 175, 178, 181 are coupled via one or more through-holes. In yet other examples, one or more of the terminals of the waveguides 148, 151, 154, 157, 160, 163, 166, 169, 172, 175, 178, 181 are coupled by a support. Alternatively, the terminals of the waveguides 148, 151, 154, 157, 160, 163, 166, 169, 172, 175, 178, 181 may be coupled by alternative components.

[0043] In example operation, antenna 103 receives a transmission. Antenna 103 transmits an analog input signal (ANALOG IN ) is supplied to the ADCs 115, 118, 121, 124. The ADCs 115, 118, 121, 124 sample the analog input signal in response to the edges of the clock signal. The ADCs 115, 118, 121, 124 generate digital values ​​(D) representing the sampled values ​​of the analog input signal. OUT_0 、D OUT_1 、D OUT_2 、D OUT_N ). Once the ADCs 115, 118, 121, 124 generate digital values, the ADCs 115, 118, 121, 124 can sample the analog input signal again. The ADCs 115, 118, 121, 124 accurately convert the analog input signal at a data rate that is up to the conversion rate of each of the ADCs 115, 118, 121, 124. The timing circuitry 112 generates a plurality of delayed clock signals to sequence the sampling of the analog inputs by the ADCs 115, 118, 121, 124. In such example operation, the ADCs 115, 118, 121, 124 sample the analog inputs sequentially in response to the clock signal or in response to one of the delayed clock signals. This sequencing allows the receiver circuitry 106 to receive transmissions at a rate that is greater than the conversion rate of an individual instance of the ADCs 115, 118, 121, 124.

[0044] In example operation, the clock circuitry 109 generates a differential clock signal pair comprising a non-inverted clock signal (CLK) and an inverted clock signal (CLK). The ADC 115 samples the analog input signal in response to the edges of the non-inverted clock signal. The delay circuitry 130, 133 generates a first pair of delayed clock signals comprising a first non-inverted delayed clock signal (CLK1) and a first inverted delayed clock signal by delaying the edges of the clock signal by a first delay duration. The ADC 118 samples the analog input signal in response to the edges of the first non-inverted delayed clock signal. The delay circuitry 136, 139 generates a second pair of delayed clock signals comprising a second non-inverted delayed clock signal (CLK2) and a second inverted delayed clock signal by delaying the edges of both signals of the first pair of delayed clock signals by a second delay duration. The ADC 121 samples the analog input signal in response to the edge of the second non-inverted delayed clock signal. The delay circuitry 142, 145 generates a third pair of delayed clock signals comprising a third non-inverted delayed clock signal (CLK3) and a third inverted delayed clock signal by delaying the edges of both signals of the second pair of delayed clock signals by a third delay duration. The ADC 124 samples the analog input signal in response to edges of the third non-inverted delayed clock signal.

[0045] In this example operation, ADC 115 samples the analog input signal in response to the rising edge of the clock signal. ADC 118 samples the analog input signal in response to the first non-inverted delayed clock signal, which occurs a first delay duration after ADC 115 samples the analog input signal. ADC 121 samples the analog input signal in response to the second non-inverted delayed clock signal, which occurs a second delay duration after ADC 118 samples the analog input signal. ADC 124 samples the analog input signal in response to the third non-inverted delayed clock signal, which occurs a third delay duration after ADC 121 samples the analog input signal. Advantageously, the delay durations of delay circuitry 130, 133, 136, 139, 142, 145 sequence the sampling of the analog input signal.

[0046] Advantageously, delay circuitry 130, 133, 136, 139, 142, 145 may have a delay duration that allows receiver circuitry 106 to accurately receive analog input signals having speeds greater than the conversion speeds of ADCs 115, 118, 121, 124. For example, when the analog input signal has a speed corresponding to thirty-two gigasamples per second (Gsps) and each of ADCs 115, 118, 121, 124 has a sampling speed of eight Gsps, delay circuitry 130, 133, 136, 139, 142, 145 may be configured to have a delay duration of thirty-one and a quarter picoseconds (pS) for sequencing ADCs 115, 118, 121, 124 to sample the analog input signal. In this example, each of the ADCs 115, 118, 121, 124 samples each bit of the relatively high-speed analog input signal sequentially in response to the delay of the delay circuitry 130, 133, 136, 139, 142, 145. In another example, when the analog input signal has a speed corresponding to sixty-four gigasamples per second (Gsps) and the sampling speed of each of the ADCs 115, 118, 121, 124 is sixteen Gsps, the delay circuitry 130, 133, 136, 139, 142, 145 is configured to have a delay duration of fifteen and five-eighths picoseconds (pS) to sequence the ADCs 115, 118, 121, 124 sampling the analog input signal.

[0047] Waveguides, such as waveguides 148, 151, 154, 157, 160, 163, 166, 169, 172, 175, 178, and 181, are electrical traces configured to use the physical properties of the waveguide to control the propagation of a signal. In some examples, the electrical trace is considered a waveguide configured as a delay line, in response to the electrical trace having physical properties that reduce the propagation speed of the signal through the waveguide. In such examples, the length of the waveguide electrical trace determines the delay duration of the signal. In the examples described herein, the electrical trace acts as both a waveguide and a delay line, in response to being configured to delay a signal by a delay duration.

[0048] In example operation, the waveguides 148, 151, 154, 157, 160, 163, 166, 169, 172, 175, 178, 181 are configured to delay the signal for the delay duration. Figures 3 to 9BTo further describe, one or more of the waveguides 148, 151, 154, 157, 160, 163, 166, 169, 172, 175, 178, 181 are configured relative to one or more of the waveguides 148, 151, 154, 157, 160, 163, 166, 169, 172, 175, 178, 181 to modify the propagation speed of the signal. For example, the waveguides 148, 151, 154, 157 are configured to delay the signal by a first delay duration. Figure 1 In the example of , the waveguides 148, 151, 154, 157 are configured to have capacitance (C) and inductance (L). The propagation speed of the clock signal through the waveguides 148, 151, 154, 157 can be determined using the following equation (1). Therefore, the delay per length (l) of the waveguides 148, 151, 154, 157 can be determined using the following equation (2).

[0049]

[0050] In the examples described herein, the waveguides 148, 151, 154, 157 are constructed with respect to each other to have relatively high capacitance. Advantageously, increasing the capacitance or inductance of the waveguides 148, 151, 154, 157, 160, 163, 166, 169, 172, 175, 178, 181 increases the delay per length, thereby reducing the length of the waveguides 148, 151, 154, 157, 160, 163, 166, 169, 172, 175, 178, 181. Figures 3 to 9B Example embodiments of configuring the waveguides 148, 151, 154, 157, 160, 163, 166, 169, 172, 175, 178, 181 to increase capacitance and inductance are further described.

[0051] Figure 2 FIG is a block diagram of an example ADC 200. Figure 2 In the example of , ADC 200 includes timing circuitry 205, flash circuitry 210, digital-to-analog converter (DAC) 215, combining circuitry 220, amplifier 225, residual ADC 230, and error correction circuitry 235. Figure 2 In the example of , the timing circuitry 205 includes a first delay circuitry 240 and a second delay circuitry 245. Figure 2 In the example of , delay circuitry 240 includes a first waveguide 250 and a second waveguide 255 , and delay circuitry 245 includes a third waveguide 260 and a fourth waveguide 265 .

[0052] The timing circuit system 205 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first and second terminals of the timing circuit system 205 are coupled to the flash memory circuit system 210 and can be coupled to supply an analog input signal (ANALOG IN The third and fourth terminals of timing circuitry 205 are coupled to combinational circuitry 220.

[0053] Flash memory circuitry 210 has a first terminal, a second terminal, and a third terminal. The first and second terminals of flash memory circuitry 210 are coupled to timing circuitry 205 and may be coupled to external circuitry that supplies analog input signals. The third terminal of flash memory circuitry 210 is coupled to DAC 215 and error correction circuitry 235. In some examples, flash memory circuitry 210 has multiple terminals coupled to DAC 215 and error correction circuitry 235. Figure 2 In the example of FIG. 2 , the flash circuit system 210 is configured as an ADC. For example, the flash circuit system 210 is configured as a six-bit ADC.

[0054] DAC 215 has a first terminal and a second terminal. The first terminal of DAC 215 is coupled to flash memory circuitry 210 and error correction circuitry 235. The second terminal of DAC 215 is coupled to combining circuitry 220.

[0055] Combining circuit system 220 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first and second terminals of combining circuit system 220 are coupled to timing circuit system 205. The third terminal of combining circuit system 220 is coupled to DAC 215. The fourth terminal of combining circuit system 220 is coupled to amplifier 225. Figure 2 In the example of , the combination circuitry 220 is configured as subtraction circuitry that subtracts the voltage at the third terminal from the voltage difference between the first terminal and the second terminal.

[0056] Amplifier 225 has a first terminal and a second terminal. The first terminal of amplifier 225 is coupled to combining circuitry 220. The second terminal of amplifier 225 is coupled to residual ADC 230. Amplifier 225 has an in-band gain (G(s)). In some examples, amplifier 225 includes filter circuitry.

[0057] Residual ADC 230 has a first terminal and a second terminal. The first terminal of residual ADC 230 is coupled to amplifier 225. The second terminal of residual ADC 230 is coupled to error correction circuitry 235. In some examples, residual ADC has multiple terminals coupled to error correction circuitry 235.

[0058] Error correction circuitry 235 has a first terminal, a second terminal, and a third terminal. The first terminal of error correction circuitry 235 is coupled to residual ADC 230. The second terminal of error correction circuitry 235 is coupled to flash memory circuitry 210 and DAC 215. The third terminal of error correction circuitry 235 may be coupled to external circuitry, such as digital signal processing circuitry.

[0059] Delay circuitry 240 has a first terminal and a second terminal. The first terminal of delay circuitry 240 is coupled to flash memory circuitry 210 and may be coupled to external circuitry supplying an analog input signal. The second terminal of delay circuitry 240 is coupled to combinational circuitry 220.

[0060] Delay circuitry 245 has a first terminal and a second terminal. The first terminal of delay circuitry 245 is coupled to flash memory circuitry 210 and may be coupled to external circuitry supplying an analog input signal. The second terminal of delay circuitry 245 is coupled to combinational circuitry 220.

[0061] Waveguide 250 (e.g., also referred to as an electrical trace, delay line, etc.) has a first terminal and a second terminal. The first terminal of waveguide 250 is coupled to flash memory circuitry 210 and can be coupled to external circuitry that supplies an analog input signal. The second terminal of waveguide 250 is coupled to waveguide 255. Waveguide 255 has a first terminal and a second terminal. The first terminal of waveguide 255 is coupled to waveguide 250. The second terminal of waveguide 255 is coupled to combining circuitry 220.

[0062] Waveguide 260 has a first terminal and a second terminal. The first terminal of waveguide 260 is coupled to flash memory circuitry 210 and can be coupled to external circuitry that supplies an analog input signal. The second terminal of waveguide 260 is coupled to waveguide 265. Waveguide 265 has a first terminal and a second terminal. The first terminal of waveguide 265 is coupled to waveguide 260. The second terminal of waveguide 265 is coupled to combinational circuitry 220.

[0063] exist Figure 2 In the examples of FIG. 1 , waveguides 250, 255, 260, 265 are described as having terminals. Alternatively, the terminals of waveguides 250, 255, 260, 265 may be described as endpoints. In some examples, one or more terminals of waveguides 250, 255, 260, 265 are directly coupled. In other examples, one or more terminals of waveguides 250, 255, 260, 265 are coupled through one or more vias. In still other examples, one or more terminals of waveguides 250, 255, 260, 265 are coupled through a support. Alternatively, the terminals of waveguides 250, 255, 260, 265 may be coupled through alternative components.

[0064] In example operation, timing circuitry 205 and flash memory circuitry 210 receive analog input signals from external circuitry. Flash memory circuitry 210 samples the analog input signals and generates digital output values ​​representing the sampled values. DAC 215 receives the digital output values ​​from flash memory circuitry 210. DAC 215 converts the digital output values ​​into analog output values. DAC 215 supplies the analog output values ​​to combinational circuitry 220.

[0065] During such example operation, the delay circuitry 240, 245 generates a delayed analog input signal by delaying the analog input signal for a delay duration. The delay duration of the delay circuitry 240, 245 is approximately (and in one example, exactly) equal to the duration between the flash circuitry 210 sampling the analog input signal and the DAC 215 generating the analog output value. The delay circuitry 240, 245 supplies the delayed analog input signal to the combinational circuitry 220. Advantageously, the analog output value from the DAC 215 corresponds to the value of the delayed analog input signal from the delay circuitry 240, 245.

[0066] In this example operation, the combinational circuit system 220 determines a difference output value between the delayed analog input signal and the analog output value. Amplifier 225 receives the difference from the combinational circuit system 220. Amplifier 225 generates a residual by amplifying and filtering the difference output value. Advantageously, amplifier 225 rejects the DAC image from DAC 215 and performs anti-aliasing in response to the amplified and filtered difference output value.

[0067] Residual ADC 230 receives the residual from amplifier 225. Residual ADC 230 generates a digital residual value representing the analog value of the residual. Error correction circuitry 235 receives the digital output value from flash memory circuitry 210 and the digital residual value from residual ADC 230. Error correction circuitry 235 generates a digital output (DIGITAL OUTPUT) by adjusting the digital output value to account for the residual. OUT ). The digital output represents the value of the sampled analog input. Advantageously, the residual represents the difference between the analog value of the digital output value and the corresponding value of the analog input signal sampled by the flash memory circuitry 210.

[0068] In example operation, the waveguides 250, 255, 260, 265 are configured to delay the analog input signal by a delay duration. Figures 3 to 9BFurther describing, the waveguides 250, 255, 260, 265 are configured to reduce the propagation speed of the signal relative to the waveguides 250, 255, 260, 265. For example, the waveguides 250, 255, 260, 265 are configured to delay the analog input signal by the time it takes the flash circuitry 210 and the DAC 215 to generate an analog output value. Figure 2 In the example of FIG. 5 , the waveguides 250, 255, 260, 265 are configured to have capacitance (C) and inductance (L). The propagation velocity of the analog input signal through the waveguides 250, 255, 260, 265 can be determined using equation (1) above. Therefore, the delay per length (l) of the waveguides 250, 255, 260, 265 can be determined using equation (2) above. Advantageously, increasing the capacitance or inductance of the waveguides 250, 255, 260, 265 increases the delay per length, thereby reducing the size of the waveguides 250, 255, 260, 265. Example embodiments in which the waveguides 250, 255, 260, 265 are configured to have relatively high capacitance and inductance are further described in conjunction with FIG. 3 through FIG. 9B .

[0069] Figure 3 is a perspective view of an example timing circuit system 300, the example timing circuit system being Figure 1 and 2 An example of the timing circuit system 112, 205. Figure 3 In the example of , the timing circuit system 300 includes a first waveguide 305, a first through hole 310, a second waveguide 315, a third waveguide 320, a second through hole 325, and a fourth waveguide 330. In some examples, such as in Figure 4 、 5A In 5B, 5C, the timing circuitry 300 is enclosed by a non-conductive material (e.g., a dielectric). In such examples, the timing circuitry 300 may be part of an integrated circuit (IC), a printed circuit board (PCB), or the like. In some examples, the waveguides 305, 315, 320, 330 are fabricated (e.g., constructed) as a relatively thick metal layer compared to other electrical traces used to route signals. In some examples, the electrical traces of the waveguides 305, 315, 320, 330 have a thickness between two-tenths of a millimeter and two and three-tenths of a millimeter. Alternatively, the thickness of the electrical traces of the waveguides 305, 315, 320, 330 may be specifically implemented. For example, in relatively high-power systems, the electrical traces of the waveguides 305, 315, 320, 330 may need to be thicker than in relatively low-power systems.

[0070] Waveguide 305 is coupled to waveguide 315 through via 310. Figure 3 In the example of FIG. 3 , the waveguides 305 , 315 and the via 310 are configured as a delay circuit system, such as Figure 1 and 2The delay circuitry 130, 133, 136, 139, 142, 145, 240, 245 of the waveguides 305, 315 is coupled to the via 310 through a non-conductive region (e.g., a dielectric layer). Alternatively, the delay circuitry of the waveguides 305, 315 may be modified to be coupled through alternative components (such as pillars).

[0071] Waveguide 320 is coupled to waveguide 330 through via 325. Figure 3 In the example of FIG. 1 , waveguides 320, 330 and vias 325 are configured as delay circuitry, such as delay circuitry 130, 133, 136, 139, 142, 145, 240, 245. Vias 325 couple waveguides 320, 330 through a non-conductive region (e.g., a dielectric layer). Alternatively, the delay circuitry of waveguides 320, 330 may be modified to be coupled through alternative components (such as pillars).

[0072] exist Figure 3 In the example of FIG, waveguide 305 has an end point 335 and a surface 340, and waveguide 320 has an end point 345 and a surface 350. End points 335, 345 may be coupled to external circuitry, such as Figure 1 The clock circuit system 109 or Figure 1 ADCs 115, 118, 121, 124 of FIG. Surfaces 340, 350 define the surface areas of waveguides 305, 320. Surfaces 340, 350 are separated by a non-conductive region (e.g., a dielectric layer). Waveguides 305, 320 are positioned such that the surface areas of surfaces 340, 350 overlap. The capacitance of waveguides 305, 320 is approximately equal to the dielectric constant (ε) of the material of the non-conductive region multiplied by the surface area (A) of the overlap between surfaces 340, 350 divided by the distance (d) between waveguides 305, 320. The capacitance of waveguides 305, 320 can be determined using the following equation (3).

[0073]

[0074] Advantageously, positioning waveguides 305, 330 so that surfaces 340, 350 overlap and are separated by a non-conductive region, such as an insulating layer, increases the capacitance of timing circuitry 300. Advantageously, increasing the capacitance of waveguides 305, 330 increases the delay per length of waveguides 305, 330. Advantageously, increasing the delay per length of waveguides 305, 330 reduces the size of timing circuitry 300.

[0075] exist Figure 3In the example of FIG, waveguide 315 has an endpoint 355 and a surface 360, and waveguide 330 has an endpoint 365 and a surface 370. Endpoints 355, 365 can be coupled to external circuitry, such as clock circuitry 109 or ADC 118. Surfaces 360, 370 define the surface area of ​​waveguides 315, 330. Surfaces 360, 370 are separated by a non-conductive region (e.g., a dielectric layer). Waveguides 315, 330 are positioned so that the surface areas of surfaces 360, 370 overlap. Waveguides 315, 330 have a capacitance that can be determined using equation (3) above. Advantageously, the delay of waveguides 305, 315, 320, 330 can be modified by adjusting the distance between waveguides 305, 315, 320, 330, the material of the non-conductive region, and the surface area of ​​surfaces 340, 350, 360, 370.

[0076] although Figure 3 The example timing circuit system 300 is shown as having a particular shape and size, but the shape or size of one or more components of the timing circuit system 300 may be different. Figure 3 Vias 310, 325 are shown coupling waveguides 305, 315, 320, 330, but the waveguides 305, 315, 320, 330 may be coupled using any type of coupling component.

[0077] Figure 4 for Figure 3 A top view of the timing circuit system 300 is shown. Figure 4 The example timing circuit system 300 includes Figure 3 Waveguides 305, 315, 320, 330 and Figure 3 endpoints 335, 345, 355, 365. Figure 4 The timing circuit system 300 further includes an example package 400. The package 400 houses the timing circuit system 300 by enclosing the waveguides 305, 315, 320, 330 in a non-conductive material. In some examples, the package 400 represents an integrated circuit. In other examples, the package 400 represents a printed circuit board. Although Figure 4 The example timing circuit system 300 is shown as having a particular shape and size, but the shape or size of one or more components of the timing circuit system 300 may be different. Figure 4 Endpoints 335 , 345 , 355 , 365 are shown as enclosed by package 400 , but package 400 may be modified to expose endpoints 335 , 345 , 355 , 365 or include additional components to allow circuitry to be coupled to endpoints 335 , 345 , 355 , 365 , such as vias, pillars, etc.

[0078] Figure 5A To follow Figure 4 The 5A-5A line is intercepted Figure 3and 4 The timing circuit system 300 and Figure 4 4. A cross-sectional view of package 400 is shown. Figure 5B To follow Figure 4 The 5B-5B line is intercepted Figure 3 and 4 The timing circuit system 300 and Figure 4 4. A cross-sectional view of package 400 is shown. Figure 5C To follow Figure 4 The 5C-5C line is intercepted Figure 3 and 4 The timing circuit system 300 and Figure 4 4. A cross-sectional view of package 400 is shown.

[0079] exist Figure 5A 、 5B In the example of 5C, the package 400 includes the timing circuit system 300, and the timing circuit system further includes Figure 3 and 4 Waveguides 305, 315, 320, 330 and Figure 3 through holes 310, 325. Figure 5A 、 5B Package 400 of 5C further includes a first example layer 520, a second example layer 540, a third example layer 560, a first example current path 570, and a second example current path 580. In some examples, package 400 is designed and manufactured by constructing each of layers 520, 540, 560. In such examples, package 400 can include additional components in each of layers 520, 540, 560 and additional layers surrounding layers 520, 540, 560. Figure 5A 、 5B Layer 520 of 5C contains waveguides 305 , 330 . Figure 5A 、 5B Layer 540 of 5C contains vias 310 , 325 . Figure 5A 、 5B and 5C, layer 560, contains waveguides 315, 320. Figure 5A 、 5B 5C , layers 520 , 540 , 560 further include a non-conductive material surrounding the conductive portions of the waveguides 305 , 315 , 320 , 330 and the vias 310 , 325 .

[0080] Current paths 570, 580 illustrate example propagation paths of signals through timing circuitry 300. Figure 5A 、 5BIn the examples of 5C and 5D, the current paths 570 and 580 have currents propagating in the same direction. In such examples, the signals propagating in the same direction generate magnetic fields that superimpose each other. In some examples, the positive and negative signals of the differential signal pair are supplied to Figure 3 and 4 Different ones of the endpoints 335, 345, 355, 365 can propagate current in the same direction. For example, Figure 1 The clock circuitry 109 supplies a non-inverted clock signal to terminal 335 and an inverted clock signal to terminal 365. In this example, the inverting nature of the differential clock signal pair causes the currents of the clock signals to propagate in the same direction.

[0081] Advantageously, supplying signals with currents traveling in the same direction increases the magnetic field of the delay circuitry, thereby increasing the inductance of the waveguides 305, 315, 320, 330. Advantageously, increasing the inductance of the waveguides 305, 315, 320, 330 increases the delay per length of the waveguides 305, 315, 320, 330. Advantageously, increasing the delay per length of the waveguides 305, 315, 320, 330 reduces the size of the timing circuitry 300.

[0082] Figure 6 is a top view of an example timing circuit system 600, the example timing circuit system being Figure 1 and 2 An example of the timing circuit system 112, 205. Figure 6 In the example of , the timing circuit system 600 includes a package 605, a first waveguide 610, a second waveguide 615, a third waveguide 620, a fourth waveguide 625, a fifth waveguide 630, a sixth waveguide 635, a seventh waveguide 640, an eighth waveguide 645, a ninth waveguide 650, and a tenth waveguide 655.

[0083] Waveguides 610, 615, 620, 625, 630 are coupled through multiple through holes (in Figure 7B and 7C ). Figure 6 In the example of FIG. 5 , waveguides 610 , 615 , 620 , 625 , 630 are configured as delay circuitry, such as Figure 1 and 2 The delay circuit system 130, 133, 136, 139, 142, 145, 240, 245. As shown below Figure 7B and 7C Further depicted, vias pass through non-conductive regions (e.g., dielectric layers) to couple waveguides 610, 615, 620, 625, 630. Alternatively, the delay circuitry of waveguides 610, 615, 620, 625, 630 may be modified to couple through alternative components, such as pillars.

[0084] exist Figure 6 In the example of FIG, waveguide 610 has an end point 660, and waveguide 630 has an end point 665. End points 660, 665 may be coupled to external circuitry, such as Figure 1 The clock circuit system 109 or Figure 1 ADCs 115, 118, 121, 124 of FIG. Waveguides 610, 615, 620, 625, 630 delay the signal by a delay duration. For example, when clock circuitry 109 supplies a non-inverted clock signal to terminal 660, waveguides 610, 615, 620, 625, 630 delay the rising and falling edges of the non-inverted clock signal to generate a delayed non-inverted clock signal at terminal 665.

[0085] Waveguides 635, 640, 645, 650, 655 are coupled through multiple through holes (in Figure 7B and 7C ). Figure 6 In the example of , waveguides 635, 640, 645, 650, 655 are configured as delay circuit systems, such as delay circuit systems 130, 133, 136, 139, 142, 145, 240, 245. As described below in conjunction with Figure 7B and 7C Further depicted, vias couple waveguides 635, 640, 645, 650, 655 through non-conductive regions (e.g., dielectric layers). Alternatively, the delay circuitry of waveguides 635, 640, 645, 650, 655 may be modified to couple through alternative components, such as pillars.

[0086] exist Figure 6 In the example of FIG, waveguide 635 has an end point 670 and waveguide 655 has an end point 675. End points 670, 675 may be coupled to external circuitry, such as Figure 1 The clock circuit system 109 or Figure 1 ADCs 115, 118, 121, 124 of FIG. Waveguides 635, 640, 645, 650, 655 delay the signal for a delay duration. For example, when clock circuitry 109 supplies an inverted clock signal to terminal 670, waveguides 635, 640, 645, 650, 655 delay the rising and falling edges of the inverted clock signal to produce a delayed inverted clock signal at terminal 675. In this example, when clock circuitry 109 supplies a non-inverted clock signal to terminal 660, the current of the clock signal propagates in the same direction.

[0087] Advantageously, supplying signals having currents traveling in the same direction increases the magnetic field of timing circuitry 600, thereby increasing the inductance of waveguides 610, 615, 620, 625, 630, 635, 640, 645, 650, 655. Advantageously, increasing the inductance of waveguides 610, 615, 620, 625, 630, 635, 640, 645, 650, 655 increases the delay per length of waveguides 610, 615, 620, 625, 630, 635, 640, 645, 650, 655. Advantageously, increasing the delay per length of waveguides 610, 615, 620, 625, 630, 635, 640, 645, 650, 655 reduces the size of timing circuitry 600.

[0088] exist Figure 6 In the example of FIG, waveguides 615 and 640 are configured to have overlapping surfaces, waveguides 620 and 645 are configured to have overlapping surfaces, waveguides 625 and 650 are configured to have overlapping surfaces, and waveguides 630 and 655 are configured to have overlapping surfaces. In addition, non-conductive regions separate the overlapping surfaces of waveguides 610, 615, 620, 625, 630, 635, 640, 645, 650, and 655. The capacitance of waveguides 610, 615, 620, 625, 630, 635, 640, 645, 650, and 655 can be determined using the combined surface area of ​​the overlapping surfaces of waveguides 610, 615, 620, 625, 630, 635, 640, 645, 650, and 655 using equation (3) above. Advantageously, looping timing circuitry 600 to increase the overlapping surface area of ​​waveguides 610 , 615 , 620 , 625 , 630 , 635 , 640 , 645 , 650 , 655 increases the capacitance of timing circuitry 600 without substantially increasing the footprint of timing circuitry 600 in package 605 .

[0089] Figure 7A To follow Figure 6 The 7A-7A line is intercepted Figure 6 6. A cross-sectional view of the timing circuit system 600 is shown. Figure 7B To follow Figure 6 The 7B-7B line is intercepted Figure 6 6. A cross-sectional view of the timing circuit system 600 is shown. Figure 7C To follow Figure 6 The 7C-7C line is intercepted Figure 6 6. A cross-sectional view of the timing circuit system 600 is shown. Figure 7D To follow Figure 6 The 7D-7D line intercepts Figure 6 6. A cross-sectional view of the timing circuit system 600 is shown. Figure 7E To follow Figure 6The 7E-7E line is intercepted Figure 6 6. A cross-sectional view of the timing circuit system 600 is shown. Figure 7F To follow Figure 6 The 7F-7F line is intercepted Figure 6 6. A cross-sectional view of the timing circuit system 600 is shown.

[0090] exist Figure 7A 、 7B , 7C, 7D, 7E and 7F, the timing circuit system 600 includes Figure 6 Package 605 and Figure 6 waveguides 610, 615, 620, 625, 630, 635, 640, 645, 650, 655. Figure 7A 、 7B , 7C, 7D, 7E and 7F include a first instance layer 705, a second instance layer 710, a third instance layer 715, a fourth instance layer 720, a fifth instance layer 725, a sixth instance layer 730 and a seventh instance layer 735. Figure 7A 、 7B , 7C, 7D, 7E, and 7F further include a first example via 740, a second example via 745, a third example via 750, a fourth example via 755, a fifth example via 760, a sixth example via 765, a seventh example via 770, and an eighth example via 775. Figure 7A 、 7B , 7C, 7D, 7E, and 7F, a first example current path 780 and a second example current path 785 are shown. Although the example timing circuitry 600 of 7A, 7B, 7C, 7D, 7E, and 7F are shown as having particular shapes and sizes, the shape or size of one or more components of timing circuitry 600 may be different.

[0091] In some examples, package 605 is designed and manufactured by constructing each of layers 705, 710, 715, 720, 725, 730, 735. In such examples, package 605 can include additional components in each of layers 705, 710, 715, 720, 725, 730, 735 and additional layers surrounding layers 705, 710, 715, 720, 725, 730, 735. Figure 7A and 7B Layer 705 contains waveguide 610. Figure 7A and 7B Layer 710 includes a through hole 740 . Figure 7A 、 7B Layer 715 of 7C, 7D, 7E and 7F contains waveguides 615, 625, 645, 655. Figure 7A 、 7BLayer 720 of 7C, 7D, 7E and 7F includes through-holes 745, 750, 755, 765, 770, 775. Figure 7A 、 7B Layer 725 of 7C, 7D, 7E and 7F contains waveguides 620, 630, 640, 650. Figure 7A and 7B Layer 730 includes a through hole 760 . Figure 7A and 7B The layer 735 contains the waveguide 635. Figure 7A 、 7B , 7C, 7D, 7E and 7F, layers 705, 710, 715, 720, 725, 730, 735 further include non-conductive material surrounding the conductive portions of the waveguides 610, 615, 620, 625, 630, 635, 640, 645, 650, 655 and the through-holes 740, 745, 750, 755, 760, 765, 770, 775.

[0092] Waveguide 610 is coupled to waveguide 615 via via 740. Waveguide 615 is coupled to waveguide 620 via via 745. Waveguide 620 is coupled to waveguide 625 via via 750. Waveguide 625 is coupled to waveguide 630 via via 755. Figure 7A 、 7B , 7C, 7D, 7E and 7F, the waveguides 610, 615, 620, 625, 630 and the through holes 740, 745, 750, 755 are constructed as a delay circuit system, such as Figure 1 and 2 The delay circuitry 130, 133, 136, 139, 142, 145, 240, 245 of the waveguides 610, 615, 620, 625, 630 is coupled through a non-conductive region (e.g., a dielectric layer). Alternatively, the delay circuitry of the waveguides 610, 615, 620, 625, 630 may be modified to be coupled through alternative components (such as pillars).

[0093] Waveguide 635 is coupled to waveguide 640 via via 760. Waveguide 640 is coupled to waveguide 645 via via 765. Waveguide 645 is coupled to waveguide 650 via via 770. Waveguide 650 is coupled to waveguide 655 via via 775. Figure 7A 、 7B, 7C, 7D, 7E, and 7F, waveguides 635, 640, 645, 650, 655 and vias 760, 765, 770, 775 are configured as delay circuitry, such as delay circuitry 130, 133, 136, 139, 142, 145, 240, 245. Vias 760, 765, 770, 775 couple waveguides 635, 640, 645, 650, 655 through a non-conductive region (e.g., a dielectric layer). Alternatively, the delay circuitry of waveguides 635, 640, 645, 650, 655 may be modified to be coupled through alternative components, such as pillars.

[0094] Current paths 780, 785 illustrate example propagation paths of signals through timing circuitry 600. Figure 7A 、 7B In the examples of 7C, 7D, 7E and 7F, the current paths 780 and 785 have currents propagating in the same direction. In such examples, the signals propagating in the same direction generate magnetic fields that superimpose each other. In some examples, the positive and negative signals of the differential signal pair are supplied to Figure 6 Different ones of the endpoints 660, 665, 670, 675 can propagate current in the same direction. For example, Figure 1 Clock circuitry 109 supplies a non-inverted clock signal to terminal 660 and an inverted clock signal to terminal 675. In this example, the inverted nature of the differential clock signal pair causes the currents of the clock signals to propagate in the same direction. Furthermore, winding waveguides 610, 615, 620, 625, 630, 635, 640, 645, 650, 655 so that the currents through waveguides 615, 625, 640, 650 propagate in the same direction further increases inductance.

[0095] Advantageously, supplying signals having currents traveling in the same direction increases the magnetic field of the delay circuitry, thereby increasing the inductance of the waveguides 610, 615, 620, 625, 630, 635, 640, 645, 650, 655. Advantageously, increasing the inductance of the waveguides 610, 615, 620, 625, 630, 635, 640, 645, 650, 655 increases the delay per length of the waveguides 610, 615, 620, 625, 630, 635, 640, 645, 650, 655. Advantageously, increasing the delay per length of the waveguides 610, 615, 620, 625, 630, 635, 640, 645, 650, 655 reduces the size of the timing circuitry 600.

[0096] Figure 8 is a top view of an example timing circuit system 800, the example timing circuit system being Figure 1 and2 An example of the timing circuit system 112, 205. Figure 8 In the example of FIG, the timing circuit system 800 includes a package 805, a first waveguide 810, a second waveguide 815, a third waveguide 820, and a fourth waveguide 825. Figure 8 The example timing circuit system 800 is shown as having a particular shape and size, but the shape or size of one or more components of the timing circuit system 800 may be different.

[0097] Waveguides 810, 815 are formed by Figure 3 、 4 The through hole is coupled to the through hole 310 of 5B. This through hole passes through a non-conductive region (e.g., a dielectric layer) to couple the waveguides 810 and 815. Figure 8 In the example of , waveguides 810, 815 are configured as delay circuitry, such as Figure 1 and 2 The delay circuitry of the waveguides 810, 815 may be modified to be coupled through alternative components, such as pillars.

[0098] Waveguides 820 and 825 are similar to Figure 3 、 4 The through hole is coupled to the through hole 325 of 5B. This through hole passes through a non-conductive region (e.g., a dielectric layer) to couple the waveguides 820 and 825. Figure 8 In the example of FIG. 8 , waveguides 820 , 825 are configured as delay circuitry, such as delay circuitry 130 , 133 , 136 , 139 , 142 , 145 , 240 , 245 . Alternatively, the delay circuitry of waveguides 820 , 825 may be modified to be coupled through alternative components, such as pillars.

[0099] exist Figure 8 In the example of FIG, waveguide 810 has an end point 830 and a fin 835, and waveguide 815 has an end point 840 and a fin 845. End points 830, 840 may be coupled to external circuitry, such as Figure 1 The clock circuit system 109 or Figure 1 ADCs 115, 118, 121, 124 of the embodiment of the present invention. Waveguides 810, 815 delay the signal by a delay duration. For example, when clock circuitry 109 supplies a non-inverted clock signal to terminal 830, waveguides 810, 815 delay the rising and falling edges of the non-inverted clock signal to generate a delayed non-inverted clock signal at terminal 840.

[0100] exist Figure 8In the example of FIG, waveguide 820 has an endpoint 850 and a fin 855, and waveguide 825 has an endpoint 860 and a fin 865. Endpoints 850 and 860 can be coupled to external circuitry, such as clock circuitry 109 or ADCs 115, 118, 121, and 124. Waveguides 820 and 825 delay a signal by a delay duration. For example, when clock circuitry 109 supplies an inverted clock signal to endpoint 860, waveguides 820 and 825 delay the rising and falling edges of the inverted clock signal to produce a delayed inverted clock signal at endpoint 850. In this example, when clock circuitry 109 supplies the inverted clock signal to endpoint 860, the currents of the clock signals propagate in the same direction. Advantageously, supplying signals with currents propagating in the same direction increases the magnetic field of timing circuitry 800, thereby increasing the inductance of waveguides 810, 815, 820, and 825. Advantageously, increasing the inductance of the waveguides 810, 815, 820, 825 increases the delay per length of the waveguides 810, 815, 820, 825. Advantageously, increasing the delay per length of the waveguides 810, 815, 820, 825 reduces the size of the timing circuitry 800.

[0101] exist Figure 8 In the example of FIG. 8 , waveguides 810 and 820 are configured to have overlapping surfaces, including surfaces of fins 835 and 855, and waveguides 815 and 825 are configured to have overlapping surfaces, including surfaces of fins 845 and 865. Furthermore, a non-conductive region separates the overlapping surfaces of waveguides 810 and 820 from the overlapping surfaces of waveguides 815 and 825. The capacitance of waveguides 810, 815, 820, and 825 can be determined using the combined surface area of ​​the overlapping surfaces of waveguides 810, 815, 820, and 825 using equation (3) above. Advantageously, the inclusion of fins 835, 845, 855, and 865 increases the overlapping surface area of ​​waveguides 810, 815, 820, and 825, thereby increasing the capacitance of timing circuitry 800, without substantially increasing the footprint of timing circuitry 800 in package 805.

[0102] Figure 9A To follow Figure 8 The 9A-9A line is intercepted Figure 8 A cross-sectional view of the timing circuit system 800 and package. Figure 9B To follow Figure 8 The 9B-9B line is intercepted Figure 8 A cross-sectional view of the timing circuit system 800 is shown. Figure 9A and 9B In the example of the timing circuit system 800, Figure 8 Waveguides 810, 815, 820, 825 and Figure 8 Fins 835, 845, 855, 865. Figure 9A and 9B In the example, Figure 8 805 includes a first example layer 910, a second example layer 920, a third example layer 930, a first example current path 940, and a second example current path 950. In some examples, package 805 is designed and manufactured by constructing each of layers 910, 920, 930. In such examples, package 805 can include additional components in each of layers 910, 920, 930 and additional layers surrounding layers 910, 920, 930.

[0103] Figure 9A and 9B Layer 910 contains waveguides 810 , 825 and fins 835 , 865 . Figure 9A and 9B Layer 920 contains through-holes for coupling waveguides 810 , 815 , 820 , 825 . Figure 9A and 9B The layer 930 includes the waveguides 820, 815 and the fins 845, 855. Figure 9A and 9B In the example of , the layers 910 , 920 , 930 further include a dielectric material surrounding the waveguides 810 , 815 , 820 , 825 and the fins 835 , 845 , 855 , 865 .

[0104] exist Figure 9B In the example of , the fins 835, 845 of the waveguides 810, 815 are along the current path 940. Figure 9B In the example of FIG, the fins 855, 865 of the waveguides 820, 825 are along the current path 950. In example operation, a signal propagates through the fins 835, 845, 855, 865. In such example operation, the fins 835, 845, 855, 865 may be spaced apart to prevent harmonic reflections from causing reflections, thereby modifying the current of the current paths 940, 950. Advantageously, adding space to the fins 835, 845, 855, 865 reduces the likelihood of harmonic reflections in the signal propagating through the timing circuit system 800. In addition, similar to Figure 5A 、 5B , 7A, 7B, 7C, 7D, 7E and 7F, the current propagating in the shared direction increases the inductance of the waveguides 810 , 815 , 820 , 825 .

[0105] "Including" and "comprising" (and all forms and tenses thereof) are used herein as open terms. Thus, whenever a claim uses any form of "includes" or "comprising" (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or in any type of claim recitation, additional elements, terms, etc. may be present without exceeding the scope of the corresponding claim or recitation. As used herein, when the phrase "at least" is used as a transition term, such as in the preamble of a claim, it is open in the same manner that the terms "includes" and "comprising" are open. The term "and / or" when used in a form such as A, B, and / or C refers to any combination or subset of A, B, C, such as (1) only A, (2) only B, (3) only C, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. As used herein in the context of describing structures, components, items, objects, and things, the phrase "at least one of A and B" refers to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and things, the phrase "at least one of A or B" refers to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the implementation or performance of a process, instruction, action, activity, etc., the phrase "at least one of A and B" refers to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the execution or performance of a process, instruction, action, activity, etc., the phrase "at least one of A or B" refers to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0106] As used herein, singular references (e.g., "a," "an," "first," "second," etc.) do not exclude plural reference. As used herein, the term "a" or "an" object refers to one or more of the objects described. The terms "a" (or "an"), "one or more," and "at least one" are used interchangeably herein. Furthermore, although listed separately, multiple components, elements, or actions may be implemented by, for example, the same entity or object. Furthermore, although individual features may be included in different examples or claims, these features may be combined, and inclusion in different examples or claims does not imply that a combination of features is not feasible or advantageous.

[0107] As used herein, unless otherwise stated, the term "above" describes the relationship of two parts relative to ground. A first part is above a second part if at least one portion of the second part is between the ground and the first part. Similarly, as used herein, a first part is "below" a second part when the first part is closer to the ground than the second part. As mentioned above, a first part can be above or below a second part, with one or more of the following: with other parts in between, without other parts in between, the first and second parts in contact, or the first and second parts not in direct contact with each other.

[0108] Notwithstanding the foregoing, when referring to a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, or an integrated circuit (IC) package containing a semiconductor die during fabrication or manufacturing, the term "above" is used not with reference to ground, but rather with reference to the underlying substrate on which the associated component is fabricated, assembled, mounted, supported, or otherwise provided. Thus, as used herein, and unless the context states or implies otherwise, a first component (e.g., a transistor or other semiconductor device) within a semiconductor die is above a second component within the semiconductor die when the first component is located further from the substrate (e.g., a semiconductor wafer) on which both components are fabricated or otherwise provided during fabrication / manufacturing than the second component. Similarly, a first component (e.g., a semiconductor die) within an IC package is above a second component within the IC package during fabrication when the first component is located further from a printed circuit board (PCB) to which the IC package will be mounted or attached, unless the context states or implies otherwise. Semiconductor devices are often used in an orientation different from their orientation during fabrication. Therefore, when reference is made during use to a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, or an integrated circuit (IC) package containing a semiconductor die, the definition of "above" in the preceding paragraph (i.e., the term "above" describes the relationship of two parts relative to ground) will likely be governed based on the context of use.

[0109] In some examples, one or more types of semiconductor manufacturing methods may be implemented to design, implement, and manufacture the timing circuitry described herein. In some examples, an electronic design automation (EDA) tool routes electrical traces to be constructed as waveguides that delay signals. For example, an EDA tool modifies Figure 3 、 4 , 5A, and 5B (e.g., modifying the length, modifying the width, etc.) to form application-specific timing circuitry. In such examples, the manufacturer uses etching methods to form layers to prepare the timing circuitry. In other examples, the manufacturer uses metallization to form layers to prepare the timing circuitry. Alternatively, the manufacturer may utilize any method of semiconductor manufacturing to prepare the timing circuitry described herein.

[0110] As used in this patent, stating that any part (e.g., a layer, film, region, area, or plate) is in any manner located on another part (e.g., located on, positioned on, disposed on, or formed on, etc.) indicates that the referenced part is in contact with the other part, or that the referenced part is above the other part with one or more intermediate parts positioned therebetween.

[0111] As used herein, unless otherwise specified, connection references (e.g., attached, coupled, connected, and joined) may include intermediate members between the elements referenced by the connection reference or relative movement between those elements. Thus, connection references do not necessarily infer that two elements are directly connected or in fixed relation to each other. As used herein, stating that any part is "in contact with" another part is defined to mean that there are no intermediate parts between the two parts.

[0112] Unless otherwise specifically stated, descriptors such as "first," "second," and "third" are used herein without imposing or otherwise indicating a priority in a list, a physical order, an arrangement, or ordering in any manner, but are merely used as labels and arbitrary names to distinguish elements to facilitate understanding of the described examples. In some examples, the descriptor "first" may be used to refer to an element in a specific embodiment, while the same element may be referred to by a different descriptor, such as "second" or "third," in the claims. In such cases, such descriptors are used only to clearly identify those elements within the context of the discussion (e.g., within the claims), where the elements may, for example, otherwise share the same name.

[0113] As used herein, "substantially" and "approximately" modify the subject matter / values ​​thereof to recognize the potential for variations that occur in real-world applications. For example, "substantially" and "approximately" may modify dimensions that may not be exact due to manufacturing tolerances and / or other real-world imperfections. For example, unless otherwise specified herein, "substantially" and "approximately" may indicate that such dimensions may be within a tolerance range of + / - 10%.

[0114] As used herein, "substantially real time" means occurring in a near-instantaneous manner, recognizing that there may be delays in real-world computation time, transmission, etc. Therefore, unless otherwise specified, "substantially real time" means real time + 1 second.

[0115] As used herein, the phrase "communication" includes variations thereof encompassing direct communication and / or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or continuous communication, but also includes selective communication at periodic intervals, predetermined intervals, non-periodic intervals and / or one-time events.

[0116] As used herein, an integrated circuit / circuitry is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, a programmable circuitry, a semiconductor substrate coupling multiple circuit elements, a system-on-chip (SoC), etc.

[0117] In this description, the term "and / or" (when used in a form such as A, B and / or C) refers to any combination or subset of A, B, C, such as: (a) only A; (b) only B; (c) only C; (d) A and B; (e) A and C; (f) B and C; and (g) A and B and C. In addition, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") refers to embodiments that include any of the following: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.

[0118] In this description, the term "coupled" may encompass any connection, communication, or signal path that enables a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B via a direct connection; or (b) in a second example, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not modify the functional relationship between devices A and B such that device B is controlled by device A via the control signal generated by device A.

[0119] Numerical identifiers such as "first," "second," "third," etc., are only used to distinguish elements of substantially the same type in terms of structure and / or function. These identifiers as used in the detailed description are not necessarily consistent with the identifiers used in the claims.

[0120] A device that is "configured to" perform a task or function may be configured (e.g., programmed or hardwired) to perform the function when manufactured by the manufacturer, or may be configured (or reconfigured) by a user after manufacture to perform the function or other additional or alternative functions. The configuration may be performed by firmware or software programming of the device, by the construction or layout of hardware components and the interconnection of the device, or a combination thereof.

[0121] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to an interconnection or termination between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components.

[0122] In the description and claims, a "circuitry" described may include one or more circuits. A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, or inductors), and / or one or more sources (such as voltage sources or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements or sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user or a third party.

[0123] The circuits described herein can be reconfigured to include replacement components to provide functionality that is at least partially similar to functionality available before component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series or in parallel to provide the impedance represented by the resistor shown. For example, a resistor or capacitor shown and described as a single component herein may alternatively be a plurality of resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described as a single component herein may actually be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor. Although some elements of the described examples are included in the integrated circuit and other elements are outside the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features shown as being outside the integrated circuit may be included in the integrated circuit, or some features shown as being inside the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" refers to one or more circuits that are: (i) incorporated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0124] The use of the phrase "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, universal ground, or any other form of ground connection that is applicable or suitable for the teachings of this description. Unless otherwise stated, the words "about," "substantially," or "substantially" preceding a value mean + / - 10% of the value, or, if the value is zero, the first reasonable range of values ​​around zero.

[0125] Modifications are possible in the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. An integrated circuit comprising: a first metal layer comprising a first delay line having a surface region; a second metal layer comprising a second delay line having a surface area overlapping the surface area of ​​the first delay line; and An insulating layer is located between the first metal layer and the second metal layer.

2. The integrated circuit of claim 1 , wherein: The first metal layer further comprises a third delay line having a surface region; and The second metal layer further includes a fourth delay line having a surface area overlapping the surface area of ​​the third delay line.

3. The integrated circuit of claim 2 , wherein the first delay line further comprises an endpoint, the second delay line further comprises an endpoint, the third delay line further comprises an endpoint, the fourth delay line further comprises an endpoint, and wherein the endpoint of the first delay line is coupled to the endpoint of the third delay line, and the endpoint of the second delay line is coupled to the endpoint of the fourth delay line.

4. The integrated circuit of claim 2 , further comprising: a first via coupled to the first delay line and the third delay line through the insulating layer; and A second via passes through the insulating layer and is coupled to the second delay line and the fourth delay line.

5. The integrated circuit of claim 2, wherein: The first delay line further comprises a fin; the second delay line further comprising fins overlapping the fins of the first delay line; The third delay line further includes fins that do not overlap with the fins of the first delay line and the fins of the second delay line; and The fourth delay line further includes fins that overlap the fins of the third delay line.

6. The integrated circuit according to claim 1 , wherein the insulating layer is a first insulating layer, and the integrated circuit further comprises: a third metal layer further comprising a third delay line having a surface region; and a fourth metal layer further comprising a fourth delay line having a surface area overlapping the surface area of ​​the third delay line; and A second insulating layer is located between the third metal layer and the fourth metal layer.

7. The integrated circuit of claim 6, further comprising: a first via passing through the first insulating layer and the second metal layer and coupled to the first delay line and the third delay line; and A second via passes through the third metal layer and the second insulating layer and is coupled to the second delay line and the fourth delay line.

8. A device comprising: a first layer comprising a first waveguide having a surface, the first waveguide being configured as a first delay circuitry; a second layer comprising a second waveguide having a surface overlapping the surface of the first waveguide, the second waveguide being configured as a second delay circuitry; and The third layer is located between the first layer and the second layer.

9. The apparatus of claim 8, further comprising: The first delay circuitry further has a third waveguide having a surface; and The second delay circuit system further includes a fourth waveguide having a surface overlapping the surface of the third waveguide.

10. The apparatus of claim 9, wherein the first waveguide further has a terminal, the second waveguide further has a terminal, the third waveguide further has a terminal, the fourth waveguide further has a terminal, and wherein the terminal of the first waveguide is coupled to the terminal of the third waveguide, and the terminal of the second waveguide is coupled to the terminal of the fourth waveguide.

11. The apparatus of claim 9, wherein the first layer further comprises the fourth waveguide, the second layer further comprises the third waveguide, and the apparatus further comprises: a first through-hole coupled to the first waveguide and the third waveguide; and A second through-hole is coupled to the second waveguide and the fourth waveguide.

12. The apparatus of claim 9, further comprising: The first waveguide further has fins; the second waveguide further having fins overlapping the fins of the first waveguide; The third waveguide further has fins that do not overlap with the fins of the first waveguide and the fins of the second waveguide; and The fourth waveguide further has fins that overlap with the fins of the third waveguide.

13. The apparatus of claim 9, further comprising: The first delay circuitry further has a fifth waveguide having a surface; and The second delay circuit system further includes a sixth waveguide having a surface overlapping the surface of the fifth waveguide.

14. The apparatus of claim 13, further comprising: The first delay circuit system further comprises: a first through-hole coupled to the first waveguide and the third waveguide; and a second through-hole coupled to the third waveguide and the fifth waveguide; and The second delay circuit system further has: a third through-hole coupled to the second waveguide and the fourth waveguide; and a fourth through-hole coupled to the fourth waveguide and the sixth waveguide.

15. A device comprising: a first layer comprising a first electrical trace having a surface area; and a second layer comprising a second electrical trace having a surface area overlapping the surface area of ​​the first electrical trace; a third layer coupled between the first layer and the second layer; a first analog-to-digital converter ADC coupled to the first electrical trace and the second electrical trace; and A second ADC is coupled to the first ADC through the first electrical trace and the second electrical trace.

16. The apparatus of claim 15, further comprising: The first layer further comprises a third electrical trace having a surface area; and The second layer further includes a fourth electrical trace having a surface area overlapping the surface area of ​​the third electrical trace.

17. The apparatus of claim 16, wherein the first electrical trace further has a terminal, the second electrical trace further has a terminal, the third electrical trace further has a terminal, the fourth electrical trace further has a terminal, the terminal of the first electrical trace is coupled to the terminal of the third electrical trace, and the terminal of the second electrical trace is coupled to the terminal of the fourth electrical trace. 18 . The apparatus of claim 17 , wherein the first and third electrical traces are configured to form a first plate, the second and fourth electrical traces are configured to form a second plate, the first and second plates having overlapping surfaces.

19. The apparatus of claim 16, further comprising: a first via configured to couple the first electrical trace to the third electrical trace through the third layer; and A second via is configured to couple the second electrical trace and the fourth electrical trace through the third layer.

20. The apparatus of claim 16, further comprising: The first electrical trace further has a fin; the second electrical trace further having a fin that overlaps the fin of the first electrical trace; The third electrical trace further has a fin that does not overlap with the fin of the first electrical trace and the fin of the second electrical trace; and The fourth electrical trace further has a fin that overlaps the fin of the third electrical trace, the fin being configured to increase a surface area between the electrical traces of the first layer and the electrical traces of the second layer.

Images