Chip thermal resistance and over-temperature protection temperature test system, method, device and medium

Abstract

The invention relates to the technical field of chip testing, in particular to a chip thermal resistance and over-temperature protection temperature testing system, method and device and a medium. The electronic load provides a load for the chip to be tested; the controllable constant-temperature box provides the working environment temperature of the to-be-tested chip; the computing device is used for acquiring the chip power consumption of the chip to be tested at the preset environment temperature at the moment before the over-temperature protection occurs after the controllable constant-temperature box is at the preset environment temperature and the electronic load is gradually increased from 0 until the over-temperature protection occurs on the chip to be tested; and after the data acquisition module acquires the corresponding chip power consumption under the n preset environment temperatures, the chip thermal resistance and the final over-temperature protection temperature are calculated based on the n preset environment temperatures and the corresponding n chip power consumption. The technical scheme is high in test precision, simple, stable and reliable in test circuit and low in test cost, and is mainly used for testing chip thermal resistance and over-temperature protection temperature.

Description

Technical Field

[0001] The present disclosure relates to the field of chip testing technology, and in particular to a chip thermal resistance and over-temperature protection temperature testing system, method, device and medium. Background Art

[0002] Temperature is a key factor affecting chip performance. In actual chip applications, the internal temperature of the chip is affected by parameters such as its power consumption, ambient temperature, and chip thermal resistance. Chip thermal resistance is a key parameter in characterizing chip thermal performance. Overtemperature protection is designed to ensure safe operation of the chip under extreme temperatures. Chips are generally designed with internal temperature protection circuits. When the internal chip temperature exceeds the overtemperature protection temperature, the temperature protection circuit automatically activates overtemperature protection. Therefore, chip thermal resistance and overtemperature protection temperature are two important test indicators for chip testing.

[0003] The chip thermal resistance is generally estimated by the chip packaging company based on the package type, material, volume, and other aspects of the simulation, which deviates greatly from the actual value. Currently, a more accurate thermal resistance test method is to measure it using professional instruments such as a thermal resistance tester. This thermal resistance tester can use the characteristics of the chip body diode and comprehensively consider the ambient temperature, power consumption, etc. to obtain the chip thermal resistance. However, this method is complex and has high testing costs.

[0004] The chip's over-temperature protection temperature is typically measured by applying ambient temperature to an incubator and measuring the temperature at which the chip inside the incubator requires over-temperature protection. However, this test method is limited by the incubator's temperature range. Laboratory incubators typically have a maximum temperature between 150°C and 180°C, making it inapplicable to over-temperature protection measurements at higher temperatures. Summary of the Invention

[0005] In order to solve the problems in the related art, the embodiments of the present disclosure provide a chip thermal resistance and over-temperature protection temperature testing system, method, device and medium.

[0006] In a first aspect, an embodiment of the present disclosure provides a chip thermal resistance and over-temperature protection temperature testing system, comprising: The chip to be tested is provided with an over-temperature protection circuit, wherein the over-temperature protection circuit starts over-temperature protection when detecting that the temperature of the chip to be tested reaches an initial over-temperature protection temperature; A test board, connected to the chip to be tested, and used to keep the chip to be tested in a normal working state; A DC power supply, connected to the test board, for supplying power to the chip under test; An electronic load, connected to the test board, for providing a load for the chip to be tested; A controllable constant temperature box, used to provide an ambient temperature for the chip to be tested to operate, and a test board connected to the chip to be tested is placed in the controllable constant temperature box; A computing device is used to obtain the chip power consumption of the chip under test at the moment before the over-temperature protection occurs at the predetermined ambient temperature when the controllable constant temperature box is at a predetermined ambient temperature and the electronic load gradually increases from 0 until the chip under test is over-temperature protected; and after obtaining the chip power consumption corresponding to n predetermined ambient temperatures, calculate the chip thermal resistance and the final over-temperature protection temperature based on the n predetermined ambient temperatures and their corresponding n chip power consumptions, where n is an integer greater than or equal to 2.

[0007] The computing device is specifically used for: The chip thermal resistance Rjc and the final over-temperature protection temperature T are calculated according to the following formula: P = (T-TA) / Rjc; Wherein, TA is the predetermined ambient temperature, and P is the chip power consumption.

[0008] In one possible implementation, the computing device is specifically configured to: The n predetermined ambient temperatures and their corresponding n chip power consumptions are fitted according to the formula P = (T-TA) / Rjc to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T.

[0009] In one possible implementation, the computing device is specifically configured to: Obtain the input voltage, input current, output voltage and output current of the chip to be tested at the moment before the over-temperature protection occurs; based on the input voltage, input current, output voltage and output current, calculate the chip power consumption of the chip to be tested at the moment before the over-temperature protection occurs.

[0010] In one possible implementation, the power input terminal and the ground terminal of the test board both support Kelvin connection, and when the DC power supply also supports Kelvin connection, the voltage output by the DC power supply is used as the input voltage of the chip under test; When the DC power supply does not support Kelvin connection, the test system further includes a first voltage measuring instrument, which is connected to the chip to be tested and is used to measure the input voltage of the chip to be tested.

[0011] In a possible implementation, when the DC power supply supports current measurement, the current output by the DC power supply measured by the DC power supply is used as the input current of the chip under test; When the DC power supply does not support current measurement, the test system further includes a first current measuring instrument, which is connected to the chip to be tested and is used to measure the input current of the chip to be tested.

[0012] In a possible implementation, when the electronic load supports current measurement, the current input to the electronic load measured by the electronic load is used as the output current of the chip under test; When the electronic load does not support current measurement, the test system further includes a second current measuring instrument, which is connected to the chip to be tested and is used to measure the output current of the chip to be tested.

[0013] In a possible implementation, the test system further includes a second voltage measuring instrument; The second voltage measuring instrument is connected to the chip under test and is used to measure the output voltage of the chip under test.

[0014] In a possible implementation, if the controllable constant temperature box has a temperature measurement function, the controllable constant temperature box controls the temperature inside the controllable constant temperature box to be at a predetermined ambient temperature based on the temperature measurement function of the controllable constant temperature box; If the controllable constant temperature box does not have a temperature measurement function, the test system also includes a temperature measurement module, which is located in the controllable constant temperature box and is used to measure the temperature inside the controllable constant temperature box; the controllable constant temperature box is connected to the temperature measurement module and is used to control the temperature inside the controllable constant temperature box to a predetermined ambient temperature based on the temperature measured by the temperature measurement module.

[0015] In a possible implementation, the chip to be tested includes a power chip.

[0016] In a second aspect, an embodiment of the present disclosure provides a method for testing chip thermal resistance and over-temperature protection temperature, including: Obtaining the chip power consumption of the chip under test at a moment before the over-temperature protection occurs at a predetermined ambient temperature; After obtaining the chip power consumption corresponding to n predetermined ambient temperatures, the chip thermal resistance and the final over-temperature protection temperature are calculated based on the n predetermined ambient temperatures and their corresponding n chip power consumptions, where n is an integer greater than or equal to 2.

[0017] In a possible implementation, the calculating the chip thermal resistance and the final over-temperature protection temperature based on the n predetermined ambient temperatures and their corresponding n chip power consumptions includes: According to the formula P = (T-TA) / Rjc, the chip thermal resistance Rjc and the final over-temperature protection temperature T are calculated, where TA is the predetermined ambient temperature and P is the chip power consumption.

[0018] In a possible implementation, the chip thermal resistance Rjc and the final over-temperature protection temperature T are calculated according to the formula P = (T-TA) / Rjc, including: The n predetermined ambient temperatures and their corresponding n chip power consumptions are fitted according to the formula P = (T-TA) / Rjc to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T.

[0019] In a possible implementation, obtaining the chip power consumption of the chip under test at a moment before the over-temperature protection occurs at a predetermined ambient temperature includes: Obtaining the input voltage, input current, output voltage, and output current of the chip under test at a moment before the over-temperature protection occurs; The chip power consumption of the chip to be tested at a moment before the over-temperature protection occurs is calculated based on the input voltage, input current, output voltage and output current.

[0020] In a third aspect, an embodiment of the present disclosure provides a device for testing chip thermal resistance and over-temperature protection temperature, comprising: An acquisition module is configured to acquire the chip power consumption of the chip under test at a moment before the over-temperature protection occurs at a predetermined ambient temperature; The parameter calculation module is configured to obtain the chip power consumption corresponding to n predetermined ambient temperatures, and then calculate the chip thermal resistance and the final over-temperature protection temperature based on the n predetermined ambient temperatures and their corresponding n chip power consumption, where n is an integer greater than or equal to 2.

[0021] In a possible implementation, the parameter calculation module is configured to: According to the formula P = (T-TA) / Rjc, the chip thermal resistance Rjc and the final over-temperature protection temperature T are calculated, where TA is the predetermined ambient temperature and P is the chip power consumption.

[0022] In a possible implementation, the parameter calculation module is configured to: The n predetermined ambient temperatures and their corresponding n chip power consumptions are fitted according to the formula P = (T-TA) / Rjc to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T.

[0023] In a possible implementation, the acquisition module is configured to: Obtaining the input voltage, input current, output voltage, and output current of the chip under test at a moment before the over-temperature protection occurs; The chip power consumption of the chip to be tested at a moment before the over-temperature protection occurs is calculated based on the input voltage, input current, output voltage and output current.

[0024] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium having computer instructions stored thereon, which, when executed by a processor, implement the method as described in any one of the second aspects.

[0025] According to the technical solution provided by the embodiment of the present disclosure, the chip to be tested has an over-temperature protection function, a test board connected to the chip to be tested, and is used to put the chip to be tested in a normal working state; a DC power supply connected to the test board, and is used to power the chip to be tested; an electronic load connected to the test board, and is used to provide a load for the chip to be tested; a controllable constant temperature box, and is used to provide the ambient temperature of the working environment of the chip to be tested, and the test board connected to the chip to be tested is placed in the controllable constant temperature box; a computing device, and is used to obtain the chip power consumption of the chip to be tested at the moment before the over-temperature protection occurs at the predetermined ambient temperature when the controllable constant temperature box is at a predetermined ambient temperature and the electronic load gradually increases from 0 until the chip to be tested is over-temperature protected; and after obtaining the chip power consumption corresponding to n predetermined ambient temperatures from the data acquisition module, based on The chip thermal resistance and the final over-temperature protection temperature are calculated based on the n predetermined ambient temperatures and the corresponding n chip power consumptions. By utilizing the characteristic that the power consumption of the chip to be tested increases with the increase of the electronic load and the over-temperature protection function of the chip to be tested itself, the chip power consumption of the chip to be tested at the moment before the over-temperature protection occurs at different predetermined ambient temperatures and different loads is tested. The chip thermal resistance and the final over-temperature protection temperature are calculated based on the n predetermined ambient temperatures and the corresponding n chip power consumptions. The chip thermal resistance and the final over-temperature protection temperature obtained by the test system are highly accurate, highly operational, and have low testing costs. Moreover, by calculating the chip thermal resistance and the final over-temperature protection temperature based on multiple n predetermined ambient temperatures and the corresponding n chip power consumptions, the chip to be tested whose operating temperature exceeds the temperature of the incubator can also be measured without being limited by the temperature range of the incubator.

[0026] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Other features, objectives and advantages of the present disclosure will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings.

[0028] Figure 1 A structural block diagram of a chip thermal resistance and over-temperature protection temperature testing system provided according to an embodiment of the present disclosure is shown.

[0029] Figure 2 A structural block diagram of another chip thermal resistance and over-temperature protection temperature testing system provided according to an embodiment of the present disclosure is shown.

[0030] Figure 3 A flow chart of a method for testing chip thermal resistance and over-temperature protection temperature provided by an embodiment of the present disclosure is shown.

[0031] Figure 4 A structural block diagram of a chip thermal resistance and over-temperature protection temperature testing device provided according to an embodiment of the present disclosure is shown.

[0032] Figure 5 A schematic diagram showing the structure of a computer system suitable for implementing the method of the embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0033] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, parts not related to the description of the exemplary embodiments are omitted in the accompanying drawings.

[0034] In the present disclosure, it should be understood that terms such as "include" or "have" are intended to indicate the presence of features, numbers, steps, actions, components, parts, or combinations thereof disclosed in the present specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, actions, components, parts, or combinations thereof exist or are added.

[0035] It should also be noted that, in the absence of conflict, the embodiments and features of the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0036] Figure 1 FIG. 1 shows a block diagram of a chip thermal resistance and over-temperature protection temperature test system according to an embodiment of the present disclosure. Figure 1 As shown, the test system includes: a chip to be tested 101, a test board 102, a DC power supply 103, an electronic load 104, a controllable constant temperature box 105 and a computing device 100.

[0037] In one possible embodiment, the chip under test 101 has an over-temperature protection function. An initial over-temperature protection temperature of the chip under test 101 can be obtained through pre-simulation testing, and a temperature protection circuit is provided within the chip under test 101. When the internal temperature of the chip is detected to be greater than the initial over-temperature protection temperature, the temperature protection circuit automatically activates over-temperature protection, thereby realizing the over-temperature protection function of the chip under test 101. The chip under test 101 in this embodiment is primarily a power supply chip.

[0038] In a possible implementation, the test board 102 is connected to the chip under test 101 . The chip under test 101 can be placed on the test board 102 and electrically connected to the test board 102 . The test board 102 can keep the chip under test 101 in a normal working state.

[0039] In one possible embodiment, the DC power supply 103 and the electronic load 104 are both connected to the test board 102. The DC power supply 103 can power the chip under test 101 through the circuit on the test board 102, and the electronic load 104 can provide a load for the chip under test 101 through the circuit on the test board 102.

[0040] In one possible embodiment, the controllable constant temperature box 105 can provide an operating environment temperature for the chip under test 101. During testing, the test board 102 connected to the chip under test 101 is placed in the controllable constant temperature box 105, which provides a constant environment temperature.

[0041] In a possible embodiment, the specific testing process may be to control the controllable constant temperature box 105 to be at a predetermined ambient temperature, and control the electronic load 104 to gradually increase from 0 until the chip under test 101 is over-temperature protected, so as to obtain the chip power consumption of the chip under test 101 at the moment before the over-temperature protection occurs.

[0042] It should be noted that the control of the temperature in the controllable constant temperature box 105 and the control of the electronic load 104 can be manually controlled by the tester. For example, a temperature selection button is provided on the controllable constant temperature box 105, and the tester can operate the selection button to control the controllable constant temperature box 105 to be at a predetermined ambient temperature; and an operation button is provided on the electronic load 104, and the tester can operate the operation button to control the electronic load 104 to gradually increase from 0. Alternatively, the temperature in the controllable constant temperature box 105 and the electronic load 104 can be controlled by a control device. When controlled by the control device, the control device can connect the controllable constant temperature box 105 and the electronic load 104 through corresponding ports, so that the control device can send control instructions to the controllable constant temperature box 105 and the electronic load 104 through the corresponding ports, controlling the controllable constant temperature box 105 to be at a predetermined ambient temperature and controlling the electronic load 104 to gradually increase from 0.

[0043] In one possible implementation, assuming that at a predetermined ambient temperature, over-temperature protection does not occur at time t, but occurs at time t1, the next moment after time t, the chip power consumption of the chip under test 101 at time t is obtained as the chip power consumption corresponding to the predetermined ambient temperature. In this way, the chip power consumption corresponding to n predetermined ambient temperatures can be obtained. After obtaining the chip power consumption corresponding to n predetermined ambient temperatures, the chip thermal resistance and the final over-temperature protection temperature can be calculated based on the n predetermined ambient temperatures and their corresponding n chip power consumptions, where n is an integer greater than or equal to 2.

[0044] In one possible implementation, the predetermined ambient temperature can be determined based on the chip's operating temperature range and the temperature range of the controllable constant temperature box 105. A number of n (n is an integer greater than or equal to 2) predetermined ambient temperatures TA1, TA2, TA3, ..., TAn can be determined. Preferably, these n predetermined ambient temperatures TA1, TA2, TA3, ..., TAn can be an arithmetic progression. It should be noted that if the chip's operating temperature exceeds the temperature range of the controllable constant temperature box 105, n temperature values ​​within the higher temperature range of the controllable constant temperature box 105 can be selected as the predetermined ambient temperature.

[0045] In one possible implementation, the electronic load 104 can be controlled to gradually increase from 0 under the n predetermined ambient temperatures TA1, TA2, TA3, ... TAn until the chip under test 101 is over-temperature protected, so that the computing device 100 can obtain the chip power consumption P1, P2, P3, ..., Pn of the chip under test 101 at the moment before the over-temperature protection occurs.

[0046] In one possible embodiment, the computing device 100 can calculate the chip thermal resistance Rjc and the final over-temperature protection temperature T based on the relationship between the chip thermal resistance Rjc and the final over-temperature protection temperature T, the ambient temperature TA, and the power consumption P of multiple chips corresponding to the ambient temperature TA, by substituting n predetermined ambient temperatures TA1, TA2, TA3, ...TAn and n chip power consumptions P1, P2, P3, ..., Pn into TA and P in the relationship.

[0047] The chip under test 101 in this embodiment has an over-temperature protection function, a test board 102, connected to the chip under test 101, for keeping the chip under test 101 in a normal working state; a DC power supply 103, connected to the test board 102, for supplying power to the chip under test 101; an electronic load 104, connected to the test board 102, for providing a load for the chip under test 101; a controllable constant temperature box 105, for providing an ambient temperature at which the chip under test 101 works, and the test board 102 connected to the chip under test 101 is placed in the controllable constant temperature box 105; a computing device 100, for obtaining the chip power consumption of the chip under test 101 at the moment before the over-temperature protection occurs at the predetermined ambient temperature when the controllable constant temperature box 105 is at a predetermined ambient temperature and the electronic load 104 gradually increases from 0 until the chip under test 101 is over-temperature protected; and After the acquisition module obtains the chip power consumption corresponding to n predetermined ambient temperatures, the chip thermal resistance and the final over-temperature protection temperature are calculated based on the n predetermined ambient temperatures and the corresponding n chip power consumptions. By utilizing the characteristic that the power consumption of the chip to be tested increases with the increase of the electronic load and the over-temperature protection function of the chip to be tested itself, the chip power consumption of the chip to be tested at the moment before the over-temperature protection occurs under different predetermined ambient temperatures and different loads is tested. The chip thermal resistance and the final over-temperature protection temperature are calculated by the n predetermined ambient temperatures and the corresponding n chip power consumptions. The chip thermal resistance and the final over-temperature protection temperature obtained by the test system are highly accurate, highly operational, and have low testing costs. Moreover, by calculating the chip thermal resistance and the final over-temperature protection temperature by multiple n predetermined ambient temperatures and the corresponding n chip power consumptions, the chip to be tested whose operating temperature exceeds the temperature of the incubator can also be measured without being restricted by the temperature range of the incubator.

[0048] In one possible implementation, the computing device 100 calculates the chip thermal resistance and the final over-temperature protection temperature based on the n predetermined ambient temperatures and their corresponding n chip power consumptions, including: The chip thermal resistance Rjc and the final over-temperature protection temperature T are calculated according to the following formula: P = (T-TA) / Rjc; Wherein, TA is the predetermined ambient temperature, and P is the chip power consumption.

[0049] In this embodiment, in P = (T-TA) / Rjc, TA is the predetermined ambient temperature, which is an independent variable, and P is the chip power consumption, which is a dependent variable. n = 2 predetermined ambient temperatures and their corresponding n = 2 chip power consumptions P can be obtained through testing. These two predetermined ambient temperatures TA and their corresponding two chip power consumptions P are substituted into the formula P = (T-TA) / Rjc, and the two-variable linear equation is solved to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T.

[0050] In a possible implementation, the computing device 100 calculates the chip thermal resistance Rjc and the final over-temperature protection temperature T according to the following formula: P = (T-TA) / Rjc, including: The n predetermined ambient temperatures and their corresponding n chip power consumptions are fitted according to the formula P = (T-TA) / Rjc to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T.

[0051] In this embodiment, when n is greater than 2, the independent variable TA and the dependent variable P in the formula P = (T-TA) / Rjc may not satisfy a linear relationship due to measurement errors and other reasons. At this time, in order to more accurately calculate the chip thermal resistance Rjc and the final over-temperature protection temperature T, the independent variable TA and the dependent variable P can be linearly fitted to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T in P = (T-TA) / Rjc; optionally, the least squares method can be used for linear fitting. Of course, other algorithms can also be used for fitting, which is not limited here.

[0052] In a possible implementation, the chip power consumption of the chip under test 101 at a moment before the over-temperature protection occurs at a predetermined ambient temperature of the computing device 100 includes: Obtain the input voltage, input current, output voltage and output current of the chip under test 101 at the moment before the over-temperature protection occurs; based on the input voltage, input current, output voltage and output current, calculate the chip power consumption of the chip under test 101 at the moment before the over-temperature protection occurs.

[0053] In this embodiment, during the test process, the input voltage, input current, output voltage and output current of the chip under test 101 can be continuously collected. In this way, after the over-temperature protection of the chip under test 101 occurs, the computing device 100 can obtain the input voltage V of the chip under test 101 before the over-temperature protection occurs. IN , input current I IN , output voltage V OUT and output current I OUT , and according to the formula P= V IN× I IN -V OUT× I OUT The chip power consumption P of the chip under test 101 at the moment before the over-temperature protection occurs is calculated.

[0054] In a possible implementation, there are two ways to measure the input voltage of the chip under test 101: The first method is: when the power input terminal and the ground terminal of the test board 102 both support Kelvin connection and the DC power supply 103 also supports Kelvin connection, the voltage output by the DC power supply 103 is used as the input voltage of the chip under test 101.

[0055] Here, Kelvin connection is a four-wire connection method for highly accurate measurement of parameters such as resistance and voltage. In chip testing, Kelvin connection is a method for improving measurement accuracy by reducing the resistance of the test system. In this embodiment, the DC power supply 103 needs to be connected to the chip under test 101 through the wires on the test board 102 to power the chip under test 101. Due to the presence of the DC impedance of the wires, the supply voltage of the DC power supply 103 will drop. To avoid this situation, in this embodiment, the power input terminal and the ground terminal of the test board 102 both support Kelvin connection, and the DC power supply 103 also supports Kelvin connection. This eliminates the voltage drop effect generated on the wires in the circuit, and can output the voltage provided by the DC power supply 103 to the chip under test 101 without a significant voltage drop. Therefore, in this embodiment, the voltage output by the DC power supply 103 can be directly used as the input voltage of the chip under test 101. The voltage output by the DC power supply 103 is a fixed value and can be manually input into the computing device 100 by the tester.

[0056] The second method is: when the DC power supply 103 does not support Kelvin connection, Figure 2 As shown, the test system further includes a first voltage measuring instrument 106 , which is connected to the chip under test 101 and is used to measure the input voltage of the chip under test 101 .

[0057] Here, if the DC power supply 103 does not support Kelvin connection, the supply voltage of the DC power supply 103 will drop due to the existence of the DC impedance of the wire, and the input voltage obtained by the chip under test 101 will be lower than the voltage output by the DC power supply. At this time, the first voltage measuring instrument 106 can be connected to the chip under test 101 (such as connected to the voltage input terminal and the ground terminal of the chip under test 101) to measure the input voltage of the chip under test 101. The first voltage measuring instrument 106 can be an instrument that can measure voltage, such as a multimeter or a voltmeter.

[0058] It should be noted here that the input voltage of the chip under test 101 measured by the first voltage measuring instrument 106 can be manually input into the computing device 100 by the tester, or the computing device 100 can be connected to the first voltage measuring instrument 106 and sent to the computing device 100 by the first voltage measuring instrument 106.

[0059] In a possible implementation, the input current of the chip under test 101 can be measured in the following two ways: The first measurement method is: when the DC power supply 103 supports current measurement, the current output by the DC power supply 103 measured by the DC power supply 103 is used as the input current of the chip under test 101; The second measurement method is: when the DC power supply 103 does not support current measurement, the test system further includes a first current measuring instrument 107 , which is connected to the chip under test 101 and is used to measure the input current of the chip under test 101 .

[0060] Here, some DC power supplies 103 support current measurement and can measure the current output by the DC power supply 103. The current output by the DC power supply 103 measured by the DC power supply 103 can be used as the input current of the chip under test 101. It should be noted that the DC power supply 103 can measure and display the input current of the chip under test 101, and the tester can manually input the input current into the computing device 100. Alternatively, the computing device 100 can be connected to the DC power supply 103, and the DC power supply 103 can send the input current to the computing device 100.

[0061] Here, some DC power supplies 103 do not support current measurement. The test system also includes a first current measuring instrument 107. The first current measuring instrument 107 can be connected to the chip under test 101 (e.g., to any point between the chip under test 101 and the DC power supply 103) to measure the input current of the chip under test 101. The first current measuring instrument 107 can be a multimeter, current sensor, or other instrument capable of measuring current. It should be noted that the input current of the chip under test 101 measured by the first current measuring instrument 107 can be manually input into the computing device 100 by the tester, or the computing device 100 can be connected to the first current measuring instrument 107, and the first current measuring instrument 107 can transmit the current to the computing device 100.

[0062] In a possible implementation, the output current of the chip under test 101 is measured in the following two ways: The first measurement method is: when the electronic load 104 supports current measurement, the current input to the electronic load 104 measured by the electronic load 104 is used as the output current of the chip under test 101; The second measurement method is: when the electronic load 104 does not support current measurement, the test system further includes a second current measuring instrument 108 , which is connected to the chip under test 101 and is used to measure the output current of the chip under test 101 .

[0063] Here, some electronic loads 104 support current measurement and can measure the current input to the electronic load 104. The current input to the electronic load 104 measured by the electronic load 104 can be used as the output current of the chip under test 101. It should be noted that the electronic load 104 can measure and display the output current of the chip under test 101, and the tester can manually input the output current into the computing device 100. Alternatively, the computing device 100 can be connected to the electronic load 104, and the DC power supply 103 can send the output current to the computing device 100.

[0064] Here, some electronic loads 104 do not support current measurement. The test system also includes a second current measuring instrument 108. The second current measuring instrument 108 can be connected to the chip under test 101 (e.g., to any point between the chip under test 101 and the load) to measure the output current of the chip under test 101. The second current measuring instrument 108 can be a multimeter, current sensor, or other instrument capable of measuring current. It should be noted that the output current of the chip under test 101 measured by the second current measuring instrument 108 can be manually input into the computing device 100 by the tester, or the computing device 100 can be connected to the second current measuring instrument 108 and the second current measuring instrument 108 can be sent to the computing device 100.

[0065] In a possible implementation, the output voltage of the chip under test 101 can be measured using a second voltage measuring instrument 109 . The test system further includes a second voltage measuring instrument 109 ; the second voltage measuring instrument 109 is connected to the chip under test 101 and is used to measure the output voltage of the chip under test 101 .

[0066] Here, a second voltage measuring instrument 109 can be connected to the chip under test 101 (e.g., connected to the voltage output terminal and the ground terminal of the chip under test 101) to measure the output voltage of the chip under test 101. The second voltage measuring instrument 109 can be a multimeter, voltmeter, or other instrument capable of measuring voltage. It should be noted that the output voltage of the chip under test 101 measured by the second voltage measuring instrument 109 can be manually input into the computing device 100 by a tester, or the computing device 100 can be connected to the second voltage measuring instrument 109 and the second voltage measuring instrument 109 can be sent to the computing device 100.

[0067] In a possible implementation, if the controllable constant temperature box 105 has a temperature measurement function, the temperature inside the controllable constant temperature box 105 is regulated based on the temperature measurement function of the controllable constant temperature box 105; If the controllable constant temperature box 105 does not have a temperature measurement function, the test system further includes a temperature measurement module 110 . The temperature measurement module 110 is located in the controllable constant temperature box 105 and is used to measure the temperature in the controllable constant temperature box 105 .

[0068] Here, some controllable constant temperature boxes 105 have a temperature measurement function, while others do not. If a temperature measurement module 110 such as a temperature sensor is installed on the controllable constant temperature box 105 and has a temperature measurement function, the controllable constant temperature box 105 can control the temperature inside the controllable constant temperature box 105 based on the temperature measurement function of the controllable constant temperature box 105 so that it is at a predetermined ambient temperature. If the controllable constant temperature box 105 does not have a temperature measurement function, the test system further includes a temperature measurement module 110, which is placed inside the controllable constant temperature box 105 and is used to measure the temperature inside the controllable constant temperature box 105; the controllable constant temperature box 105 is connected to the temperature measurement module 110 and can control the temperature inside the controllable constant temperature box 105 to be at a predetermined ambient temperature based on the temperature measured by the temperature measurement module 110. For example, the controllable constant temperature box 105 can increase the temperature when the measured temperature does not reach the predetermined ambient temperature, and decrease the temperature when it is higher than the predetermined ambient temperature, etc.

[0069] The present disclosure provides a method for testing chip thermal resistance and over-temperature protection temperature. Figure 3 FIG. 1 is a flow chart showing a method for testing chip thermal resistance and over-temperature protection temperature provided by an embodiment of the present disclosure. Figure 3 As shown, the chip thermal resistance and over-temperature protection temperature testing method includes the following steps S301-S302: In step S301, the chip power consumption of the chip under test at the moment before the over-temperature protection occurs at a predetermined ambient temperature is obtained; In step S302, after obtaining the chip power consumption corresponding to n predetermined ambient temperatures, the chip thermal resistance and the final over-temperature protection temperature are calculated based on the n predetermined ambient temperatures and their corresponding n chip power consumptions, where n is an integer greater than or equal to 2.

[0070] In a possible implementation, the chip thermal resistance and over-temperature protection temperature testing method is applicable to electronic devices such as computers and computing devices that can perform chip thermal resistance and over-temperature protection temperature testing.

[0071] In one possible implementation, the predetermined ambient temperature can be determined based on the chip's operating temperature range and the temperature range of the controllable constant temperature chamber. A number of n (n is an integer greater than or equal to 2) predetermined ambient temperatures, TA1, TA2, TA3, ..., TAn, can be determined. Preferably, these n predetermined ambient temperatures, TA1, TA2, TA3, ..., TAn, can be an arithmetic progression. It should be noted that if the chip's operating temperature exceeds the temperature range of the controllable constant temperature chamber, n temperature values ​​within the higher temperature range of the controllable constant temperature chamber can be selected as the predetermined ambient temperature.

[0072] In one possible embodiment, the above-mentioned test system is used to control the electronic load to gradually increase from 0 under the n predetermined ambient temperatures TA1, TA2, TA3, ... TAn until the chip under test is over-temperature protected, so that the computing device can obtain the chip power consumption P1, P2, P3, ..., Pn of the chip under test at the moment before the over-temperature protection occurs.

[0073] In one possible embodiment, the computing device can calculate the chip thermal resistance Rjc and the final over-temperature protection temperature T by substituting n predetermined ambient temperatures TA1, TA2, TA3, ... TAn and n chip power consumptions P1, P2, P3, ..., Pn into the relationship between the chip thermal resistance Rjc and the final over-temperature protection temperature T, the ambient temperature TA, and the power consumption of multiple chips corresponding to the ambient temperature TA.

[0074] This embodiment can obtain the chip power consumption of the chip under test at the moment before the over-temperature protection occurs under different predetermined ambient temperatures and different loads by utilizing the characteristic that the power consumption of the chip under test increases with the increase of the electronic load and the over-temperature protection function of the chip under test itself. The chip thermal resistance and the final over-temperature protection temperature are calculated through n predetermined ambient temperatures and their corresponding n chip power consumptions. The chip thermal resistance and the final over-temperature protection temperature obtained by this test system are highly accurate, highly operational, and have low testing costs. Moreover, by calculating the chip thermal resistance and the final over-temperature protection temperature through multiple n predetermined ambient temperatures and their corresponding n chip power consumptions, chips under test whose operating temperatures exceed the temperature of the incubator can also be measured without being limited by the temperature range of the incubator.

[0075] In a possible implementation, the calculating the chip thermal resistance and the final over-temperature protection temperature based on the n predetermined ambient temperatures and their corresponding n chip power consumptions includes: According to the formula P = (T-TA) / Rjc, the chip thermal resistance Rjc and the final over-temperature protection temperature T are calculated, where TA is the predetermined ambient temperature and P is the chip power consumption.

[0076] In this embodiment, in P = (T-TA) / Rjc, TA is the predetermined ambient temperature, which is an independent variable, and P is the chip power consumption, which is a dependent variable. n = 2 predetermined ambient temperatures and their corresponding n = 2 chip power consumptions P can be obtained through testing. These two predetermined ambient temperatures and their corresponding two chip power consumptions P are substituted into the formula P = (T-TA) / Rjc, and the two-variable linear equation is solved to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T.

[0077] In a possible implementation, the chip thermal resistance Rjc and the final over-temperature protection temperature T are calculated according to the formula P = (T-TA) / Rjc, including: The n predetermined ambient temperatures and their corresponding n chip power consumptions are fitted according to the formula P = (T-TA) / Rjc to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T.

[0078] In this embodiment, when n is greater than 2, the independent variable TA and the dependent variable P in the formula P = (T-TA) / Rjc may not satisfy a linear relationship due to measurement errors and other reasons. At this time, in order to more accurately calculate the chip thermal resistance Rjc and the final over-temperature protection temperature T, the independent variable TA and the dependent variable P can be linearly fitted to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T in P = (T-TA) / Rjc; optionally, the least squares method can be used for linear fitting. Of course, other algorithms can also be used for fitting, which is not limited here.

[0079] In a possible implementation, obtaining the chip power consumption of the chip under test at a moment before the over-temperature protection occurs at a predetermined ambient temperature includes: Obtaining the input voltage, input current, output voltage, and output current of the chip under test at a moment before the over-temperature protection occurs; The chip power consumption of the chip to be tested at a moment before the over-temperature protection occurs is calculated based on the input voltage, input current, output voltage and output current.

[0080] In this embodiment, during the test process, the input voltage, input current, output voltage and output current of the chip under test can be continuously collected. In this way, after the over-temperature protection of the chip under test occurs, the computing device can obtain the input voltage V of the chip under test at the moment before the over-temperature protection occurs. IN , input current I IN , output voltage V OUT and output current I OUT , and according to the formula P= V IN× I IN -V OUT× I OUTThe chip power consumption P of the chip under test at the moment before the over-temperature protection occurs is calculated.

[0081] The present disclosure also provides a device for testing chip thermal resistance and over-temperature protection temperature. Figure 4 The following is a block diagram showing a device for testing chip thermal resistance and over-temperature protection temperature according to an embodiment of the present disclosure. The device can be implemented as part or all of an electronic device through software, hardware, or a combination of both. Figure 4 As shown, the testing device includes: The acquisition module 401 is configured to acquire the chip power consumption of the chip under test at a moment before the over-temperature protection occurs at a predetermined ambient temperature; The parameter calculation module 402 is configured to calculate the chip thermal resistance and the final over-temperature protection temperature based on the n predetermined ambient temperatures and their corresponding n chip power consumptions after obtaining the chip power consumption corresponding to n predetermined ambient temperatures, where n is an integer greater than or equal to 2.

[0082] In a possible implementation, the chip thermal resistance and over-temperature protection temperature testing device is suitable for electronic devices such as computers and computing devices that can perform chip thermal resistance and over-temperature protection temperature tests.

[0083] In one possible implementation, the predetermined ambient temperature can be determined based on the chip's operating temperature range and the temperature range of the controllable constant temperature chamber. A number of n (n is an integer greater than or equal to 2) predetermined ambient temperatures, TA1, TA2, TA3, ..., TAn, can be determined. Preferably, these n predetermined ambient temperatures, TA1, TA2, TA3, ..., TAn, can be an arithmetic progression. It should be noted that if the chip's operating temperature exceeds the temperature range of the controllable constant temperature chamber, n temperature values ​​within the higher temperature range of the controllable constant temperature chamber can be selected as the predetermined ambient temperature.

[0084] In one possible embodiment, the above-mentioned test system is used to control the electronic load to gradually increase from 0 under the n predetermined ambient temperatures TA1, TA2, TA3, ... TAn until the chip under test is over-temperature protected, so that the acquisition module 401 obtains the chip power consumption P1, P2, P3, ..., Pn of the chip under test at the moment before the over-temperature protection occurs.

[0085] In one possible implementation, the parameter calculation module 402 can calculate the chip thermal resistance Rjc and the final over-temperature protection temperature T by substituting n predetermined ambient temperatures TA1, TA2, TA3, ... TAn and n chip power consumptions P1, P2, P3, ..., Pn into the relationship between the chip thermal resistance Rjc and the final over-temperature protection temperature T, the ambient temperature TA, and the power consumption of multiple chips corresponding to the ambient temperature TA.

[0086] This embodiment can obtain the chip power consumption of the chip under test at the moment before the over-temperature protection occurs under different predetermined ambient temperatures and different loads by utilizing the characteristic that the power consumption of the chip under test increases with the increase of the electronic load and the over-temperature protection function of the chip under test itself. The chip thermal resistance and the final over-temperature protection temperature are calculated through n predetermined ambient temperatures and their corresponding n chip power consumptions. The chip thermal resistance and the final over-temperature protection temperature obtained by this test system are highly accurate, highly operational, and have low testing costs. Moreover, by calculating the chip thermal resistance and the final over-temperature protection temperature through multiple n predetermined ambient temperatures and their corresponding n chip power consumptions, chips under test whose operating temperatures exceed the temperature of the incubator can also be measured without being limited by the temperature range of the incubator.

[0087] In a possible implementation, the parameter calculation module is configured to: According to the formula P = (T-TA) / Rjc, the chip thermal resistance Rjc and the final over-temperature protection temperature T are calculated, where TA is the predetermined ambient temperature and P is the chip power consumption.

[0088] In this embodiment, in P = (T-TA) / Rjc, TA is the predetermined ambient temperature, which is an independent variable, and P is the chip power consumption, which is a dependent variable. n = 2 predetermined ambient temperatures and their corresponding n = 2 chip power consumptions P can be obtained through testing. These two predetermined ambient temperatures and their corresponding two chip power consumptions P are substituted into the formula P = (T-TA) / Rjc, and the two-variable linear equation is solved to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T.

[0089] In a possible implementation, the parameter calculation module is configured to: The n predetermined ambient temperatures and their corresponding n chip power consumptions are fitted according to the formula P = (T-TA) / Rjc to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T.

[0090] In this embodiment, when n is greater than 2, the independent variable TA and the dependent variable P in the formula P = (T-TA) / Rjc may not satisfy a linear relationship due to measurement errors and other reasons. At this time, in order to more accurately calculate the chip thermal resistance Rjc and the final over-temperature protection temperature T, the independent variable TA and the dependent variable P can be linearly fitted to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T in P = (T-TA) / Rjc; optionally, the least squares method can be used for linear fitting. Of course, other algorithms can also be used for fitting, which is not limited here.

[0091] In a possible implementation, the acquisition module is configured to: Obtaining the input voltage, input current, output voltage, and output current of the chip under test at a moment before the over-temperature protection occurs; The chip power consumption of the chip to be tested at a moment before the over-temperature protection occurs is calculated based on the input voltage, input current, output voltage and output current.

[0092] In this embodiment, during the test process, the input voltage, input current, output voltage and output current of the chip under test can be continuously collected. In this way, after the over-temperature protection of the chip under test occurs, the acquisition module can obtain the input voltage V of the chip under test at the moment before the over-temperature protection occurs. IN , input current I IN , output voltage V OUT and output current I OUT , and according to the formula P= V IN× I IN -V OUT× I OUT The chip power consumption P of the chip under test at the moment before the over-temperature protection occurs is calculated.

[0093] The technical terms and technical features mentioned in the above-mentioned method implementation methods and device implementation methods are the same as or similar to those mentioned in the above-mentioned test system implementation methods. For the explanation and description of the technical terms and technical features involved in the method implementation methods and device implementation methods, please refer to the explanation and description of the above-mentioned test system implementation methods, and will not be repeated here.

[0094] Figure 5 A schematic diagram showing the structure of a computer system suitable for implementing the method of the embodiment of the present disclosure is shown.

[0095] like Figure 5 As shown, computer system 500 includes a processing unit 501, which can execute various processes in the above-described embodiments according to programs stored in a read-only memory (ROM) 502 or programs loaded from a storage unit 508 into a random access memory (RAM) 503. Various programs and data required for the operation of computer system 500 are also stored in RAM 503. Processing unit 501, ROM 502, and RAM 503 are connected to each other via a bus 504. An input / output (I / O) interface 505 is also connected to bus 504.

[0096] The following components are connected to the I / O interface 505: an input section 506 including a keyboard, mouse, and the like; an output section 507 including components such as a cathode ray tube (CRT), a liquid crystal display (LCD), and speakers; a storage section 508 including components such as a hard disk; and a communication section 509 including a network interface card such as a LAN card or a modem. The communication section 509 performs communication processing via a network such as the Internet. A drive 510 is also connected to the I / O interface 505 as needed. Removable media 511, such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory, is installed in the drive 510 as needed, so that computer programs read therefrom can be installed into the storage section 508 as needed. The processing unit 501 can be implemented as a CPU, a GPU, a TPU, an FPGA, an NPU, or other processing units.

[0097] In particular, according to embodiments of the present disclosure, the methods described above can be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising computer instructions that, when executed by a processor, implement the method steps described above. In such embodiments, the computer program product can be downloaded and installed from a network via the communication portion 509 and / or installed from removable media 511.

[0098] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment or part of code, and the module, program segment or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or can be implemented using a combination of dedicated hardware and computer instructions.

[0099] The units or modules involved in the embodiments described in this disclosure may be implemented by software or programmable hardware. The units or modules described may also be provided in a processor, and the names of these units or modules do not, in certain circumstances, constitute limitations on the units or modules themselves.

[0100] As another aspect, the present disclosure further provides a computer-readable storage medium. This computer-readable storage medium may be included in the electronic device or computer system described in the above embodiments, or may be a standalone computer-readable storage medium not incorporated into the device. The computer-readable storage medium stores one or more programs, which are used by one or more processors to execute the methods described in the present disclosure.

[0101] The above description is merely a preferred embodiment of the present disclosure and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of the invention herein is not limited to technical solutions formed by specific combinations of the aforementioned technical features. It also encompasses other technical solutions formed by any combination of the aforementioned technical features or their equivalents, without departing from the inventive concept. For example, a technical solution formed by replacing the aforementioned features with (but not limited to) technical features with similar functions disclosed in this disclosure.

Claims

1. A chip thermal resistance and over-temperature protection temperature testing system, characterized in that: include: The chip to be tested is provided with an over-temperature protection circuit, wherein the over-temperature protection circuit starts over-temperature protection when detecting that the temperature of the chip to be tested reaches an initial over-temperature protection temperature; A test board, connected to the chip to be tested, and used to keep the chip to be tested in a normal working state; A DC power supply, connected to the test board, for supplying power to the chip under test; An electronic load, connected to the test board, for providing a load for the chip to be tested; A controllable constant temperature box, used to provide an ambient temperature for the chip to be tested to operate, and a test board connected to the chip to be tested is placed in the controllable constant temperature box; A computing device is used to obtain the chip power consumption of the chip under test at the moment before the over-temperature protection occurs at the predetermined ambient temperature when the controllable constant temperature box is at a predetermined ambient temperature and the electronic load gradually increases from 0 until the chip under test is over-temperature protected; and after obtaining the chip power consumption corresponding to n predetermined ambient temperatures, calculate the chip thermal resistance and the final over-temperature protection temperature based on the n predetermined ambient temperatures and their corresponding n chip power consumptions, where n is an integer greater than or equal to 2.

2. The test system according to claim 1, wherein: The computing device is specifically used for: The chip thermal resistance Rjc and the final over-temperature protection temperature T are calculated according to the following formula: P = (T-TA) / Rjc; Wherein, TA is the predetermined ambient temperature, and P is the chip power consumption.

3. The test system according to claim 2, wherein: The computing device is specifically used for: The n predetermined ambient temperatures and their corresponding n chip power consumptions are linearly fitted according to the formula P = (T-TA) / Rjc to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T.

4. The test system according to claim 1, wherein: The computing device is specifically used for: Obtain the input voltage, input current, output voltage and output current of the chip to be tested at the moment before the over-temperature protection occurs; based on the input voltage, input current, output voltage and output current, calculate the chip power consumption of the chip to be tested at the moment before the over-temperature protection occurs.

5. The test system according to claim 4, characterized in that: The power input terminal and the ground terminal of the test board both support Kelvin connection. When the DC power supply also supports Kelvin connection, the voltage output by the DC power supply is used as the input voltage of the chip to be tested; When the DC power supply does not support Kelvin connection, the test system further includes a first voltage measuring instrument; the first voltage measuring instrument is connected to the chip to be tested and is used to measure the input voltage of the chip to be tested.

6. The test system according to claim 4, characterized in that: When the DC power supply supports current measurement, the current output by the DC power supply measured by the DC power supply is used as the input current of the chip under test; When the DC power supply does not support current measurement, the test system further includes a first current measuring instrument; The first current measuring instrument is connected to the chip to be tested and is used to measure the input current of the chip to be tested.

7. The test system according to claim 4, characterized in that: When the electronic load supports current measurement, the current input to the electronic load measured by the electronic load is used as the output current of the chip under test; When the electronic load does not support current measurement, the test system further includes a second current measuring instrument, which is connected to the chip to be tested and is used to measure the output current of the chip to be tested.

8. The test system according to claim 4, wherein: The test system also includes a second voltage measuring instrument; The second voltage measuring instrument is connected to the chip under test and is used to measure the output voltage of the chip under test.

9. The test system according to claim 1, wherein: If the controllable constant temperature box has a temperature measurement function, the controllable constant temperature box controls the temperature inside the controllable constant temperature box to be at a predetermined ambient temperature based on the temperature measurement function of the controllable constant temperature box; If the controllable constant temperature box does not have a temperature measurement function, the test system also includes a temperature measurement module, which is located in the controllable constant temperature box and is used to measure the temperature inside the controllable constant temperature box; the controllable constant temperature box is connected to the temperature measurement module and is used to control the temperature inside the controllable constant temperature box to a predetermined ambient temperature based on the temperature measured by the temperature measurement module.

10. The test system according to claim 1, wherein: The chip to be tested includes a power chip.

11. A method for testing chip thermal resistance and over-temperature protection temperature, characterized in that: include: Obtain the chip power consumption of the chip under test at the moment before the over-temperature protection occurs at a predetermined ambient temperature; After obtaining the chip power consumption corresponding to n predetermined ambient temperatures, the chip thermal resistance and the final over-temperature protection temperature are calculated based on the n predetermined ambient temperatures and their corresponding n chip power consumptions, where n is an integer greater than or equal to 2.

12. The testing method according to claim 11, characterized in that: The calculating the chip thermal resistance and the final over-temperature protection temperature based on the n predetermined ambient temperatures and the corresponding n chip power consumptions includes: According to the formula P = (T-TA) / Rjc, the chip thermal resistance Rjc and the final over-temperature protection temperature T are calculated, where TA is the predetermined ambient temperature and P is the chip power consumption.

13. The testing method according to claim 12, characterized in that: According to the formula P = (T-TA) / Rjc, the chip thermal resistance Rjc and the final over-temperature protection temperature T are calculated, including: The n predetermined ambient temperatures and their corresponding n chip power consumptions are fitted according to the formula P = (T-TA) / Rjc to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T.

14. The testing method according to claim 11, characterized in that: The step of obtaining the chip power consumption of the chip under test at a moment before the over-temperature protection occurs at a predetermined ambient temperature includes: Obtaining the input voltage, input current, output voltage, and output current of the chip under test at a moment before the over-temperature protection occurs; The chip power consumption of the chip to be tested at a moment before the over-temperature protection occurs is calculated based on the input voltage, input current, output voltage and output current.

15. A device for testing chip thermal resistance and over-temperature protection temperature, characterized in that: include: An acquisition module is configured to acquire the chip power consumption of the chip under test at a moment before the over-temperature protection occurs at a predetermined ambient temperature; The parameter calculation module is configured to obtain the chip power consumption corresponding to n predetermined ambient temperatures, and then calculate the chip thermal resistance and the final over-temperature protection temperature based on the n predetermined ambient temperatures and their corresponding n chip power consumption, where n is an integer greater than or equal to 2.

16. The testing device according to claim 15, characterized in that The parameter calculation module is configured to: According to the formula P = (T-TA) / Rjc, the chip thermal resistance Rjc and the final over-temperature protection temperature T are calculated, where TA is the predetermined ambient temperature and P is the chip power consumption.

17. The testing device according to claim 16, characterized in that The parameter calculation module is configured to: The n predetermined ambient temperatures and their corresponding n chip power consumptions are fitted according to the formula P = (T-TA) / Rjc to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T.

18. The testing device according to claim 15, characterized in that The acquisition module is configured to: Obtaining the input voltage, input current, output voltage, and output current of the chip under test at a moment before the over-temperature protection occurs; The chip power consumption of the chip to be tested at a moment before the over-temperature protection occurs is calculated based on the input voltage, input current, output voltage and output current.

19. A readable storage medium, characterized in that Computer instructions are stored thereon, and when the computer instructions are executed by a processor, the method according to any one of claims 11 to 14 is implemented.

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