Delay-locked loop circuit, clock generator, chip, and electronic device

Abstract

The embodiment of the invention discloses a delay-locked loop circuit, a clock generator, a chip and electronic equipment, and belongs to the technical field of integrated circuits. The delay-locked loop circuit includes: a digital control circuit for transmitting a first adjustment code adapted to adjust the number of delay units in a coarse adjustment phase, and determining whether to adjust the first adjustment code based on a first feedback signal; in the fine adjustment stage, a third adjustment code suitable for adjusting the delay attribute parameter of the delay unit is sent, and whether the third adjustment code is adjusted or not is determined based on the second feedback signal; in the locking phase, transmitting a second adjustment code suitable for adjusting the control voltage of the delay unit, and determining whether to adjust the second adjustment code based on the third feedback signal; and the phase detection unit is used for sending the first feedback signal, the second feedback signal and the third feedback signal to the digital control circuit. A hybrid circuit of digital design and analog design is provided, high-precision clock phase adjustment is achieved, and an output clock in a wide frequency range can also be achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and more particularly to a delay locked loop (DLL) circuit, a clock generator, a chip, and an electronic device. Background Art

[0002] The DLL circuit is a synchronization circuit widely used in integrated circuits, mainly used to synchronize clock signals to ensure the accuracy and stability of data transmission.

[0003] With the continuous development of VLSI technology and the continuous increase in clock frequencies, the impact of clock signal synchronization on data transmission has become increasingly sensitive. At the same time, different parts of the system have different clock frequency requirements. Therefore, the requirements for DLL efficiency, stability, accuracy, reusability, and applicability to a wide clock frequency range are also constantly increasing. Summary of the Invention

[0004] The present invention provides a DLL circuit, a clock generator, a chip and an electronic device, which are helpful to improve the accuracy of clock phase adjustment.

[0005] The technical solutions of the embodiments of the present invention are as follows:

[0006] A DLL circuit includes a voltage-controlled delay line unit, a phase detection unit, and a digital control circuit, wherein the voltage-controlled delay line unit includes a plurality of delay units;

[0007] The digital control circuit is configured to, in a coarse adjustment phase, send a first adjustment code suitable for adjusting the number of delay cells to the voltage-controlled delay line unit, and determine whether to adjust the first adjustment code based on a first feedback signal, wherein the first feedback signal represents a delay state after the number of delay cells is adjusted; in a fine adjustment phase following the coarse adjustment phase, send a third adjustment code suitable for adjusting a delay attribute parameter of the delay cell to the voltage-controlled delay line unit, and determine whether to adjust the third adjustment code based on a second feedback signal, wherein the second feedback signal represents a delay state after the delay attribute parameter is adjusted; and in a locking phase following the fine adjustment phase, send a second adjustment code suitable for adjusting a control voltage of the delay cell to the voltage-controlled delay line unit, and determine whether to adjust the second adjustment code based on a third feedback signal, wherein the third feedback signal represents a delay state after the control voltage is adjusted;

[0008] The phase detection unit is used to send the first feedback signal to the digital control circuit in the coarse adjustment stage; send the second feedback signal to the digital control circuit in the fine adjustment stage; and send the third feedback signal to the digital control circuit in the locking stage.

[0009] In one embodiment, the digital control circuit comprises:

[0010] a state machine unit, configured to execute the conversion among the coarse adjustment phase, the fine adjustment phase, and the locking phase;

[0011] An interface circuit, configured to receive a first configuration value, a second configuration value, and a third configuration value;

[0012] The digital control circuit is configured to determine whether to adjust the first adjustment code based on a comparison result between the first feedback signal and the first configuration value; determine an adjustment speed of the third adjustment code based on the second configuration value; and determine whether to adjust the second adjustment code based on a comparison result between the third feedback signal and the third configuration value.

[0013] In one embodiment, the delay unit includes:

[0014] A first regulating unit, comprising a plurality of buffers connected in parallel between the input and output ends of the delay unit;

[0015] The second regulating unit includes a plurality of capacitors connected in parallel between the output terminal of the delay unit and the ground terminal.

[0016] In one embodiment, the delay attribute parameter includes at least one of the following:

[0017] Number of buffers; capacitance value of capacitors; number of capacitors.

[0018] In one embodiment, the digital control circuit comprises:

[0019] A first adjustment code generating circuit is configured to generate the first adjustment code based on at least one of the frequency and phase target values ​​of a reference clock; when the first feedback signal indicates that the actual phase difference of the output clock relative to the reference clock is greater than the phase target value and the absolute value of the difference between the actual phase difference and the phase target value is greater than a predetermined threshold, adjust the first adjustment code to indicate a reduction in the number of delay units; when the first feedback signal indicates that the actual phase difference of the output clock relative to the reference clock is less than the phase target value and the absolute value of the difference between the actual phase difference and the phase target value is greater than the predetermined threshold, adjust the first adjustment code to increase the number of delay units; when the first feedback signal indicates that the absolute value of the difference between the actual phase difference and the phase target value is less than the predetermined threshold, lock the first adjustment code.

[0020] In one embodiment, the digital control circuit comprises:

[0021] The third adjustment code generating circuit is configured to generate a third adjustment code having a minimum value within a preset range of the third adjustment code; when the second feedback signal indicates that the actual phase difference of the output clock relative to the reference clock is less than the phase target value, increase the third adjustment code by a predetermined step size within the preset range to increase the delay attribute parameter until the second feedback signal changes to indicate that the actual phase difference of the output clock relative to the reference clock is greater than or equal to the phase target value, thereby locking the third adjustment code; or, generate a third adjustment code having a maximum value within the preset range of the third adjustment code; when the second feedback signal indicates that the actual phase difference of the output clock relative to the reference clock is greater than the phase target value, decrease the third adjustment code by a predetermined step size within the preset range to decrease the delay attribute parameter until the second feedback signal changes to indicate that the actual phase difference of the output clock relative to the reference clock is less than or equal to the phase target value, thereby locking the third adjustment code.

[0022] In one embodiment, the digital control circuit comprises:

[0023] The second adjustment code generating circuit is configured to generate the second adjustment code based on the current delay state sent by the phase detection unit at the start time of the locking phase; adjust the second adjustment code to increase the control voltage when the number of third feedback signals indicating that the actual phase difference of the output clock relative to the reference clock is less than the phase target value within a predetermined time of the locking phase is positively skewed compared to the number of third feedback signals indicating that the actual phase difference of the output clock relative to the reference clock is greater than the phase target value within the predetermined time, and the offset is greater than a predetermined threshold; adjust the second adjustment code to decrease the control voltage when the number of third feedback signals indicating that the actual phase difference of the output clock relative to the reference clock is greater than the phase target value within the predetermined time is positively skewed compared to the number of third feedback signals indicating that the actual phase difference of the output clock relative to the reference clock is less than the phase target value within the predetermined time, and the offset is greater than a predetermined threshold; and lock the second adjustment code when the number of third feedback signals indicating that the actual phase difference of the output clock relative to the reference clock is less than the phase target value within the predetermined time is evenly distributed compared to the number of third feedback signals indicating that the actual phase difference of the output clock relative to the reference clock is greater than the phase target value within the predetermined time.

[0024] In one embodiment, the digital control circuit comprises:

[0025] A timeout alarm circuit is used to issue an alarm instruction when at least one of the following conditions is met;

[0026] When the first adjustment code cannot be locked within the first predetermined time in the coarse adjustment stage;

[0027] When the third adjustment code cannot be locked within a second predetermined time in the fine adjustment stage;

[0028] During the third predetermined time in the locking stage, the second adjustment code cannot be locked.

[0029] In one embodiment, the digital control circuit comprises:

[0030] An over-threshold alarm circuit is used to issue an alarm instruction when at least one of the following conditions is met;

[0031] When the first adjustment code exceeds a preset first threshold;

[0032] When the third adjustment code exceeds a preset second threshold;

[0033] When the second adjustment code exceeds a preset third threshold.

[0034] In one embodiment, it includes:

[0035] A plurality of output taps for providing equally spaced output clocks within a phase range of 0 degrees to 360 degrees;

[0036] The delay state represented by the first feedback signal is determined based on the output clock provided by the 0-degree output tap, the output clock provided by the 180-degree output tap, and the output clock provided by the 360-degree output tap; the delay state represented by the second feedback signal is determined based on the output clock provided by the 0-degree output tap and the output clock provided by the 360-degree output tap; the delay state represented by the third feedback signal is determined by at least two output clocks provided by at least two output taps of the multiple output taps, wherein the at least two output taps include the 0-degree output tap.

[0037] A clock generator comprises any one of the above-mentioned DLL circuits.

[0038] A chip comprises any one of the above-mentioned DLL circuits.

[0039] An electronic device comprises the chip described above.

[0040] As can be seen from the above technical solution, in an embodiment of the present invention, the digital control circuit is configured to, during a coarse adjustment phase, send a first adjustment code to the voltage-controlled delay line unit, suitable for adjusting the number of delay cells; during a fine adjustment phase, send a third adjustment code to the voltage-controlled delay line unit, suitable for adjusting the delay property parameters of the delay cells; during a lock phase, send a second adjustment code to the voltage-controlled delay line unit, suitable for adjusting the control voltage of the delay cells; determine whether to adjust the first adjustment code based on a first feedback signal; determine whether to adjust the third adjustment code based on a second feedback signal; and determine whether to adjust the second adjustment code based on a third feedback signal. Thus, the embodiment of the present invention proposes a DLL circuit based on a hybrid digital and analog design. By integrating a state machine into the digital control circuit, various types of parameters in the analog portion can be adjusted in stages, thereby achieving high-precision clock phase adjustment. Furthermore, in the embodiment of the present invention, the various adjustment codes are fully refined, enabling an output clock with a wider frequency range. Furthermore, the digital control circuit in the embodiment of the present invention can provide software configuration and interface circuitry, enabling flexible software configuration and real-time monitoring of the DLL circuit, thereby improving the robustness of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is an exemplary schematic diagram of a DLL circuit in the related art.

[0042] Figure 2 is an exemplary block diagram of a DLL circuit according to an embodiment of the present invention.

[0043] Figure 3 is a schematic diagram of a VCDL unit according to an embodiment of the present invention.

[0044] Figure 4 is a schematic diagram of a delay unit according to an embodiment of the present invention.

[0045] Figure 5 is an exemplary block diagram of a digital control circuit according to an embodiment of the present invention.

[0046] Figure 6 is an exemplary diagram of a state machine according to an embodiment of the present invention. DETAILED DESCRIPTION

[0047] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings.

[0048] For the sake of brevity and intuitiveness in description, the solution of the present invention is explained below by describing several representative implementations. A large number of details in the implementations are only used to help understand the solution of the present invention. However, it is obvious that the technical solution of the present invention may not be limited to these details when implemented. In order to avoid unnecessarily obscuring the solution of the present invention, some implementations are not described in detail, but only a framework is given. Hereinafter, "including" means "including but not limited to", and "according to..." means "at least according to..., but not limited to only according to...". Due to the language habits of Chinese, when the number of a component is not specifically specified below, it means that the component can be one or more, or can be understood as at least one.

[0049] Figure 1 FIG. 1 is an exemplary schematic diagram of a DLL circuit in the related art. Figure 1 As shown, the DLL circuit mainly includes four-stage delay units (each stage delay unit is marked with a triangle), a phase detector PD and a low-pass filter LPF. The four-stage delay units are connected in series on the clock signal path, and the clock signal CK in Entering the first delay unit generates a first delay signal CK1, the first delay signal CK1 enters the second delay unit to generate a second delay signal CK2, the second delay signal CK2 enters the third delay unit to generate a third delay signal CK3, the third delay signal CK3 enters the fourth delay unit to generate a fourth delay signal CK4, the fourth delay signal CK4 and the clock signal CK in The control voltage V of the four-stage delay unit is generated by the phase detector PD and the low-pass filter LPF. cont , thereby realizing the clock signal CK in and the phase of the fourth delayed signal CK4.

[0050] Figure 1 The DLL circuit shown is an analog loop that outputs a control voltage V through a phase detector PD combined with a low-pass filter LPF. cont Directly controlling the delay line composed of four delay units has poor integral non-linearity (INL) and differential non-linearity (DNL). The delay of the delay line can only be controlled by the control voltage V cont Control, the supported frequency range is small, the stability design of the analog loop is more complicated, and the reusability of different processes is weak.

[0051] In Figure 1 In the related art, which is a typical example, DLL circuits are implemented using analog design, resulting in low testability, controllability, and operational efficiency. Furthermore, due to the complexity of analog design, the frequency range of the DLL circuit's output clock is relatively narrow. Furthermore, due to the lack of a software interface, the DLL circuit's debugging and repair capabilities are limited. Furthermore, DLL circuits implemented using analog design also suffer from low reusability.

[0052] In an embodiment of the present invention, a DLL circuit based on a hybrid digital and analog design is proposed. By integrating a state machine into the digital control circuit, various parameters in the analog portion can be adjusted in stages, achieving high-precision clock phase adjustment. Furthermore, in this embodiment of the present invention, by fully refining the various adjustment codes based on a trade-off between circuit area and output results, a wider frequency range of output clocks can be achieved.

[0053] The above disclosure details the technical defects in the related art, the causes of these defects, and the analytical process for overcoming them. In reality, the understanding of these technical defects is not common knowledge in the field, but rather a novel discovery made by the inventors during their research. Furthermore, the tracing of the causes of these defects and the analytical process for overcoming them are the result of gradual analysis conducted by the inventors during their actual research and are not common knowledge in the field.

[0054] Figure 2 1 is an exemplary module diagram of a DLL circuit according to an embodiment of the present invention. Figure 2 As shown, the DLL circuit includes a voltage controlled delay line (VCDL) unit, a phase detection unit, and a digital control circuit, wherein the VCDL unit includes multiple delay units.

[0055] The VCDL unit belongs to the analog circuit. Each delay unit in the VCDL unit has the same structure and produces the same delay to the input signal. By adjusting the delay time of the VCDL unit, the phase of the clock signal output by the DLL circuit can be precisely controlled. The control voltage (refer to Figure 1 V in cont ) controls the delay of the delay cell. Different control voltages will result in different delays in the VCDL cell. Furthermore, the number of delay cells in the VCDL cell can also affect the delay of the VCDL cell. Furthermore, delay attribute parameters such as the capacitance value of the delay cells in the VCDL cell can also affect the delay of the VCDL cell.

[0056] Figure 3 Schematic diagram of a VCDL unit according to an embodiment of the present invention. The VCDL unit includes N stages of delay cells, each having the same circuit structure. The power supply terminal of each delay cell is coupled to a voltage source, and the input terminal of the subsequent delay cell in two adjacent delay cells is coupled to the output terminal of the previous delay cell. In the exemplary embodiment, N ≥ 2, and the number N is adjustable.

[0057] In one embodiment, a delay unit includes: a first adjustment unit including a plurality of buffers connected in parallel between an input and an output of the delay unit; and a second adjustment unit including a plurality of capacitors connected in parallel between an output of the delay unit and a ground terminal. In one embodiment, the delay property parameters of the delay unit include at least one of the following: the number of buffers; the capacitance of the capacitors; or the number of capacitors.

[0058] Figure 4 Schematic diagram of a delay unit according to an embodiment of the present invention. The delay unit includes a first adjustment unit 1211 and a second adjustment unit 1212. The first adjustment unit 1211 includes an input terminal ( Figure 4 Left side) and output side ( Figure 4 The second adjustment unit 1212 includes a plurality of capacitors C connected in parallel between the output end of the delay unit and the ground end, and the number and capacitance value of the capacitors C are adjustable.

[0059] The above exemplary descriptions describe the specific structures of the VCDL unit and the delay unit. Those skilled in the art will appreciate that such descriptions are merely exemplary and are not intended to limit the scope of protection of the embodiments of the present invention.

[0060] Phase detection units can be implemented as either digital or analog designs, depending on the application requirements. Digital designs offer advantages such as precise control, temperature and process stability, and flexibility, but may introduce latency and design complexity. Analog designs offer advantages such as smooth response, low latency, and simplicity, but are susceptible to temperature and process variations, and can be complex to design and debug.

[0061] The digital control circuit is a digital circuit. The digital control circuit is configured to, during a coarse adjustment phase, send a first adjustment code suitable for adjusting the number of delay cells to the VCDL unit, wherein the VCDL unit adjusts the number of delay cells in response to the first adjustment code. The phase detection unit is configured to, during a coarse adjustment phase, send a first feedback signal to the digital control circuit that represents the delay state after the number of delay cells is adjusted. The digital control circuit is further configured to, during the coarse adjustment phase, determine whether to adjust the first adjustment code based on the first feedback signal, wherein, upon determining to adjust the first adjustment code, the digital control circuit further sends the adjusted first adjustment code to the VCDL unit, wherein the VCDL unit further adjusts the number of delay cells in response to the adjusted first adjustment code; and upon determining not to adjust the first adjustment code, the digital control circuit locks the current first adjustment code and enters a fine adjustment phase.

[0062] The digital control circuit is further configured to, during a fine-tuning phase, send a third adjustment code suitable for adjusting the delay property parameters of the delay unit to the VCDL unit, wherein the VCDL unit adjusts the delay property parameters of the delay unit in response to the third adjustment code. The phase detection unit is configured to, during the fine-tuning phase, send a second feedback signal to the digital control circuit that represents the delay state after the delay property parameters are adjusted. The digital control circuit is further configured to, during the fine-tuning phase, determine whether to adjust the third adjustment code based on the second feedback signal. If the third adjustment code is determined to be adjusted, the digital control circuit further sends the adjusted third adjustment code to the VCDL unit, and the VCDL unit further adjusts the delay property parameters of the delay unit in response to the adjusted third adjustment code. If the third adjustment code is determined not to be adjusted, the digital control circuit locks the current third adjustment code and enters a locking phase.

[0063] The digital control circuit is further configured to, during the locking phase, send a second adjustment code suitable for adjusting the control voltage of the delay cell to the VCDL unit, wherein the VCDL unit adjusts the control voltage of the delay cell in response to the second adjustment code (the control voltage is applicable to each delay cell). The phase detection unit is configured to, during the locking phase, send a third feedback signal to the digital control circuit that represents the delay state after the control voltage is adjusted. The digital control circuit is further configured to, during the locking phase, determine whether to adjust the second adjustment code based on the third feedback signal. If it is determined that the second adjustment code is to be adjusted, the digital control circuit further sends the adjusted second adjustment code to the VCDL unit, and the VCDL unit further adjusts the control voltage in response to the adjusted second adjustment code. If it is determined that the second adjustment code is not to be adjusted, the current second adjustment code is locked and the locking phase is exited.

[0064] In one embodiment, the locked first adjustment code, second adjustment code, and third adjustment code are associated with the target frequency and phase values ​​of the reference clock during the adjustment process and stored in a storage medium (e.g., a memory coupled to the DLL circuit). When the target frequency and phase values ​​of the reference clock subsequently input to the DLL circuit match the target frequency and phase values ​​of the reference clock stored in the storage medium, the number of delay cells, delay attribute parameters, and control voltage in the VCDL unit are rapidly adjusted using the associated first adjustment code, second adjustment code, and third adjustment code stored in the storage medium, thereby achieving rapid adjustment of the DLL circuit.

[0065] As can be seen, the phase adjustment process of the embodiments of the present invention includes a coarse adjustment stage, a fine adjustment stage, and a locking stage. The main function of the coarse adjustment stage is to quickly adjust the phase of the clock signal output by the DLL circuit, so that the phase difference quickly approaches the target value. The main function of the fine adjustment stage is to further accurately adjust the phase of the clock signal output by the DLL circuit based on the coarse adjustment, so that the phase difference achieves a higher accuracy. The locking stage performs a final adjustment on the line delay to ensure that the output clock signal of the DLL is stable with high precision. Therefore, the embodiments of the present invention, based on the staged adjustment, can gradually improve the phase adjustment accuracy and stability of the DLL, ultimately achieving high-precision, high-efficiency, and high-stability clock phase adjustment.

[0066] The first, second, and third feedback signals sent by the phase detection unit to the digital control circuit respectively indicate whether the loop line delay is too fast or too slow in different stages. If the first, second, and third feedback signals respectively indicate that the loop line delay is too fast, the digital control circuit accordingly adjusts the first adjustment code, the third adjustment code, and the second adjustment code to reduce the loop line delay in the corresponding stage. Conversely, if the first, second, and third feedback signals respectively indicate that the loop line delay is too slow, the digital control circuit accordingly adjusts the first adjustment code, the third adjustment code, and the second adjustment code to increase the loop line delay in the corresponding stage.

[0067] Figure 5 is an exemplary module diagram of a digital control circuit according to an embodiment of the present invention. Figure 5 In the embodiment, the digital control circuit includes: a state machine unit for executing transitions between a coarse adjustment phase, a fine adjustment phase, and a lock phase; an interface circuit for receiving a first configuration value, a second configuration value, and a third configuration value; wherein the digital control circuit is configured to determine whether to adjust the first adjustment code based on a comparison result between a first feedback signal and the first configuration value; determine a speed for adjusting the third adjustment code based on the second configuration value; and determine whether to adjust the second adjustment code based on a comparison result between a third feedback signal and the third configuration value. The first configuration value, the second configuration value, and the third configuration value may be user-set thresholds.

[0068] For example, the first configuration value can be a threshold of the absolute value of the difference between the actual phase difference and the phase target value; the second configuration value can be an adjustment step of the third adjustment code (for example, when the adjustment accuracy is higher, the second configuration value is usually smaller, and when the adjustment accuracy is lower, the second configuration value is usually larger); the third configuration value can be a threshold of the offset degree.

[0069] In one embodiment, a first threshold value for the first adjustment code, a second threshold value for the third adjustment code, and a third threshold value for the second adjustment code set by the user may also be received via the interface circuit. When the first adjustment code exceeds the first threshold value, the third adjustment code exceeds the second threshold value, or the second adjustment code exceeds the third threshold value during the adjustment process, an alarm mechanism is triggered. The first, second, and third threshold values ​​may be user-provided via the interface circuit. Furthermore, the first, second, and third threshold values ​​are preferably adjustable.

[0070] In one embodiment, a first predetermined time, a second predetermined time, and a third predetermined time set by a user may also be received via the interface circuit. If the first adjustment code cannot be locked within the first predetermined time, the third adjustment code cannot be locked within the second predetermined time, and the second adjustment code cannot be locked within the third predetermined time, an alarm mechanism is triggered. The first predetermined time, the second predetermined time, and the third predetermined time may be set by the user via the interface circuit. Furthermore, the first predetermined time, the second predetermined time, and the third predetermined time are preferably adjustable.

[0071] exist Figure 5In the embodiment, the digital control circuit includes a first adjustment code generation circuit. The first adjustment code generation circuit is configured to generate a first adjustment code based on at least one of a frequency and a phase target value of a reference clock; when a first feedback signal provided by a phase detection unit indicates that an actual phase difference of an output clock relative to a reference clock is greater than a phase target value and an absolute value of a difference between the actual phase difference and the phase target value is greater than a predetermined threshold value (e.g., a predetermined threshold value determined by a first configuration value), the first adjustment code is adjusted to indicate a reduction in the number of delay units; when the first feedback signal indicates that an actual phase difference of an output clock relative to a reference clock is less than a phase target value and an absolute value of a difference between the actual phase difference and the phase target value is greater than a predetermined threshold value, the first adjustment code is adjusted to indicate an increase in the number of delay units; and when the first feedback signal indicates that an absolute value of a difference between the actual phase difference and the phase target value is less than a predetermined threshold value, the first adjustment code is locked.

[0072] The frequency of the reference clock can affect the first adjustment code. The lower the reference clock frequency, the more delay cells should be used. Conversely, the higher the reference clock frequency, the fewer delay cells should be used. Therefore, when the reference clock frequency is lower, the first adjustment code corresponding to that frequency should increase the number of delay cells in the VLDC unit, resulting in a greater linear delay. Conversely, when the reference clock frequency is higher, the first adjustment code corresponding to that frequency should decrease the number of delay cells in the VLDC unit, resulting in a smaller linear delay.

[0073] The phase target value refers to the ideal phase difference of the output clock relative to the reference clock. The phase target value can also influence the first adjustment code. Based on the phase target value, a phase error can be determined. The larger the phase error, the more delay units should be used. Conversely, the smaller the phase error, the fewer delay units should be used. The phase detection unit measures the actual phase difference Δφ, where the actual phase difference Δφ is the true phase difference of the output clock relative to the reference clock. The phase detection unit compares the actual phase difference Δφ with the phase target value φtarget to calculate the phase error Δφerror (Δφerror = Δφ-φtarget), which is carried in the first feedback signal. After receiving the first feedback signal carrying the phase error, the digital control circuit adjusts the first adjustment code. Specifically, as the phase error Δφerror increases, the number of delay units in the VLDC unit should increase under the influence of the first adjustment code corresponding to the phase target value calculated for the phase error Δφerror, thereby increasing the linear delay generated by the VLDC unit. On the contrary, when the phase error Δφerror is smaller, under the action of the first adjustment code corresponding to the phase target value calculated for the phase error Δφerror, the number of delay units in the VLDC unit should be smaller, and the linear delay generated by the VLDC unit will be smaller.

[0074] For example, the value of the first adjustment code and the corresponding number of delay units can be preset based on different phase error ranges. For example, when |Δφerror|>180 degrees, the first adjustment code is 7 (corresponding to 10 delay units); when 90 degrees <|Δφerror|≤180 degrees, the first adjustment code is 5 (corresponding to 8 delay units); when 45 degrees <|Δφerror|≤90 degrees, the first adjustment code is 3 (corresponding to 6 delay units); and when |Δφerror|≤45 degrees, the first adjustment code is 1 (corresponding to 4 delay units). Assuming the phase target value is 45 degrees and the actual phase difference Δφ detected by the phase detection unit is 270 degrees, then the phase error Δφerror = 270 degrees - 45 degrees = 225 degrees. Based on the above correspondence, the first adjustment code is adjusted to 7 and the number of delay units is adjusted to 10.

[0075] The above describes the coarse adjustment stage by taking specific numerical values ​​as an example. Those skilled in the art will appreciate that such description is merely exemplary and is not intended to limit the scope of protection of the embodiments of the present invention.

[0076] During the coarse adjustment phase, the line delay can be quickly and roughly adjusted by adjusting the number of delay cells in the analog circuit. Once the coarse adjustment is complete, the lock signal is released, locking the first adjustment code. Furthermore, the first adjustment code can be directly configured by software via the interface circuit. Therefore, this embodiment of the present invention also offers the advantages of strong debugging capabilities and high flexibility.

[0077] exist Figure 5 In the embodiment, the digital control circuit further includes a third adjustment code generation circuit. The third adjustment code generation circuit is configured to generate a third adjustment code having a minimum value within a preset range of the third adjustment code. When the second feedback signal indicates that the actual phase difference of the output clock relative to the reference clock is less than the phase target value, the third adjustment code is increased by a predetermined step size (e.g., a second configuration value) within the preset range to increase the delay attribute parameter until the second feedback signal changes to indicate that the actual phase difference of the output clock relative to the reference clock is greater than or equal to the phase target value, thereby locking the third adjustment code. Alternatively, the third adjustment code is generated having a maximum value within the preset range of the third adjustment code. When the second feedback signal indicates that the actual phase difference of the output clock relative to the reference clock is greater than the phase target value, the third adjustment code is decreased by a predetermined step size within the preset range to decrease the delay attribute parameter until the second feedback signal changes to indicate that the actual phase difference of the output clock relative to the reference clock is less than or equal to the phase target value, thereby locking the third adjustment code. It can be seen that the main function of the fine adjustment stage is to accurately adjust the line delay to ensure a more accurate phase relationship between the output clock and the reference clock.

[0078] For example, when the actual phase difference is smaller than the phase target value, the third adjustment code is added to increase the capacitance value of the capacitor in the delay unit, thereby increasing the line delay generated by the VLDC unit; when the actual phase difference is larger than the phase target value, the third adjustment code is reduced to reduce the capacitance value of the capacitor in the delay unit, thereby reducing the line delay generated by the VLDC unit.

[0079] exist Figure 5 In the embodiment, the digital control circuit further includes a second adjustment code generation circuit. The second adjustment code generation circuit is configured to generate a second adjustment code based on a current delay state sent by the phase detection unit at the start of a locking phase; adjust the second adjustment code to increase the control voltage when the number of third feedback signals representing that the actual phase difference of the output clock relative to the reference clock is less than the phase target value within a predetermined time of the locking phase is positively skewed compared to the number of third feedback signals representing that the actual phase difference of the output clock relative to the reference clock is greater than the phase target value within a predetermined time, and the offset is greater than a predetermined threshold (e.g., a third configuration value); adjust the second adjustment code to decrease the control voltage when the number of third feedback signals representing that the actual phase difference of the output clock relative to the reference clock is greater than the phase target value within a predetermined time is positively skewed compared to the number of third feedback signals representing that the actual phase difference of the output clock relative to the reference clock is less than the phase target value within a predetermined time, and the offset is greater than a predetermined threshold; and lock the second adjustment code when the number of third feedback signals representing that the actual phase difference of the output clock relative to the reference clock is less than the phase target value within a predetermined time is uniformly distributed compared to the number of third feedback signals representing that the actual phase difference of the output clock relative to the reference clock is greater than the phase target value within a predetermined time.

[0080] During the locking phase, the phase detection unit continuously compares the reference clock and the output clock to continuously generate the actual phase difference and continuously outputs a real-time third feedback signal. When the number of third feedback signals indicating that the actual phase difference is less than the phase target value within a predetermined period is evenly distributed compared to the number of third feedback signals indicating that the actual phase difference is greater than the phase target value within a predetermined period, the actual phase difference is deemed to have stabilized. This indicates that the current second adjustment code is stable and the phase relationship between the output clock and the reference clock has been locked. Therefore, the digital control circuit releases the lock signal and locks the second adjustment code.

[0081] As can be seen, during the locking phase, the phase relationship between the output clock and the reference clock is maintained. Real-time monitoring and adjustment during the locking phase ensure that the DLL circuit's output clock remains stable over time, improving circuit stability.

[0082] In one embodiment, the digital control circuit includes a timeout alarm circuit. The timeout alarm circuit is configured to issue an alarm instruction when at least one of the following conditions is met: (1) when the first adjustment code cannot be locked within a first predetermined time in the coarse adjustment phase; (2) when the third adjustment code cannot be locked within a second predetermined time in the fine adjustment phase; (3) when the second adjustment code cannot be locked within a third predetermined time in the locking phase.

[0083] In one embodiment, the digital control circuit includes an over-threshold alarm circuit. The over-threshold alarm circuit is configured to issue an alarm instruction when at least one of the following conditions is met: (1) when the first adjustment code exceeds a preset first threshold; (2) when the third adjustment code exceeds a preset second threshold; (3) when the second adjustment code exceeds a preset third threshold.

[0084] Therefore, based on the timeout alarm circuit and the over-threshold alarm circuit, multiple types of alarms can be implemented to improve the safety of the DLL circuit.

[0085] Figure 2 The DLL circuit can output multi-phase clocks or single-phase clocks. When outputting a single-phase clock, a specific output tap is selected from the tap group (for example, when the target phase difference is zero, the output tap of 0 degrees is usually selected) to output a single clock. When outputting multi-phase clocks, multiple output taps are selected that are evenly distributed at different positions in the delay line to output multiple clocks, ensuring that the phases of the output multiple clocks are evenly distributed.

[0086] In one embodiment, the DLL circuit includes a plurality of output taps for providing equally spaced output clocks within a phase range of 0 degrees to 360 degrees.

[0087] Example (1): The delay state represented by the first feedback signal is determined based on the output clock provided by the 0-degree output tap, the output clock provided by the 180-degree output tap, and the output clock provided by the 360-degree output tap.

[0088] During the coarse adjustment phase, the phase detection unit compares the output clocks provided by the 0-degree, 180-degree, and 360-degree output taps (referred to as phase points). This allows for rapid detection of large phase differences, facilitating subsequent rapid delay adjustment. Furthermore, selecting the 180-degree and 360-degree phase taps to generate the first feedback signal during the coarse adjustment phase avoids harmonic lock. The 0-degree phase point serves as the starting point of the reference clock; the 180-degree phase point serves as the midpoint of the reference clock; and the 360-degree phase point serves as the ending point of the reference clock.

[0089] The phase detection unit compares the 0-degree phase point with the 360-degree phase point and the 0-degree phase point with the 180-degree phase point, and executes the following control logic respectively:

[0090] (1) If the 180-degree phase point lags more than 180 degrees relative to the 0-degree phase point, and the 360-degree phase point lags more than 360 degrees relative to the 0-degree phase point, it indicates that the clock signal delay is too large. In this case, the first feedback signal generated by the phase detection unit indicates that the delay needs to be reduced. The digital control circuit adjusts the first adjustment code accordingly to reduce the delay.

[0091] (2) If the 180-degree phase point leads the 0-degree phase point, and the 360-degree phase point leads the 0-degree phase point, it indicates that the clock signal delay is too small. In this case, the first feedback signal generated by the phase detection unit indicates that the delay needs to be increased. The digital control circuit adjusts the first adjustment code accordingly to increase the delay.

[0092] (3) Otherwise, the first feedback signal generated by the phase detection unit indicates that the delay is appropriate. Accordingly, the digital control circuit exits the coarse adjustment phase and enters the fine adjustment phase.

[0093] Example (2): The delay state represented by the second feedback signal is determined based on the output clock provided by the output tap of 0 degrees and the output clock provided by the output tap of 360 degrees.

[0094] During the fine-tuning phase, the phase detection unit compares the output clock signals provided by the 0-degree and 360-degree output taps and executes the following control logic respectively:

[0095] (1) If the 360-degree phase point lags behind the 0-degree phase point, it indicates that the clock signal delay is too large. In this case, the second feedback signal generated by the phase detection unit indicates that the delay needs to be reduced. The digital control circuit adjusts the third adjustment code accordingly to reduce the delay.

[0096] (2) If the 360-degree phase point is ahead of 0 degrees, it indicates that the clock signal delay is too small. In this case, the second feedback signal generated by the phase detection unit indicates that the delay needs to be increased. The digital control circuit adjusts the third adjustment code accordingly to increase the delay.

[0097] (3) If the 360-degree phase point coincides with the 0-degree phase point, it indicates that the clock signal delay is appropriate. The second feedback signal generated by the phase detection unit indicates that the delay is appropriate. Accordingly, the digital control circuit exits the fine-tuning phase and enters the locking phase.

[0098] Example (3): The delay state represented by the third feedback signal is determined by at least two output clocks provided by at least two output taps among a plurality of output taps, wherein the at least two output taps include an output tap of 0 degrees.

[0099] In the locking phase, the phase detection unit can ensure that the phase relationship between all output clocks and the reference clock is stable based on the output clock signals provided by the 0-degree output tap and at least one other output tap.

[0100] For example, assume that at least one output tap is a 45-degree output tap. Theoretically, the phase difference between the 0-degree phase point and the 45-degree phase point should be 45 degrees. The phase detection unit compares the output clock signals provided by the 0-degree and 45-degree output taps in real time and generates a third feedback signal in real time. Among them: (1) If the 45-degree phase point lags behind the 0-degree phase point by more than 45 degrees within the predetermined time, it indicates that the delay of the clock signal is too large. At this time, the third feedback signal indicates that the delay needs to be reduced (usually the control voltage needs to be reduced); (2) If the 45-degree phase point lags behind the 0-degree phase point by less than 45 degrees within the predetermined time, it indicates that the delay of the clock signal is too small. At this time, the third feedback signal indicates that the delay needs to be increased (usually the control voltage needs to be increased); (3) If the 45-degree phase point lags behind the 0-degree phase point by 45 degrees within the predetermined time, the third feedback signal is not generated.

[0101] Within a predetermined time period: when the number of third feedback signals indicating a need for delay reduction presents a positively skewed distribution compared to the number of third feedback signals indicating a need for delay increase, and the offset is greater than a predetermined threshold, the digital control circuit adjusts the second adjustment code to reduce the control voltage of the delay unit; when the number of third feedback signals indicating a need for delay increase presents a positively skewed distribution compared to the number of third feedback signals indicating a need for delay reduction, and the offset is greater than the predetermined threshold, the digital control circuit adjusts the second adjustment code to increase the control voltage of the delay unit; when the number of third feedback signals indicating a need for delay increase and the number of third feedback signals indicating a need for delay reduction are evenly distributed, the digital control circuit locks the second adjustment code and exits the locking stage.

[0102] Figure 6 is an exemplary schematic diagram of a state machine according to an embodiment of the present invention. Figure 6 As shown, the state machine includes:

[0103] State 1: "Idle state" means the DLL circuit is not turned on. At this time, the counter and logic control inside the DLL circuit will be in the off state, reducing circuit power consumption.

[0104] State 2: "Stable State"—The DLL circuit is enabled. The digital control circuit in the DLL circuit activates the counter circuit. After a software-configurable clock cycle, the digital control circuit sequentially issues control signals to enable the analog portion of the DLL circuit (e.g., the VCDL unit and phase detection unit). This state allows the analog low-dropout linear regulator to stabilize.

[0105] State 3: "Coarse Adjustment Phase"—At this point, the digital control circuit will match different reference clock frequencies to send corresponding first adjustment codes to the VCDL unit to adjust the number of delay cells. Generally, the lower the reference clock frequency, the greater the number of delay cells under the action of the first adjustment code corresponding to the reference clock frequency, and the greater the line delay generated by the VCDL unit. Conversely, the higher the reference clock frequency, the fewer the number of delay cells under the action of the first adjustment code corresponding to the reference clock frequency, and the smaller the line delay generated by the VCDL unit. State 3 implements the first adjustment phase in the state machine, achieving fast and coarse adjustment of the line delay. After coarse adjustment is completed, the lock signal is released to lock the first adjustment code. Alternatively, the first adjustment code can also be directly configured by software.

[0106] State 4: "Fine-tuning stage", at this time, the digital control circuit sends the third adjustment code used to adjust the capacitor in the delay unit to the VCDL unit, and adjusts the third adjustment code based on the clock taps of the 0-degree clock and the 360-degree clock, and finally pulls out all the phase-shifted clocks so that these clocks are evenly offset to the same phase.

[0107] For example: First, the digital control circuit sends the minimum value of the third adjustment code to the VCDL unit (software configurable). Then, based on the minimum value of the third adjustment code, the capacitor in the delay unit in the VCDL unit is set to have a minimum capacitance value. Next, the phase detection unit compares the output clock signals provided by the 0-degree and 360-degree output taps, and finds that the 360-degree phase point is ahead of 0 degrees, indicating that the delay of the clock signal is too small. The second feedback signal sent by the phase detection unit to the digital control circuit indicates that the delay needs to be increased. The digital control circuit adjusts the third adjustment code (for example, plus 1) in a predetermined step size to increase the delay. Similarly, when the 360-degree phase point coincides with the 0-degree phase point, it means that the clock signal delay is appropriate, and the third adjustment code is locked at this time.

[0108] State five: "Locked phase". In this state, the digital control circuit will adjust the second adjustment code in combination with the third feedback signal fed back by the phase detection unit. The VLDC unit adjusts the control voltage of the delay unit based on the second adjustment code to adjust the line delay. In this state, the digital control circuit and the analog circuit cooperate with each other. The digital control circuit adjusts the second adjustment code based on the third feedback signal, and the phase detection unit generates a third feedback signal by comparing the output clock with the reference voltage. When the third feedback signal tends to be stable, for example, the information representing the line delay being too fast and the line delay being too slow is evenly distributed in the third feedback signal, and the error range configured by the circuit through software is reached, the digital control circuit will release the lock signal and lock the current second adjustment code.

[0109] In summary, the embodiments of the present invention implement the digital control circuit portion of the DLL using a hybrid digital-analog approach, achieving higher operating efficiency and output accuracy compared to traditional analog DLL circuits. Furthermore, the digital control circuit can provide software configuration and interface circuitry, enabling flexible software configuration and real-time monitoring of the DLL circuit, thereby improving the circuit's robustness. The digital control circuit also provides control logic, feedback logic, and error alarm logic for the analog circuit, thereby enhancing the DLL circuit's operating efficiency. Furthermore, the digital control circuit subdivides multiple types of line delay adjustment codes, improving the accuracy of the output clock phase and extending the clock frequency range. Furthermore, the embodiments of the present invention, based on a state machine, perform phased adjustment of the clock phase offset, thereby improving operating efficiency. The embodiments of the present invention also assist the analog circuit in parameter adjustment, taking into account the analog circuit's operating conditions and providing the analog circuit with sufficient circuit stabilization time, thereby improving circuit robustness and operational stability.

[0110] The DLL circuit according to the embodiments of the present invention can be applied to various electronic devices for clock synchronization, phase adjustment, signal processing, etc. For example, it can be applied to various types of processors (such as CPUs, GPUs, GPGPUs, MCUs, or DSPs, etc.), memories, field programmable gate arrays (FPGAs), communication devices, digital televisions and video processing devices, audio processing devices, network devices, embedded systems, or measurement devices.

[0111] In an exemplary embodiment, embodiments of the present invention further provide a clock generator comprising the DLL circuit described in any of the above embodiments. In an exemplary embodiment, a chip comprising the DLL circuit described in any of the above embodiments is further provided. In an exemplary embodiment, an electronic device comprising the chip described above is further provided.

[0112] It should be noted that the division of the above modules is only for the convenience of describing the functional division. In actual implementation, one module can be implemented by multiple modules, and the functions of multiple modules can also be implemented by the same module. These modules can be located in the same device or in different devices.

[0113] The hardware modules in each embodiment can be implemented mechanically or electronically. For example, a hardware module may include specially designed permanent circuits or logic devices (such as dedicated processors, such as FPGAs or ASICs) to perform specific operations. For example, specific operations can be performed in various types of chips (for example, artificial intelligence chips). The hardware module may also include programmable logic devices or circuits (such as general-purpose processors or other programmable processors) temporarily configured by software to perform specific operations. As for whether to implement the hardware module mechanically, or using a dedicated permanent circuit, or using a temporarily configured circuit (such as configured by software), it can be decided based on cost and time considerations.

[0114] In this document, "schematic" means "serving as an example, instance or illustration", and any diagram or embodiment described as "schematic" in this document should not be interpreted as a more preferred or more advantageous technical solution. In order to keep the drawings simple, each figure only schematically shows the parts related to the present invention, and does not represent its actual structure as a product. In addition, in order to keep the drawings simple and easy to understand, in some figures, only one of the components with the same structure or function is schematically drawn, or only one of them is marked. In this document, "one" does not mean that the number of relevant parts of the present invention is limited to "only one", and "one" does not mean excluding the situation where the number of relevant parts of the present invention is "more than one". In this document, "upper", "lower", "front", "back", "left", "right", "inside", "outside" and the like are only used to indicate the relative positional relationship between the relevant parts, rather than to limit the absolute positions of these relevant parts.

[0115] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the scope of protection of the present invention.

Claims

1. A delay-locked loop circuit, characterized in that: It includes a voltage-controlled delay line unit, a phase detection unit and a digital control circuit, wherein the voltage-controlled delay line unit includes a plurality of delay units; The digital control circuit is configured to, in a coarse adjustment phase, send a first adjustment code suitable for adjusting the number of delay cells to the voltage-controlled delay line unit, and determine whether to adjust the first adjustment code based on a first feedback signal, wherein the first feedback signal represents a delay state after the number of delay cells is adjusted; and, in a fine adjustment phase subsequent to the coarse adjustment phase, send a third adjustment code suitable for adjusting a delay attribute parameter of the delay cell to the voltage-controlled delay line unit, and determine whether to adjust the third adjustment code based on a second feedback signal, wherein the second feedback signal represents a delay state after the delay attribute parameter is adjusted; In a locking phase after the fine adjustment phase, a second adjustment code suitable for adjusting a control voltage of the delay unit is sent to the voltage-controlled delay line unit, and whether to adjust the second adjustment code is determined based on a third feedback signal, wherein the third feedback signal represents a delay state after adjusting the control voltage; The phase detection unit is used to send the first feedback signal to the digital control circuit in the coarse adjustment stage; send the second feedback signal to the digital control circuit in the fine adjustment stage; and send the third feedback signal to the digital control circuit in the locking stage.

2. The delay locked loop circuit according to claim 1, wherein: The digital control circuit comprises: a state machine unit, configured to execute the conversion among the coarse adjustment phase, the fine adjustment phase, and the locking phase; An interface circuit, configured to receive a first configuration value, a second configuration value, and a third configuration value; The digital control circuit is configured to determine whether to adjust the first adjustment code based on a comparison result between the first feedback signal and the first configuration value; determine an adjustment speed of the third adjustment code based on the second configuration value; and determine whether to adjust the second adjustment code based on a comparison result between the third feedback signal and the third configuration value.

3. The delay locked loop circuit according to claim 1, wherein: The delay unit comprises: A first regulating unit, comprising a plurality of buffers connected in parallel between the input and output ends of the delay unit; The second regulating unit includes a plurality of capacitors connected in parallel between the output terminal of the delay unit and the ground terminal.

4. The delay locked loop circuit according to claim 3, wherein: The delay attribute parameter includes at least one of the following: Number of buffers; capacitance value of capacitors; number of capacitors.

5. The delay locked loop circuit according to claim 1, wherein: The digital control circuit comprises: A first adjustment code generating circuit is configured to generate the first adjustment code based on at least one of the frequency and phase target values ​​of a reference clock; when the first feedback signal indicates that the actual phase difference of the output clock relative to the reference clock is greater than the phase target value and the absolute value of the difference between the actual phase difference and the phase target value is greater than a predetermined threshold, adjust the first adjustment code to indicate a reduction in the number of delay units; when the first feedback signal indicates that the actual phase difference of the output clock relative to the reference clock is less than the phase target value and the absolute value of the difference between the actual phase difference and the phase target value is greater than the predetermined threshold, adjust the first adjustment code to increase the number of delay units; when the first feedback signal indicates that the absolute value of the difference between the actual phase difference and the phase target value is less than the predetermined threshold, lock the first adjustment code.

6. The delay-locked loop circuit according to claim 1, wherein: The digital control circuit comprises: The third adjustment code generating circuit is configured to generate a third adjustment code having a minimum value within a preset range of the third adjustment code; when the second feedback signal indicates that the actual phase difference of the output clock relative to the reference clock is less than the phase target value, increase the third adjustment code by a predetermined step size within the preset range to increase the delay attribute parameter until the second feedback signal changes to indicate that the actual phase difference of the output clock relative to the reference clock is greater than or equal to the phase target value, thereby locking the third adjustment code; or, generate a third adjustment code having a maximum value within the preset range of the third adjustment code; when the second feedback signal indicates that the actual phase difference of the output clock relative to the reference clock is greater than the phase target value, decrease the third adjustment code by a predetermined step size within the preset range to decrease the delay attribute parameter until the second feedback signal changes to indicate that the actual phase difference of the output clock relative to the reference clock is less than or equal to the phase target value, thereby locking the third adjustment code.

7. The delay locked loop circuit according to claim 1, wherein: The digital control circuit comprises: The second adjustment code generating circuit is configured to generate the second adjustment code based on the current delay state sent by the phase detection unit at the start time of the locking phase; adjust the second adjustment code to increase the control voltage when the number of third feedback signals indicating that the actual phase difference of the output clock relative to the reference clock is less than the phase target value within a predetermined time of the locking phase is positively skewed compared to the number of third feedback signals indicating that the actual phase difference of the output clock relative to the reference clock is greater than the phase target value within the predetermined time, and the offset is greater than a predetermined threshold; adjust the second adjustment code to decrease the control voltage when the number of third feedback signals indicating that the actual phase difference of the output clock relative to the reference clock is greater than the phase target value within the predetermined time is positively skewed compared to the number of third feedback signals indicating that the actual phase difference of the output clock relative to the reference clock is less than the phase target value within the predetermined time, and the offset is greater than a predetermined threshold; and lock the second adjustment code when the number of third feedback signals indicating that the actual phase difference of the output clock relative to the reference clock is less than the phase target value within the predetermined time is evenly distributed compared to the number of third feedback signals indicating that the actual phase difference of the output clock relative to the reference clock is greater than the phase target value within the predetermined time.

8. The delay-locked loop circuit according to any one of claims 1 to 7, wherein: The digital control circuit comprises: A timeout alarm circuit is used to issue an alarm instruction when at least one of the following conditions is met; When the first adjustment code cannot be locked within the first predetermined time in the coarse adjustment stage; When the third adjustment code cannot be locked within a second predetermined time in the fine adjustment stage; During the third predetermined time in the locking stage, the second adjustment code cannot be locked.

9. The delay-locked loop circuit according to any one of claims 1 to 7, wherein: The digital control circuit comprises: An over-threshold alarm circuit is used to issue an alarm instruction when at least one of the following conditions is met; When the first adjustment code exceeds a preset first threshold; When the third adjustment code exceeds a preset second threshold; When the second adjustment code exceeds a preset third threshold.

10. The delay-locked loop circuit according to any one of claims 1 to 7, wherein: include: A plurality of output taps for providing equally spaced output clocks within a phase range of 0 degrees to 360 degrees; The delay state represented by the first feedback signal is determined based on the output clock provided by the 0-degree output tap, the output clock provided by the 180-degree output tap, and the output clock provided by the 360-degree output tap; The delay state represented by the second feedback signal is determined based on the output clock provided by the 0-degree output tap and the output clock provided by the 360-degree output tap; The delay state represented by the third feedback signal is determined by at least two output clocks provided by at least two output taps of the plurality of output taps, wherein the at least two output taps include an output tap of 0 degrees.

11. A clock generator, characterized in that: The method comprises the delay locked loop circuit according to any one of claims 1 to 10.

12. A chip, characterized in that: The method comprises the delay locked loop circuit according to any one of claims 1 to 10.

13. An electronic device, characterized in that: Comprising the chip as claimed in claim 12.

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