Preparation method of HBT (Heterojunction Bipolar Transistor) material for reducing secondary passivation of intermediate layer and HBT material
By dividing the n-GaAs:Si layer into multiple thin layers and annealing them in situ, the problem of secondary passivation of the intermediate layer of HBT material is solved, the carrier concentration is increased and the resistance is reduced, thereby improving the overall performance of HBT material.
Patent Information
- Application Number
- CN202510472767.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-16
- Publication Date
- 2025-11-04
AI Technical Summary
The C doping concentration in the intermediate layer of existing HBT materials is low, and in-situ annealing leads to secondary hydrogen passivation, which affects the carrier concentration and resistance. Existing annealing processes are inefficient or have poor effects.
The n-GaAs:Si layer was divided into multiple thin layers. After the growth of each layer, in-situ annealing was performed in a hydrogen atmosphere to prevent H elements from combining with C elements in the p-GaAs:C intermediate base region. The growth conditions of each layer were controlled by MOCVD to increase carrier concentration and reduce resistance.
This improved the carrier concentration and carrier activation rate of the HBT material, reduced the base region resistance and loss, and enhanced the overall performance of the material.
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Figure CN120897544A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application relates to the technical field of heterojunction bipolar transistor materials, and particularly relates to a preparation method of HBT material with reduced secondary passivation of an intermediate layer and the HBT material. BACKGROUND
[0002] Heterojunction bipolar transistor (HBT) based on III-V semiconductor material is one of the most promising devices in future high-speed applications, and has been widely used in power amplifiers of mobile phones and base stations. Compared with Si bipolar devices, metal semiconductor field effect transistors (MESFETs) or high electron mobility transistors (HEMTs), HBT has unique advantages in performance. Compared with AlGaAs / GaAs HBT, InGaP / GaAs HBT has larger valence band discontinuity, smaller conduction band discontinuity, fewer recombination centers (no DX center problem), higher electron saturation drift velocity and better etching selectivity. After doping C in the base region, the doping concentration is increased, and better reliability is achieved.
[0003] The existing HBT structure is generally npn-type GaAs / GaInP base material, that is, the C-doped p-type GaAs (denoted as p-GaAs:C) base layer is located in the intermediate layer, and the C-doped p-type GaAs material is easily hydrogen passivated in the MOCVD (new type of vapor phase epitaxial growth) process, resulting in inconsistent impurity concentration and hole concentration. The reason is that the existence of C-H bond weakens the acceptor impurity effect of C element, and the actual doping concentration is reduced. High-temperature (generally about 600 DEG C) annealing is required to remove H element. Annealing generally adopts in-situ annealing process, which can anneal and then grow the subsequent structure after the growth of the p-GaAs:C intermediate base layer, or can grow all the structures and then anneal in-situ, but both have disadvantages. Annealing and then growing the subsequent structure after the growth of the p-GaAs:C intermediate base layer can break the C-H bond, but in the growth process of the subsequent other epitaxial layer, H element will continue to combine with C, causing secondary passivation of the layer; when annealing in-situ after growing all the structures, the material has been grown, the n-type emitter region on the p-type base region of the intermediate layer blocks H, and cannot dissociate H element, which will reduce the annealing efficiency. SUMMARY
[0004] In view of the problem that the C doping concentration of the intermediate layer p-type GaAs base region is low and in-situ annealing causes secondary hydrogen passivation, the application provides a preparation method of HBT material for reducing secondary passivation of an intermediate layer and HBT material, wherein the n-GaAs:Si layer is divided into multiple thin layers, in-situ annealing is performed under a hydrogen atmosphere after the growth of each thin layer, penetration of H elements into the combination of C elements in the p-GaAs:C intermediate base region is effectively blocked, and the comprehensive performance of the HBT material is improved.
[0005] To solve the above technical problems, the technical scheme provided by the application is: In a first aspect, the application provides a preparation method of HBT material for reducing secondary passivation of an intermediate layer, comprising the following steps: S1, using the MOCVD method, growing a p-GaAs:C intermediate base region layer and an n-GaInP:Si emitter region layer on the surface of an n-GaAs collector region layer in sequence; S2, growing multiple n-GaAs:Si thin layers on the surface of the n-GaInP:Si emitter region layer, and performing in-situ annealing under a hydrogen atmosphere after the growth of each n-GaAs:Si thin layer; S3, continuing to grow an n-GaAs / InGaAs contact layer to obtain the HBT material.
[0006] Compared with the prior art, the preparation method of HBT material for reducing secondary passivation of an intermediate layer provided by the application divides the n-GaAs:Si layer into multiple thin layers after growing a p-GaAs:C intermediate base region layer and an n-GaInP:Si emitter region layer on the surface of an n-GaAs collector region layer in sequence, performs in-situ annealing under a hydrogen atmosphere after the growth of each thin layer, and then grows the remaining layers. In this way, penetration of H elements into the combination of C elements in the p-GaAs:C intermediate base region is effectively blocked, the purpose of reducing secondary hydrogen passivation of the intermediate layer is achieved, the carrier concentration is improved, the resistance and loss of the base region are reduced, the comprehensive performance of the HBT material is improved, and the application has high market value.
[0007] It should be noted that in the application, p-GaAs:C represents C-doped p-type GaAs, n-GaInP:Si represents Si-doped n-type GaInP, and n-GaAs:Si represents Si-doped n-type GaAs.
[0008] Preferably, the preparation method of HBT material for reducing secondary passivation of an intermediate layer comprises the following steps: S1, using the MOCVD method, growing an n-GaAs collector region layer and a p-GaAs:C intermediate base region layer on the surface of a GaAs substrate under a hydrogen atmosphere; supplying phosphine, growing an n-GaInP:Si emitter region layer on the surface of the p-GaAs:C intermediate base region layer; S2, supplying arsine, growing 2-10 n-GaAs:Si thin layers on the surface of the n-GaInP:Si emitter region layer; after the growth of each n-GaAs:Si thin layer, stopping the supply of arsine, and performing in-situ annealing in a hydrogen atmosphere; S3, supplying arsine, growing an n-GaAs:Si emitter contact layer and an InGaAs:Si contact layer in sequence on the surface of the n-GaAs:Si thin layer, to obtain an HBT material.
[0009] Preferably, in the MOCVD method, the V-group source includes arsine or phosphine, the In source includes TMIn, the Ga source includes at least one of TMGa or TEGa, and the n-type doping source includes at least one of SiH4, Si2H6 or DETe.
[0010] Further preferably, in S1, the growth temperature of the n-GaAs collector region layer is 600-700°C (more preferably 620-680°C), and the growth pressure is 50-100 mbar.
[0011] Preferably, in S1, the thickness of the n-GaAs collector region layer is 1000-2000 nm.
[0012] Preferably, in S1, the growth temperature of the p-GaAs:C intermediate base region layer is 500-650°C (further preferably 550-600°C), and the growth pressure is 50-100 mbar.
[0013] Preferably, in S1, the doping concentration of C in the p-GaAs:C intermediate base region layer is 1×10 19 cm -3 ~8×10 19 cm -3 .
[0014] Preferably, in S1, the thickness of the p-GaAs:C intermediate base region layer is 50-150 nm.
[0015] Preferably, in S1, the growth temperature of the n-GaInP:Si emitter region layer is 550-700°C (further preferably 580-650°C), and the growth pressure is 50-100 mbar.
[0016] Preferably, in S1, the mass content of In in the n-GaInP:Si emitter region layer is 45-50% (more preferably 48.4%).
[0017] The application limits the mass content of In element in the n-GaInP:Si emitting region layer, and can increase the matching degree with the GaAs lattice.
[0018] Preferably, in S1, the thickness of the n-GaInP:Si emitting region layer is 20-100 nm.
[0019] Preferably, in S2, the growth temperature of the n-GaAs:Si thin layer is 550-700 (further preferably 580-650) ℃ and is not higher than the growth temperature of the n-GaInP:Si emitting region layer, the growth pressure is 50-100 mbar, and the flow rate of arsine is 10-200 sccm.
[0020] Preferably, in S2, the doping concentration of Si in the n-GaAs:Si thin layer is 1×10 18 cm -3 -8×10 18 cm -3 .
[0021] Preferably, in S2, the thickness of a single n-GaAs:Si thin layer is 5-20 nm.
[0022] Preferably, in S2, the temperature of the in-situ annealing is 550-700 (further preferably 580-650) ℃, and the annealing time is 1-10 (further preferably 1-5) min.
[0023] Further preferably, in S2, the temperature of the in-situ annealing is the same as the growth temperature of the n-GaAs:Si thin layer.
[0024] The temperature of the in-situ annealing is the same as the growth temperature of the n-GaAs:Si thin layer, which can avoid the time required for temperature rising and falling, shorten the exposure time of the epitaxial wafer in a hydrogen atmosphere, and avoid too poor crystal quality.
[0025] Preferably, in S2, the number of layers of the n-GaAs:Si thin layer is 2-4.
[0026] The application limits the number of layers of the n-GaAs:Si thin layer, which can better balance the relationship between the annealing efficiency and the crystal quality.
[0027] Preferably, in S3, the growth temperature of the n-GaAs / InGaAs contact layer is 500-650 ℃ and is not higher than the temperature of the in-situ annealing, the growth pressure is 50-100 mbar, and the flow rate of arsine is 10-200 sccm.
[0028] Further preferably, in S3, the doping concentration of Si in the n-GaAs:Si emitter contact layer is 1*10 18 cm -3 ~8*10 18 cm -3
[0029] Further preferably, in S3, the mass content of In in the InGaAs:Si contact layer is 40% to 55%.
[0030] Preferably, in S3, the thickness of the n-GaAs / InGaAs contact layer is 100nm to 300nm.
[0031] The present application can better meet the performance design requirements of HBT materials by controlling the growth conditions of each layer, and further improve the comprehensive performance of HBT materials. The present application has found through a large number of experiments that if the growth temperature of each layer is too high, the C doping amount will decrease; if the growth temperature of each layer is too low, the crystal quality will be poor; if the growth pressure of each layer is too high, the impurity elements of HBT materials will increase, causing the crystal quality to be poor; and if the growth pressure of each layer is too low, the utilization rate of raw materials will decrease.
[0032] In a second aspect, the present application provides an HBT material prepared by the preparation method of the HBT material with reduced secondary passivation of the intermediate layer.
[0033] Preferably, the HBT material comprises, from bottom to top, a GaAs substrate, an n-GaAs collector region layer, a p-GaAs:C intermediate base region layer, an n-GaInP:Si emitter region layer, 2-11 n-GaAs:Si thin layers, an n-GaAs:Si emitter contact layer, and an InGaAs:Si contact layer.
[0034] The specific implementation data show that the HBT material provided by the present application has a higher carrier concentration, a carrier activation rate of more than 95%, a very small H passivation effect, a greatly reduced resistance and loss of the base region, and improved comprehensive performance of the HBT material. BRIEF DESCRIPTION OF DRAWINGS
[0035] Figure 1 Figure 1 is a preparation flowchart of the HBT material with reduced secondary passivation of the intermediate layer in the embodiments of the present application; Figure 2 Figure 2 is a structure diagram of the HBT material in the embodiments of the present application; in the figure, 1 represents a GaAs substrate, 2 represents an n-GaAs collector region layer, 3 represents a p-GaAs:C intermediate base region layer, 4 represents an n-GaInP:Si emitter region layer, 5 represents an n-GaAs:Si thin layer, 6 represents an n-GaAs:Si emitter contact layer, and 7 represents an InGaAs:Si contact layer. DETAILED DESCRIPTION
[0036] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to examples. It should be understood that the specific examples described herein are only used to explain the present application and not intended to limit the present application.
[0037] In the present application, the materials not specifically described are commercially available products.
[0038] Example 1 The present example provides a preparation method of HBT material with reduced secondary passivation of intermediate layer (see Figure 1 and Figure 2 ), which comprises the following steps: Sa, using MOCVD method, GaAs substrate 1 is put into the reaction chamber, heated to 650℃ under hydrogen atmosphere, vacuumed to 80mbar, n-GaAs collector region layer 2 is grown on the surface of GaAs substrate 1, and SiH4 is used as the doping source; the thickness of n-GaAs collector region layer 2 is 1500nm.
[0039] Sb, at 580℃, 80mbar, p-GaAs:C intermediate base region layer 3 is continuously grown on the surface of n-GaAs collector region layer 2, and CCl4 is used as the doping source; the thickness of p-GaAs:C intermediate base region layer 3 is 100nm, and the doping concentration of C is 4.5×10 19 cm -3 .
[0040] Sc, the V group source is switched to phosphine, n-GaInP:Si emitter region layer 4 is grown on the surface of p-GaAs:C intermediate base region layer 3 at 620℃, 80mbar, and SiH4 is used as the doping source; the thickness of n-GaInP:Si emitter region layer 4 is 60nm, and the mass content of In element is 48.4%.
[0041] Sd, the V group source is switched to arsine, the flow rate of arsine is 100sccm, n-GaAs:Si thin layer 5 is grown on the surface of n-GaInP:Si emitter region layer 4 at 600℃, 80mbar, and Si2H6 is used as the doping source; the thickness of n-GaAs:Si thin layer 5 is 12nm, and the doping concentration of Si is 4.6×10 18 cm -3 ; Stop supplying arsine, in-situ annealing is carried out at 600℃ under hydrogen atmosphere, and the heat preservation time is 3min; Se, step Sd is repeated once, and one layer of n-GaAs:Si thin layer is continuously grown on the surface of n-GaAs:Si thin layer; Sf, continue to supply arsine, the flow rate of arsine is 100 sccm, grow n-GaAs:Si emitter contact layer 6 on the surface of n-GaAs:Si thin layer 5 at 580°C and 80 mbar, the doping source used is Si2H6; the doping concentration of Si in n-GaAs:Si emitter contact layer 6 is 4.4 x 1019cm-3. 18 cm -3 .
[0042] Sg, continue to grow InGaAs:Si contact layer 7 on the surface of n-GaAs:Si emitter contact layer 6 at 580°C and 80 mbar, the doping source used is DETe; the mass content of In in InGaAs:Si contact layer 7 is 48%.
[0043] n-GaAs:Si emitter contact layer 6 and InGaAs:Si contact layer 7 jointly form n-GaAs / InGaAs contact layer, the thickness of n-GaAs / InGaAs contact layer is 200 nm, and HBT material is obtained.
[0044] Example 2 The embodiment provides a preparation method of HBT material with reduced secondary passivation of an intermediate layer (see Figure 1 and Figure 2 ), which comprises the following steps: Sa, using MOCVD method, place GaAs substrate 1 into a reaction chamber, grow n-GaAs collector layer 2 on the surface of GaAs substrate 1 under hydrogen atmosphere, temperature is raised to 620°C, and pressure is reduced to 50 mbar, the doping source used is Si2H6; the thickness of n-GaAs collector layer 2 is 1000 nm.
[0045] Sb, continue to grow p-GaAs:C intermediate base layer 3 on the surface of n-GaAs collector layer 2 at 530°C and 50 mbar, the doping source used is CBr4; the thickness of p-GaAs:C intermediate base layer 3 is 50 nm, and the doping concentration of C is 8 x 1019cm-3. 19 cm -3 .
[0046] Sc, switch the V group source to phosphine, grow n-GaInP:Si emitter layer 4 on the surface of p-GaAs:C intermediate base layer 3 at 570°C and 50 mbar, the doping source used is Si2H6; the thickness of n-GaInP:Si emitter layer 4 is 30 nm, and the mass content of In is 48.2%.
[0047] Sd, the V-group source is switched to arsine, the flow rate of arsine is 20sccm, n-GaAs:Si thin layer 5 is grown on the surface of n-GaInP:Si emitter region layer 4 at 560℃ and 50mbar, the doping source used is SiH4; the thickness of n-GaAs:Si thin layer 5 is 6nm, and the doping concentration of Si is 8×1018cm-3. 18 -3 The supply of arsine is stopped, in-situ annealing is performed at 560℃ under hydrogen atmosphere, and the temperature is kept for 5min; Se, step Sd is repeated twice, and two layers of n-GaAs:Si thin layer are continuously grown on the surface of n-GaAs:Si thin layer; Sf, the supply of arsine is continued, the flow rate of arsine is 20sccm, n-GaAs:Si emitter region contact layer 6 is grown on the surface of n-GaAs:Si thin layer 5 at 520℃ and 50mbar, the doping source used is SiH4; the doping concentration of Si in n-GaAs:Si emitter region contact layer 6 is 8×1018cm-3. 18 -3
[0048] Sg, InGaAs:Si contact layer 7 is continuously grown on the surface of n-GaAs:Si emitter region contact layer 6 at 520℃ and 50mbar, the doping source used is Si2H6; the mass content of In element in InGaAs:Si contact layer 7 is 42%.
[0049] n-GaAs:Si emitter region contact layer 6 and InGaAs:Si contact layer 7 jointly form n-GaAs / InGaAs contact layer, the thickness of n-GaAs / InGaAs contact layer is 100nm, and HBT material is obtained.
[0050] Example 3 The embodiment provides a preparation method of HBT material with reduced secondary passivation of an intermediate layer (see Figure 1 and Figure 2 ), which comprises the following steps: Sa, by using the MOCVD method, the GaAs substrate 1 is placed into a reaction chamber, the temperature is raised to 680℃ under hydrogen atmosphere, the pressure is reduced to 100mbar, and n-GaAs collector region layer 2 is grown on the surface of the GaAs substrate 1, the doping sources used are SiH4 and Si2H6; the thickness of n-GaAs collector region layer 2 is 2000nm.
[0051] Sb, continue to grow p-GaAs:C intermediate base region layer 3 on the surface of n-GaAs collector region layer 2 at 630℃, 100mbar, using CCl4 and CBr4 as the doping source; the thickness of p-GaAs:C intermediate base region layer 3 is 150nm, and the doping concentration of C is 1.2×1019cm-3. 19 cm -3 .
[0052] Sc, switch the V group source to phosphine, grow n-GaInP:Si emitter region layer 4 on the surface of p-GaAs:C intermediate base region layer 3 at 690℃, 100mbar, using SiH4 and Si2H6 as the doping source; the thickness of n-GaInP:Si emitter region layer 4 is 100nm, and the mass content of In element is 48.6%.
[0053] Sd, switch the V group source to arsine, grow n-GaAs:Si thin layer 5 on the surface of n-GaInP:Si emitter region layer 4 at 680℃, 100mbar, using SiH4 as the doping source; the thickness of n-GaAs:Si thin layer 5 is 20nm, and the doping concentration of Si is 1.1×1019cm-3. 18 cm -3 ; Stop supplying arsine, perform in-situ annealing at 680℃ under hydrogen atmosphere for 2min; Se, repeat step Sd for 4 times to continue growing 4 layers of n-GaAs:Si thin layer on the surface of n-GaAs:Si thin layer; Sf, continue to supply arsine, grow n-GaAs:Si emitter contact layer 6 on the surface of n-GaAs:Si thin layer 5 at 650℃, 100mbar, using SiH4 as the doping source; the doping concentration of Si in n-GaAs:Si emitter contact layer 6 is 1.2×1019cm-3. 18 cm -3 .
[0054] Sg, continue to grow InGaAs:Si contact layer 7 on the surface of n-GaAs:Si emitter contact layer 6 at 640℃, 100mbar, using SiH4 as the doping source; the mass content of In element in InGaAs:Si contact layer 7 is 54%.
[0055] n-GaAs:Si emitter contact layer 6 and InGaAs:Si contact layer 7 jointly form n-GaAs / InGaAs contact layer, the thickness of n-GaAs / InGaAs contact layer is 300nm, and HBT material is obtained.
[0056] Example 4 This example provides a preparation method of HBT material with reduced secondary passivation of intermediate layer, which is similar to example 1, except that the holding time of in-situ annealing in Sd is 1 min, and the number of repeating step Sd in Se is 6 times. The rest conditions are the same as those in example 1, and will not be repeated here.
[0057] Example 5 This example provides a preparation method of HBT material with reduced secondary passivation of intermediate layer, which is similar to example 1, except that the holding time of in-situ annealing in Sd is 1 min, and the number of repeating step Sd in Se is 9 times. The rest conditions are the same as those in example 1, and will not be repeated here.
[0058] Comparative Example 1 This comparative example provides a preparation method of HBT material, which is similar to example 1, except that the in-situ annealing in Sd is omitted, and Se is also omitted. Specifically, the following steps are included: Sa~Sc, which are the same as Sa~Sc in example 1, and will not be repeated here.
[0059] Sd, the group V source is switched to arsine, and the flow rate of arsine is 100 sccm. n-GaAs: Si thin layer 5 is grown on the surface of n-GaInP: Si emitter region layer 4 at 600°C and 80 mbar, and the doping source used is Si2H6; the thickness of n-GaAs: Si thin layer 5 is 12 nm, and the doping concentration of Si is 4.6 x 1019 cm-3. 18 cm -3 .
[0060] Se~Sf, which are the same as Sf~Sg in example 1, and will not be repeated here.
[0061] Comparative Example 2 This comparative example provides a preparation method of HBT material, which is similar to example 1, except that step Se is omitted. The rest conditions are the same as those in example 1, and will not be repeated here.
[0062] Comparative Example 3 This comparative example provides a preparation method of HBT material, which is similar to example 1, except that the in-situ annealing in Sd is omitted, Se is also omitted, and after growing InGaAs: Si contact layer 7, in-situ annealing is performed again. Specifically, the following steps are included: Sa~Se, which are the same as Sa~Se in comparative example 1, and will not be repeated here.
[0063] Sf, InGaAs: Si contact layer 7 is continuously grown on the surface of n-GaAs: Si emitter region contact layer 6 at 580°C and 80 mbar, and the doping source used is DETe; the mass content of In element in InGaAs: Si contact layer 7 is 48%.
[0064] The n-GaAs:Si emission region contact layer 6 and the InGaAs:Si contact layer 7 jointly form an n-GaAs / InGaAs contact layer, and the thickness of the n-GaAs / InGaAs contact layer is 200 nm.
[0065] Sg, in-situ annealing at 580 DEG C under a hydrogen atmosphere for 3 min, to obtain an HBT material.
[0066] Verification test The carrier concentration of the HBT material prepared in Examples 1-5 and Comparative Examples 1-3 is indirectly characterized by using a contact resistance tester, which can avoid the influence of the n-type doped layer on the test results, and has higher accuracy than direct carrier test methods such as CV.
[0067] The test procedure is as follows: (1) The HBT material is etched using a selective etching liquid (phosphoric acid, hydrogen peroxide and water in a volume ratio of 15:10:100) until the n-GaInP:Si emission region layer is exposed, and then removed and tested for sheet resistance using a contact resistance tester, and the value is recorded as R1; (2) The etched HBT material is again placed in the selective etching liquid and etched until the n-GaInP:Si emission region layer is completely removed and the p-GaAs:C intermediate base layer is exposed; the HBT material is removed and placed in a rapid annealing furnace and annealed at 490 DEG C-600 DEG C for 1 min-6 min, at which time the H element in the twice-etched HBT material has been theoretically completely removed, and the sheet resistance is again tested using a contact resistance tester, and the value is recorded as R2; (3) The ratio of R2 to R1 is the carrier activation rate of the doped C element. The test results are shown in Table 1.
[0068] Table 1: Carrier performance of HBT materials of examples and comparative examples
[0069] The above only describes the preferred embodiments of the present application and is not intended to limit the present application, and any modification, equivalent replacement or improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A method for preparing an HBT material with reduced secondary passivation of the interlayer, characterized in that, The method comprises the following steps: S1, growing a p-GaAs:C intermediate base region layer and an n-GaInP:Si emission region layer on the surface of the n-GaAs collector region layer by using MOCVD method; S2, growing a plurality of n-GaAs:Si thin layers on the surface of the n-GaInP:Si emission region layer, and performing in-situ annealing under a hydrogen atmosphere after the growth of each n-GaAs:Si thin layer; S3, continuously growing an n-GaAs / InGaAs contact layer to obtain an HBT material.
2. The method of claim 1 wherein the HBT material is a mid-layer, secondary- passivated HBT material. The method for preparing the HBT material with reduced secondary passivation of the intermediate layer comprises the following steps: S1, growing an n-GaAs collector region layer and a p-GaAs:C intermediate base region layer on the surface of a GaAs substrate under a hydrogen atmosphere by using MOCVD method; supplying phosphine to grow an n-GaInP:Si emission region layer on the surface of the p-GaAs:C intermediate base region layer; S2, supplying arsine to grow 2-10 n-GaAs:Si thin layers on the surface of the n-GaInP:Si emission region layer; stopping the supply of arsine after the growth of each n-GaAs:Si thin layer and performing in-situ annealing under a hydrogen atmosphere; S3, supplying arsine to grow an n-GaAs:Si emission region contact layer and an InGaAs:Si contact layer on the surface of the n-GaAs:Si thin layer in sequence to obtain an HBT material.
3. The method for preparing HBT material with reduced secondary passivation of the intermediate layer as described in claim 1 or 2, characterized in that, In S2, the number of the n-GaAs:Si thin layers is 2-4.
4. The method of claim 1 wherein the HBT material is a mid-layer, secondary- passivated HBT material. In S2, the temperature of the in-situ annealing is 550-700°C, and the annealing time is 1-10 min.
5. The method for preparing HBT material with reduced secondary passivation of the intermediate layer as described in claim 1 or 2, characterized in that, In S1, the thickness of the n-GaAs collector region layer is 1000-2000 nm. In S1, the thickness of the p-GaAs:C intermediate base region layer is 50-150 nm. In S1, the thickness of the n-GaInP:Si emission region layer is 20-100 nm. In S2, the thickness of a single n-GaAs:Si thin layer is 5-20 nm. In S3, the thickness of the n-GaAs / InGaAs contact layer is 100-300 nm.
6. The method of claim 2 wherein the HBT material is a mid-layer, secondary- passivated HBT material. In S1, the growth temperature of the n-GaAs collector region layer is 600-700°C, and the growth pressure is 50-100 mbar. In S1, the growth temperature of the p-GaAs:C intermediate base region layer is 500-650°C, and the growth pressure is 50-100 mbar. In S1, the growth temperature of the n-GaInP:Si emission region layer is 550-700°C, and the growth pressure is 50-100 mbar. In S2, the growth temperature of the n-GaAs:Si thin layer is 550-700°C and is not higher than the growth temperature of the n-GaInP:Si emission region layer, and the growth pressure is 50-100 mbar; and the flow rate of the arsine is 10-200 sccm. In S3, the growth temperature of the n-GaAs / InGaAs contact layer is 500-650℃ and is not higher than the temperature of the in-situ annealing, and the growth pressure is 50-100 mbar; the flow rate of arsine is 10-200 sccm.
7. The method of claim 2 wherein the HBT material is a mid-layer, secondary- passivated HBT material. In S1, the C doping concentration in the p-GaAs:C intermediate base layer is 1×10⁻⁶. 19 cm -3 ~8×10 19 cm -3 ; In S1, the mass content of In in the n-GaInP:Si emitter layer is 45-50%. In S2, the doping concentration of Si in the n-GaAs:Si thin layer is 1 x 10 18 cm -3 8 x 10 18 cm -3 In S3, the doping concentration of Si in the n-GaAs:Si emitter contact layer is 1 x 10 18 cm -3 8 x 10 18 cm -3 ; In S3, the mass content of In in the InGaAs:Si contact layer is 40-55%.
8. The method of claim 2, 4 or 6, wherein the HBT material is prepared by the steps of: depositing a first layer of a first conductivity type on a substrate; depositing a second layer of a second conductivity type on the first layer; and depositing a third layer of the first conductivity type on the second layer. In S2, the temperature of the in-situ annealing is the same as the growth temperature of the n-GaAs:Si thin layer.
9. An HBT material, characterized in that, The preparation method of the HBT material with reduced secondary passivation of an intermediate layer is prepared by any one of claims 1-8.
10. The HBT material of claim 9 wherein, The HBT material comprises, from bottom to top, a GaAs substrate, an n-GaAs collector layer, a p-GaAs:C intermediate base layer, an n-GaInP:Si emitter layer, 2-11 n-GaAs:Si thin layers, an n-GaAs:Si emitter contact layer and an InGaAs:Si contact layer.