High-precision self-timekeeping method based on FPGA

Abstract

The invention discloses a high-precision self-timekeeping method based on an FPGA, and relates to the technical field of high-precision time synchronization, and the method comprises the steps: providing a 10MHz system clock through a constant-temperature active crystal oscillator, carrying out the up-sampling of the clock frequency to 200MHz through a phase-locked loop frequency multiplication algorithm, and carrying out the up-sampling of the clock frequency to 200MHz; performing time synchronization on the system by using reliable time data and effective pulse per second signals provided by a satellite module, screening and selecting reference pulse per second, recording reference pulse per second data of at least 30 minutes, monitoring a rising edge of the pulse per second based on a sampling rate of 200MHz, and storing a maximum value of a counter per second to an RAM (Random Access Memory); the high-precision self-timekeeping method based on the FPGA not only can cope with complex environmental conditions, but also can ensure that stable synchronization performance is kept under long-time operation, so that the strict requirement of a modern high-precision time synchronization system on clock precision is met.

Description

Technical Field

[0001] This invention relates to the field of high-precision time synchronization technology, and specifically to a high-precision self-timekeeping method based on FPGA. Background Technology

[0002] In modern high-precision time synchronization systems, clock accuracy is a key factor in ensuring stable system operation. Traditional self-synchronizing techniques typically rely on the stability and periodicity of crystal oscillators, achieving time synchronization by statistically analyzing the crystal oscillator's pulse output frequency.

[0003] However, crystal oscillators are susceptible to frequency shifts due to factors such as temperature variations and aging, causing traditional self-synchronous timing algorithms to fall short of high-precision synchronization requirements. This instability is particularly pronounced during long-term operation or in harsh environments, severely impacting the accuracy of the time synchronization system. While FPGA-based high-frequency sampling techniques attempt to improve time synchronization accuracy, these methods typically rely on adjusting the frequency of a single crystal oscillator, neglecting the complex changes that may occur during long-term operation, such as temperature drift and aging. Therefore, existing self-synchronous timing algorithms still cannot operate stably and continuously under high-precision requirements, especially in environments with significant variations; the accuracy of traditional methods fails to meet the demands of modern high-precision time synchronization systems. Summary of the Invention

[0004] The purpose of this invention is to provide a high-precision self-timekeeping method based on FPGA, thereby solving the problems existing in the prior art.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a high-precision self-timekeeping method based on FPGA, the method comprising:

[0006] A 10MHz system clock is provided by a temperature-controlled active crystal oscillator, and the clock frequency is upsampled to 200MHz using a phase-locked loop frequency multiplication algorithm;

[0007] The system is time-synchronized using reliable time data and valid second pulse signals provided by the satellite module, and reference second pulses are filtered and selected.

[0008] Record at least 30 minutes of reference second pulse data, monitor the rising edge of the second pulse based on a sampling rate of 200MHz, and store the maximum value of the second counter to RAM;

[0009] The recorded reference second pulse data is divided into multiple time periods, and the mean and variance of each time period are calculated separately.

[0010] In the event of a satellite signal interruption, the mean and variance data are read from RAM, and the variable k for the number of output pulses of the analog crystal oscillator is set. Initially, the value of k is the mean of the first time period.

[0011] Compare the variance differences between adjacent time periods. If the difference exceeds a preset threshold, update the value of k to the mean of the corresponding time period; if the difference is below the threshold, maintain the mean of the previous time period.

[0012] A dynamic adaptive adjustment mechanism is introduced to dynamically adjust the adjustment strategy of the analog crystal oscillator output pulse number by analyzing factors such as signal quality and environmental changes in real time, thereby optimizing the accuracy and stability of self-timekeeping.

[0013] By continuously adjusting the value of k, the actual output pulse number of the crystal oscillator is simulated, thereby achieving high-precision self-timekeeping.

[0014] Preferably, the phase-locked loop frequency multiplication algorithm is implemented using a HighCloud IP core, the frequency multiplication factor is 20, and the selection of the frequency multiplication factor is based on the ratio of the FPGA clock frequency to the target high-frequency clock.

[0015] Preferably, the time data provided by the satellite module includes time signals from at least three satellites, wherein the signal quality of each satellite meets a preset signal quality standard, which includes the signal noise figure, the signal phase deviation, and the satellite positioning accuracy.

[0016] Preferably, the reference second pulse signal is selected by filtering signals with high data quality and a large number of satellites. The filtering method adopts a weighted average algorithm, which considers not only the number of satellites when calculating the reference second pulse, but also assigns different weights according to the quality of each satellite signal.

[0017] Preferably, the mean and variance of each time period of the reference second pulse data are calculated based on the rising edge of the pulse measured in real time, wherein the mean is calculated as the arithmetic mean of the maximum value of the counter per second, and the variance is calculated as the average of the sum of squares of the differences between the maximum value of the counter per second and the mean.

[0018] Preferably, the initial value of the variable k for the number of simulated crystal oscillator output pulses is the mean of each time period. In each calculation, the variable k is adjusted according to the variance of the time period. When the variance difference between adjacent time periods exceeds a preset threshold, it indicates that the crystal oscillator frequency fluctuates more violently, and then it is updated to the mean of the current time period. If the variance difference does not exceed the preset threshold, the mean of the previous time period is maintained.

[0019] Preferably, the method further includes a strategy for determining whether to update the number of analog crystal oscillator output pulses by comparing the variance difference between adjacent time periods. The update condition is that the variance difference between adjacent time periods exceeds a set threshold. If the difference exceeds the threshold, the mean of the current time period is used as the new value. If the difference is lower than the threshold, the mean of the previous time period is used.

[0020] Preferably, the satellite signal selection logic optimizes the selection process based on the number of satellites and data quality over multiple time periods, and selects the best signal source by calculating the average quality and number of satellite signals within the current time period and combining historical data.

[0021] Preferably, the satellite signal selection logic prioritizes multiple received satellite signals and selects the satellite data with the most satellites as the reference signal.

[0022] Preferably, the adjustment strategy for the number of output pulses of the simulated crystal oscillator includes recursive analysis based on historical data to predict the trend of crystal oscillator frequency changes in the future time period.

[0023] As can be seen from the above technical solution, the present invention has the following beneficial effects:

[0024] This FPGA-based high-precision self-synchronization method effectively solves the time synchronization accuracy problem caused by insufficient crystal oscillator stability in traditional self-synchronization techniques by introducing a dynamic adaptive adjustment mechanism. Traditional methods typically rely on the stability and periodicity of the crystal oscillator and often ignore the effects of temperature drift and aging on the crystal during long-term operation, leading to a decrease in the accuracy of the time synchronization system. Compared with existing technologies, this invention dynamically adjusts the output pulse number of the simulated crystal oscillator by analyzing factors such as satellite signal quality and environmental changes in real time, thereby accurately simulating the actual output frequency of the crystal oscillator and significantly improving the accuracy and stability of time synchronization. Furthermore, by segmenting the calculation of the mean and variance of the reference second pulse data and using an adaptive adjustment mechanism based on threshold values, the self-synchronization accuracy is further optimized, enabling the system to maintain high-precision synchronization capabilities even under signal interruptions or significant environmental fluctuations. In summary, this invention not only copes with complex environmental conditions but also ensures stable synchronization performance over long-term operation, thus meeting the stringent clock accuracy requirements of modern high-precision time synchronization systems. Attached Figure Description

[0025] Figure 1 This is a flowchart of the method of the present invention. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] like Figure 1 As shown, the present invention provides a technical solution: a high-precision self-timekeeping method based on FPGA, the method comprising:

[0028] A 10MHz system clock is provided by a temperature-controlled active crystal oscillator, and the clock frequency is upsampled to 200MHz using a phase-locked loop frequency multiplication algorithm;

[0029] The system is time-synchronized using reliable time data and valid second pulse signals provided by the satellite module, and reference second pulses are filtered and selected.

[0030] Record at least 30 minutes of reference second pulse data, monitor the rising edge of the second pulse based on a sampling rate of 200MHz, and store the maximum value of the second counter to RAM;

[0031] The recorded reference second pulse data is divided into multiple time periods, and the mean and variance of each time period are calculated separately.

[0032] In the event of a satellite signal interruption, the mean and variance data are read from RAM, and the variable k for the number of output pulses of the analog crystal oscillator is set. Initially, the value of k is the mean of the first time period.

[0033] Compare the variance differences between adjacent time periods. If the difference exceeds a preset threshold, update the value of k to the mean of the corresponding time period; if the difference is below the threshold, maintain the mean of the previous time period.

[0034] A dynamic adaptive adjustment mechanism is introduced to dynamically adjust the adjustment strategy of the analog crystal oscillator output pulse number by analyzing factors such as signal quality and environmental changes in real time, thereby optimizing the accuracy and stability of self-timekeeping.

[0035] By continuously adjusting the value of k, the actual output pulse number of the crystal oscillator is simulated, thereby achieving high-precision self-timekeeping.

[0036] In this embodiment, the system first uses a temperature-controlled active crystal oscillator to generate a stable 10 MHz clock signal, which is then input as the base clock into the field-programmable gate array (FPGA). The clock signal is then frequency-multiplied by an internal phase-locked loop (PLL) circuit, increasing its frequency to 200 MHz, thereby achieving a sampling frequency of 200 million times per second, significantly improving the resolution of time measurement.

[0037] During system operation, the satellite module serves as a reference source for time synchronization. This module outputs accurate time information and a second pulse signal once per second. Upon receiving the rising edge of each second pulse, the system immediately reads the current value of the counter driven by high-frequency sampling and uses it as the timing result for that second. The counter value is recorded once per second and stored in the on-chip random access memory, while also being associated with the corresponding time stamp.

[0038] After receiving a continuous valid second pulse signal for at least thirty minutes, the system divides the collected second-by-second count data into several time periods. Within each time period, statistical analysis is performed on the included second-by-second count values. First, the average value of all data within each period is calculated to obtain the counting benchmark for that period. Then, the deviation of each data point within each period from this average value is calculated, thereby deriving a statistical fluctuation value reflecting stability. All statistical results are stored in memory for later use.

[0039] When the system detects a satellite signal interruption, the self-timekeeping function is activated. The system retrieves previously saved statistical data from memory and first sets an initial parameter for the number of pulses output by the analog crystal oscillator. The initial value of this parameter is set to the average count value of the first time period. During subsequent operation, the system compares the difference between the fluctuation values ​​of two adjacent time periods after each time period. If the difference exceeds a set threshold, it indicates that the system's current timing characteristics may have changed, and the output parameter of the analog crystal oscillator needs to be updated to the average count value of the current time period. If the difference does not exceed the threshold, the previous count parameter remains unchanged.

[0040] To further improve the accuracy of self-timekeeping and the system's adaptability to external disturbances, a dynamic adaptive adjustment mechanism is introduced. This mechanism continuously monitors multiple parameters during operation, including ambient temperature, power supply fluctuations, and signal integrity, and dynamically optimizes the analog crystal oscillator's output strategy based on the changing trends of these factors. By continuously correcting and updating the output parameters, the system can maintain accurate time output with high stability even when the external time source fails.

[0041] This implementation achieves precise control with second-level time accuracy by introducing a second pulse monitoring mechanism based on a high sampling rate of 200MHz. Compared with traditional self-timekeeping schemes, this method can still dynamically adjust based on historical data even when an external time source is lost, significantly improving the system's time-keeping capability. Simultaneously, by comparing variance changes to identify abnormal periods and adjusting the output of the analog crystal oscillator in a timely manner, the impact of temperature drift and system noise on time-keeping accuracy is effectively suppressed. Furthermore, the dynamic adaptive mechanism ensures that the system maintains stable performance in the face of environmental fluctuations, further enhancing the system's robustness and application adaptability.

[0042] The phase-locked loop frequency multiplication algorithm is implemented using the Gowin IP core. The frequency multiplication factor is 20, and the selection of the frequency multiplication factor is based on the ratio of the FPGA clock frequency to the target high-frequency clock.

[0043] In this embodiment, to stably boost the system base clock from 10MHz to 200MHz, the field-programmable gate array (FPGA) is configured with and utilizes a phase-locked loop (PLL) IP core provided by Gowin Semiconductor. This IP core is a standard digital logic module capable of multiplying, dividing, and controlling the phase of the input clock signal.

[0044] First, the system inputs the 10MHz temperature-controlled active crystal oscillator output signal to the FPGA's global clock input port via wiring. This clock signal then enters the phase-locked loop (PLL) module as a reference input via a clock buffer. In the FPGA engineering configuration, the input parameters set for the PLL IP core include the reference clock frequency, the target output frequency, and the multiplication factor. Since there is a clear integer multiple relationship between 10MHz and the target output frequency of 200MHz, a multiplication factor of 20 is chosen.

[0045] The internal logic of the phase-locked loop (PLL) module is based on a feedback control mechanism. It mainly consists of three parts: a phase comparator, a loop filter, and a voltage-controlled oscillator (VCO). When a 10MHz reference clock signal enters the PLL module, the system first activates a feedback channel. The output clock signal, after being processed by a frequency divider, is sent to the phase comparator for phase comparison with the reference signal. If there is a difference in their edge positions, the system generates a set of phase difference control signals. These signals are smoothed by the filter and then control the VCO to adjust its frequency output, gradually approaching the target frequency until the phase difference between the reference clock and the feedback clock is minimized or zero, thus achieving a locked state.

[0046] In locked state, the frequency of the output clock signal is 200MHz, which is the 10MHz reference frequency multiplied by 20. The system uses this as the master clock for all subsequent modules. This output signal features high stability and low phase noise, and can be directly used in counter driving, second pulse rising edge capture, and time statistics logic modules to ensure the timing accuracy of the entire system.

[0047] This phase-locked loop (PLL) IP core is embedded into the bitstream file as a logic constraint during FPGA synthesis. When deployed in hardware, its control registers support status querying and debugging, facilitating developers to confirm the lock status and diagnose phase deviations. Furthermore, the system's logic design includes a PLL completion flag; subsequent timing logic is only allowed to start when this flag is valid, ensuring the stability and reliability of the entire timing chain.

[0048] This implementation method avoids the complexity of designing custom clock management logic by using a dedicated phase-locked loop (PLL) IP core provided by Gowin, while ensuring timing accuracy and frequency stability during the frequency multiplication process. Because this IP core has high integration and maturity, it can be called on different FPGA chips via a standard interface, significantly shortening the development cycle. Setting the frequency multiplication factor to twenty satisfies the system's frequency conversion requirements from 10 MHz to 200 MHz, while ensuring a strict correspondence between the clock multiplication factor and the target sampling rate, preventing frequency deviations from affecting subsequent time counting accuracy. Overall, this approach helps improve the system's time synchronization capability and sampling accuracy, laying a high-quality clock foundation for subsequent second pulse capture and time holding.

[0049] The time data provided by the satellite module includes time signals from at least three satellites, wherein the signal quality of each satellite meets a preset signal quality standard, which includes the signal noise figure, the signal phase deviation, and the satellite positioning accuracy.

[0050] In this embodiment, the system connects to an external satellite receiving module via a communication interface. This satellite module can simultaneously receive satellite signals from multiple navigation systems, such as the Global Positioning System (GPS), BeiDou Navigation Satellite System (BDS), Galileo Navigation Satellite System (GDS), and GLONASS Navigation Satellite System (GLONASS). The system has a time synchronization quality assurance mechanism that requires the collected satellite time data to simultaneously meet the following two conditions: first, the number of received satellite signals must be no less than three; and second, each satellite signal must meet a preset signal quality standard.

[0051] During operation, the system reads navigation messages from the satellite module every 1 second and sequentially extracts signal parameters from all visible satellites. The signal from each satellite undergoes a three-dimensional quality assessment: First, the signal noise figure, or signal-to-noise ratio (SNR). This parameter assesses the clarity of the satellite signal in the current environment. The system considers a signal usable if its SNR is greater than or equal to 30; otherwise, it is discarded. Second, phase deviation, the difference between the current phase of the satellite signal and the phase predicted by the theoretical model. The system requires this value to be less than 1 microsecond; otherwise, it is considered an abnormal signal. Third, positioning accuracy, derived from the accuracy estimate included in the positioning calculation results output by the satellite module. The system requires this value to be within 5 meters; if it exceeds this value, it indicates that the current signal is significantly affected by multipath interference or obstruction, and will be discarded.

[0052] After completing the above three assessments, the system includes all satellite signals that meet the above conditions in the "available satellite set". The system is configured with judgment logic that only when the number of valid satellites in the set is greater than or equal to 3 will the system be allowed to enter the synchronization state, and time data and second pulse signals will be extracted from them as the current clock reference source.

[0053] For the time data in this set, the system employs a time consistency detection mechanism, which detects the maximum time difference between the time scale values ​​of the three satellites. If the difference is within a specified tolerance (e.g., 100 nanoseconds), the time consistency is considered good, and the system will use the average time of the satellites in the set as the current reference time; otherwise, the synchronization process is rejected during this time period, and the system proceeds to the next period to wait for qualified data.

[0054] Simultaneously, the system records the signal-to-noise ratio, phase deviation, and positioning accuracy of each adopted satellite signal in the system log for reference in subsequent signal quality trend analysis and adaptive adjustment mechanisms. This mechanism is repeatedly executed throughout the synchronization cycle, enabling real-time filtering and acquisition of high-quality multi-source time signals, ensuring the accuracy and stability of the time reference upon which the system relies.

[0055] By introducing signals from multiple satellites and setting explicit signal quality standards, this implementation method effectively enhances the anti-interference capability and robustness of the time synchronization process. The strategy of using at least three satellite signal sources avoids the risk of missynchronization caused by distortion or anomalies in a single satellite signal. Joint constraints on signal-to-noise ratio, phase stability, and positioning accuracy ensure high reliability and engineering usability of the adopted time signals, significantly reducing the system's second pulse alignment error and contributing to improved timing accuracy of subsequent self-synchronous timing modules and the reliability of reference data. Overall, this approach improves the quality of time signal acquisition and the prerequisites for high-precision self-synchronous timing in the entire system.

[0056] The reference second pulse signal is selected by filtering signals with high data quality and a large number of satellites. The filtering method adopts a weighted average algorithm. When calculating the reference second pulse, not only the number of satellites is considered, but also different weights are assigned according to the quality of each satellite signal.

[0057] In this embodiment, to improve the stability and representativeness of the system's reference second pulse signal, the system executes a second pulse filtering mechanism based on a weighted average algorithm within a one-second synchronization cycle. First, the system connects to an external satellite module to extract the second pulse data and signal quality indicators of currently visible satellites. The system presets a minimum effective satellite count threshold of 3; when this threshold is met, the system enters the second pulse calculation process.

[0058] In practice, the system first reads three key indicators for each satellite that meets the signal quality requirements: signal-to-noise ratio (SNR), phase deviation, and positioning accuracy. Each indicator is quantified into a score. The system assigns a quality score to each satellite, which is a weighted sum of the three indicators. Signals with an SNR higher than 30 dB receive a higher score, signals with a phase deviation of less than 1 microsecond receive an even higher score, and signals with a positioning accuracy of less than 5 meters are also assigned a higher value. Each indicator can be assigned a corresponding weight; for example, SNR accounts for 40%, phase deviation for 30%, and positioning accuracy for 30%. The sum of these three factors yields the satellite's total quality score.

[0059] The system then assigns weighting coefficients based on the total quality score of each satellite and multiplies the second pulse time value of each satellite with the corresponding weighting coefficient. After summing all the products, it divides by the sum of all weighting coefficients to obtain the weighted average reference second pulse time point for the current period. In other words, the system does not simply average all second pulse values; instead, it assigns greater influence to high-quality signals and correspondingly reduces the influence of low-quality signals based on the differences in signal quality among the satellites.

[0060] This calculation process executes once per second, using the resulting weighted second pulse time point as the current clock synchronization reference to correct the initial value of the internal 200MHz driven counter and for high-precision time alignment operations within the system. Simultaneously, this time point is also stored in the on-chip memory, providing high-quality data support for subsequent predictive modeling under self-timed conditions.

[0061] Through this screening and weighting process, the system effectively avoids the accumulation of second pulse errors caused by poor quality of individual satellite signals, improves the stability and accuracy of the overall clock synchronization system, and ensures that the subsequent time-keeping mechanism operates on a reliable and high-precision basis.

[0062] This implementation introduces a weighted averaging mechanism based on satellite signal quality, making the reference second pulse's time point more representative and accurate, and avoiding time deviations caused by the incorporation of low-quality signals. Compared to traditional simple averaging methods, this scheme is more robust in multi-satellite parallel operation environments, and is particularly suitable for application scenarios with complex channel conditions or unstable signals. By assigning higher weights to high-quality signals, the overall time synchronization accuracy of the system is improved, effectively enhancing the accuracy and stability of subsequent predictions by the self-timekeeping algorithm.

[0063] The mean and variance of each time period of the reference second pulse data are calculated based on the rising edge of the pulse measured in real time. The mean is calculated as the arithmetic mean of the maximum value of the counter per second, and the variance is calculated as the average of the sum of squares of the differences between the maximum value of the counter per second and the mean.

[0064] In this embodiment, the system uses a 200MHz clock as the sampling reference, which is provided by the phase-locked loop module of the field-programmable gate array. The system employs a high-precision counter that automatically resets to zero and starts counting from 0 within each second pulse cycle. Within a complete second cycle, from the rising edge of one second pulse to the rising edge of the next, the counter continuously increments. When the system detects the next rising edge of the pulse, it immediately latches the current counter value and records it as the "maximum count value" for that second cycle.

[0065] During continuous operation, the system will continuously record such "maximum count values" for no less than 30 minutes. At a rate of once per second, a total of 1800 data points can be obtained. The system divides these 1800 values ​​into several time periods of fixed duration. For example, if each time period is 300 seconds, the entire dataset can be divided into 6 time periods, each containing 300 maximum counter values.

[0066] During statistical processing, the system first performs a summation operation on the 300 values ​​within each time period, accumulating these 300 "maximum count values" one by one to obtain a sum. Then, the sum is divided by 300 to obtain the "mean" of that time period, which is the average of the maximum counter values ​​within that 300-second period, and is used to represent the average frequency of the analog crystal oscillator output during that period.

[0067] Subsequently, the system further processes the maximum value of each counter within this segment. First, it subtracts the previously calculated "mean" from this value, then squares the difference, and finally sums all 300 squared results to obtain a sum of squared differences. Finally, the system divides this sum by 300 to obtain the "variance" of this time period, reflecting the degree of fluctuation in the simulated crystal oscillator frequency during this period.

[0068] The entire process of calculating the mean and variance is automatically completed in a pipelined manner within the system by a dedicated computation module in a field-programmable gate array (FPGA). The obtained mean and variance results are stored in on-chip memory and serve as a crucial basis for subsequent self-timekeeping calculations in the event of satellite time source failure. After entering self-timekeeping mode, the system sets the output target of the analog crystal oscillator based on these statistical results of historical time periods, thereby ensuring timing accuracy and long-term stability.

[0069] This implementation method records the count values ​​corresponding to the rising edges of pulses with high precision within a one-second cycle, and calculates the mean and variance based on mathematical statistical methods, forming highly stable and representative statistical characteristics over a time period. This method not only reflects the operating state of the analog crystal oscillator over a certain period of time, but also provides a clear evaluation basis for subsequent dynamic adjustments. Compared with traditional methods that only use single-point frequency data, this method can more accurately capture frequency fluctuation trends, improve self-timekeeping accuracy and system response capability, and is particularly suitable for time-keeping applications in dynamic environments.

[0070] The initial value of the variable k, which simulates the number of output pulses of the crystal oscillator, is the mean of each time period. During each calculation, the variable k is adjusted according to the variance of the time period. When the difference in variance between adjacent time periods exceeds a preset threshold, it indicates that the fluctuation of the crystal oscillator frequency is relatively violent, and the value is updated to the mean of the current time period. If the difference in variance does not exceed the preset threshold, the mean of the previous time period is maintained.

[0071] In this embodiment, when the system is in self-timed mode, the variable k serves as the control basis for the analog crystal oscillator, and its value directly determines the time base output by the system. Before the external time signal fails, the system has recorded and calculated the mean and variance of the maximum value of the second pulse counter for multiple consecutive time periods, and these data are stored in memory.

[0072] When the system enters self-timed state, it first reads the mean data of the first time interval from memory and sets this value as the initial value of variable k. Subsequently, the system reads the variance value of each time interval sequentially and compares it with the variance value of the previous time interval. Specifically, the comparison method involves first calculating the difference between the variance value of the current time interval and the variance value of the previous time interval, and then taking the absolute value of this difference to quantify the degree of crystal oscillator frequency fluctuation between the two time intervals.

[0073] The system sets a threshold for judging variance difference during factory manufacturing or initialization, for example, 10000. After each comparison, the system compares the absolute difference with this threshold. If the difference is greater than 10000, it indicates that the crystal oscillator frequency fluctuates significantly within the current time period, and the system considers the statistical state of the current time period to be more representative. Therefore, the variable k is updated to the mean of the current time period. If the difference is less than or equal to 10000, it indicates that the stability of the current time period is basically the same as that of the previous time period, and the system continues to use the mean of the previous time period as the value of variable k without updating it.

[0074] This decision logic is executed once at the end of each time period and continues to iterate through all time periods, forming a dynamic update process for the variable k. This variable k is ultimately used to control the output of the analog crystal oscillator, making its output pulse number match as closely as possible to the historical operating characteristics of the system when there is an external synchronization signal, thereby ensuring the continuity and accuracy of the system timing.

[0075] The above process can be automated through the internal hardware logic module of the FPGA, including sequential reading, difference judgment, value update and final output, ensuring that the judgment process has real-time performance and high reliability.

[0076] By introducing a variance difference comparison mechanism based on time intervals, this implementation can accurately identify abnormal fluctuations in the crystal oscillator frequency, effectively avoiding the problem of using outdated statistical data when the frequency changes drastically. Simultaneously, a preset threshold mechanism is employed to control fluctuations within an acceptable range, ensuring a certain degree of stability and disturbance resistance in the self-time adjustment process. The dynamically updated variable k enables the simulated crystal oscillator to respond promptly to state changes during operation, significantly improving the system's accuracy and adaptability in self-time mode.

[0077] It also includes a strategy to determine whether to update the number of analog crystal oscillator output pulses by comparing the variance difference between adjacent time periods. The update condition is that the variance difference between adjacent time periods exceeds a set threshold. If the difference exceeds the threshold, the mean of the current time period is used as the new value; if the difference is below the threshold, the mean of the previous time period is used.

[0078] In this embodiment, after the system enters the self-timed state, to ensure that the adjustment strategy for the number of output pulses of the analog crystal oscillator can dynamically change with the system state, a strategy update mechanism based on the variance difference between adjacent time periods is designed. This mechanism relies on the statistical data of multiple time periods previously recorded and calculated, namely the mean and variance of each time period, to dynamically evaluate the stability and fluctuation of the crystal oscillator frequency.

[0079] In the specific implementation process, the system first reads the variance values ​​of two adjacent time periods from the memory in chronological order. For example, it reads the variances of the first and second periods, calculates the difference between them, and takes the absolute value as a comparison index. The system sets a threshold value to determine whether the difference indicates significant frequency fluctuations. This threshold value is a fixed value, such as 10000.

[0080] If the absolute value of the variance difference between two time periods is greater than 10000, it indicates that the output frequency stability of the crystal oscillator has changed significantly between these two time periods. Based on this, the system judges that the existing control strategy may no longer be applicable, so it immediately makes adjustments and sets the mean of the current time period, i.e. the mean of the second period, as the new reference value for the number of analog crystal oscillator output pulses to update the frequency control logic.

[0081] Conversely, if the difference is less than or equal to 10,000, it indicates that the fluctuation of the crystal oscillator frequency is within an acceptable range. The system determines that the frequency is basically stable, so no adjustment is made, and the average value of the previous time period, i.e. the average value of the first period, is used as the basis for the current frequency control strategy to avoid unstable output caused by frequent changes in the system.

[0082] This judgment process is executed automatically after data processing is completed for each new time period, and variable updates are completed through the logic comparison module in the FPGA in conjunction with the state switching controller. The system can also mark and store each judgment result for subsequent trend tracking analysis and strategy optimization.

[0083] By using this strategy update method based on statistical data differences, the system can flexibly choose whether to update the control parameters according to the changes in crystal oscillator performance in practical applications, thereby effectively enhancing the control capability of the output frequency in self-timekeeping mode and improving the stability and time retention accuracy of the entire system.

[0084] This implementation method achieves real-time monitoring and strategy updates for crystal oscillator frequency stability by setting a clear variance difference threshold as a judgment condition, significantly improving the system's ability to cope with environmental changes and inherent fluctuations. Compared to a fixed adjustment strategy, this solution has higher adaptability and judgment sensitivity, enabling rapid response to sudden changes in system state and preventing frequency drift from affecting the time base. Simultaneously, by maintaining the strategy unchanged when the difference is less than the threshold, it effectively avoids system jitter caused by frequent switching, further optimizing the operating efficiency and output stability in self-timekeeping mode.

[0085] The satellite signal selection logic optimizes the selection process based on the number of satellites and data quality over multiple time periods. It also selects the best signal source by calculating the average quality and number of satellite signals within the current time period and combining historical data.

[0086] In this embodiment, to improve the accuracy and stability of satellite signal selection, the system constructs a comprehensive optimization selection logic based on the number of satellites and signal quality over multiple time periods. This logic periodically collects and records the satellite signal status every second during system operation and performs centralized analysis at the end of each time period.

[0087] The system first extracts all currently available satellite information from the accessed satellite modules within a one-second cycle. For each satellite, the system reads three indicators: signal-to-noise ratio (SNR), signal phase deviation, and positioning accuracy. The system sets evaluation criteria for each indicator. For example, an SNR higher than 30 dB is considered a high-quality signal, a signal phase deviation lower than 1 microsecond indicates a stable signal, and a positioning accuracy lower than 5 meters indicates reliable space positioning. Based on these three indicators, the system assigns a rating level to each satellite and uses this to construct a set of signal quality data for all available satellites within that second.

[0088] After each data recording period, for example, every 300 seconds, the system performs statistical analysis on all second-level data within that period. First, the system calculates the average signal quality score for all participating satellites within that period. Second, it counts the number of available satellites per second within that period and calculates their average to obtain the average number of satellites in that period. These two values ​​together constitute the signal stability characteristics for that period.

[0089] When selecting a reference second pulse synchronization source, the system no longer relies solely on data from the current second or time period. Instead, it simultaneously retrieves and compares statistical results from several previous time periods (e.g., the past five periods). The system compares the average number of satellites and the average signal quality of the current time period with similar indicators from historical time periods, prioritizing signal sources within time periods with high average quality, a large number of satellites, and minimal fluctuations. Priority determination also considers signal persistence over past time periods; for example, if a satellite consistently achieves a high score for three consecutive periods, that satellite will be assigned higher reference value.

[0090] Ultimately, the system uses the set of satellites selected through this comprehensive evaluation process as the time synchronization reference source, extracting their corresponding second pulse information and timestamps as the internal clock alignment benchmark. This process is repeated every 300 seconds to ensure that the reference signal has high stability and consistency during long-term operation.

[0091] This implementation method overcomes the limitations of traditional real-time single-point quality assessment by introducing a satellite signal selection mechanism spanning multiple time periods, making it particularly effective in complex or short-term unstable signal environments. This method utilizes historical data trends for reference source optimization, effectively avoiding time base shifts caused by instantaneous signal fluctuations, and significantly improving the stability of the reference second pulse and the overall system synchronization accuracy. Furthermore, the selection model based on multidimensional statistical analysis is scalable and can adapt to more complex navigation system signal environments.

[0092] The satellite signal selection logic prioritizes multiple received satellite signals and selects the satellite data with the most satellites as the reference signal.

[0093] In this embodiment, the system employs a second-pulse reference signal selection mechanism based on satellite quantity priority ranking to enhance the system's ability to select high-quality synchronization sources during self-synchronous operation. This mechanism primarily relies on the satellite navigation data received periodically every second to make judgments and selects the most suitable signal source as the system synchronization reference according to priority.

[0094] During operation, the system acquires a complete set of satellite navigation data from an external satellite receiving module every second via a serial communication interface or a dedicated navigation data channel. This data contains information about multiple independent satellites, with each satellite's information including its number, current signal quality status, timestamp, and whether it meets validity conditions.

[0095] After receiving complete data, the system first performs a screening step: removing satellite signals that do not meet the minimum signal quality standards from the data set. For example, signals with a signal-to-noise ratio below 30 dB, a phase deviation above 1 microsecond, or a positioning accuracy above 5 meters are all excluded. The system counts the number of satellites remaining after the exclusions and uses this number as the "effective number of satellites" for the current candidate reference signal group.

[0096] When multiple candidate signal groups coexist, the system sorts all groups by the number of "effective satellites" from largest to smallest. The system sets a priority selection logic, that is, it first selects the signal group with the largest number of "effective satellites" as the reference second pulse signal source for the current period.

[0097] If multiple signal groups have the same number of "effective satellites," the system further performs a second-level judgment: calculating the average signal quality of all satellites within each candidate signal group. The system uses this average quality value as a second ranking criterion, selecting the signal group with the highest average quality as the final second pulse synchronization source. The purpose of this is to prioritize the synchronization data source with higher quality and greater stability when the number of satellites is the same.

[0098] The final selected satellite signal group will be used to extract the current second pulse time point and its corresponding timestamp. The system will then use this information to calibrate its internal clock and for reference updates to the subsequent 200MHz counter. The entire process is executed automatically once per second, ensuring sufficient real-time performance and stability of the system's synchronization reference.

[0099] This implementation employs a priority selection mechanism based on the number of satellites, simplifying the reference signal selection logic and improving the system's anti-interference capability and response speed in complex electromagnetic environments. By prioritizing the signal group with the largest number of satellites as the reference, not only is the spatial redundancy of synchronization data improved, but robustness to factors such as multipath effects and signal obstruction is also enhanced. Furthermore, this scheme offers good real-time performance and computational efficiency, making it particularly suitable for implementing high-precision timekeeping in scenarios with frequent fluctuations in navigation signal strength.

[0100] The strategy for adjusting the number of output pulses of the analog crystal oscillator includes recursive analysis based on historical data to predict the trend of crystal frequency changes in the future time period.

[0101] In this embodiment, in order to improve the time-holding performance and frequency stability of the system in self-keeping state, the system designs a recursive analysis mechanism based on historical statistical data to predict the changing trend of the simulated crystal oscillator frequency in the future time period, and dynamically adjust its output pulse number control value accordingly.

[0102] During operation, the system takes the average of the maximum values ​​of the second pulse counter recorded within a fixed time interval, such as every 300 seconds, and stores this average value in on-chip RAM or non-volatile memory. The system continuously records the average data for multiple time intervals and arranges them in chronological order to form a statistical data sequence.

[0103] In self-timed mode, the system first extracts the average data from the five most recent consecutive time periods, forming a data list of length 5, representing the frequency performance of the simulated crystal oscillator over the past 1500 seconds. The system performs recursive trend analysis on this list to determine whether the average shows a gradual increasing or decreasing trend. Specifically, this involves calculating the difference between the averages of two adjacent time periods and summing these consecutive differences to obtain a cumulative trend value, which is used to determine the direction and speed of frequency change.

[0104] If the system detects that the mean value of subsequent time intervals is continuously increasing compared to previous time intervals (e.g., the second interval is greater than the first, the third is greater than the second, the fourth is greater than the third, and the fifth is greater than the fourth), then the system considers the crystal oscillator output frequency to be trending upwards. To maintain system time accuracy, the system will appropriately decrease the value of variable k in the next time interval, for example, by decreasing it by 100 count units. Conversely, if the mean value continuously decreases, indicating a frequency decrease, the system will increase the value of variable k, for example, by increasing it by 100 count units, to compensate for the decrease in crystal oscillator frequency.

[0105] When performing adjustments, the system sets a maximum allowable adjustment step size, such as a single adjustment not exceeding 500 count units, to prevent overcorrection due to prediction errors. Simultaneously, the system sets a trend judgment threshold; for example, if the cumulative trend value within 5 segments is less than 500 count units, it indicates that the fluctuation is insufficient to constitute a trend, and no adjustment is made in this case.

[0106] This recursive prediction mechanism executes once after each new time period data recording is completed, constantly tracking the crystal oscillator output state and making corrections in advance based on trends. The adjusted value of variable k is used as the target for controlling the output pulse of the simulated crystal oscillator in the next time period, thereby maintaining the stability of the system clock output.

[0107] By introducing a frequency prediction mechanism based on recursive analysis of historical data, this implementation achieves proactive control of crystal oscillator frequency variation trends. This allows the system to prepare for frequency adjustment in advance should an external time source fail, significantly improving time retention accuracy. Compared to traditional static mean maintenance strategies, this approach dynamically responds to natural factors such as crystal oscillator aging and temperature drift, enhancing the system's long-term timing stability and adaptability. Furthermore, this mechanism achieves predictive control without relying on external sensors or complex hardware, demonstrating excellent ease of implementation and versatility.

[0108] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A high-precision self-synchronous timing method based on FPGA, characterized in that, The method includes: A 10MHz system clock is provided by a temperature-controlled active crystal oscillator, and the clock frequency is upsampled to 200MHz using a phase-locked loop frequency multiplication algorithm; The system is time-synchronized using reliable time data and valid second pulse signals provided by the satellite module, and reference second pulses are filtered and selected. Record at least 30 minutes of reference second pulse data, monitor the rising edge of the second pulse based on a sampling rate of 200MHz, and store the maximum value of the second counter to RAM; The recorded reference second pulse data is divided into multiple time periods, and the mean and variance of each time period are calculated separately. In the event of a satellite signal interruption, the mean and variance data are read from RAM, and the variable k for the number of output pulses of the analog crystal oscillator is set. Initially, the value of k is the mean of the first time period. Compare the variance differences between adjacent time periods. If the difference exceeds a preset threshold, update the value of k to the mean of the corresponding time period; if the difference is below the threshold, maintain the mean of the previous time period. A dynamic adaptive adjustment mechanism is introduced to dynamically adjust the adjustment strategy of the analog crystal oscillator output pulse number by analyzing factors such as signal quality and environmental changes in real time, thereby optimizing the accuracy and stability of self-timekeeping. By continuously adjusting the value of k, the actual output pulse number of the crystal oscillator is simulated, thereby achieving high-precision self-timekeeping.

2. The high-precision self-timekeeping method based on FPGA according to claim 1, characterized in that: The phase-locked loop frequency multiplication algorithm is implemented using the GoCloud IP core. The frequency multiplication factor is 20, and the selection of the frequency multiplication factor is based on the ratio of the FPGA clock frequency to the target high-frequency clock.

3. The high-precision self-timekeeping method based on FPGA according to claim 1, characterized in that: The time data provided by the satellite module includes time signals from at least three satellites, wherein the signal quality of each satellite meets a preset signal quality standard, which includes the signal noise figure, the signal phase deviation, and the satellite positioning accuracy.

4. The high-precision self-timekeeping method based on FPGA according to claim 1, characterized in that: The reference second pulse signal is selected by filtering signals with high data quality and a large number of satellites. The filtering method adopts a weighted average algorithm. When calculating the reference second pulse, not only the number of satellites is considered, but also different weights are assigned according to the quality of each satellite signal.

5. The high-precision self-timekeeping method based on FPGA according to claim 1, characterized in that: The mean and variance of the reference second pulse data for each time period are calculated based on the rising edge of the pulse measured in real time. The mean is calculated as the arithmetic mean of the maximum value of the counter per second, and the variance is calculated as the average of the sum of squares of the differences between the maximum value of the counter per second and the mean.

6. The high-precision self-timekeeping method based on FPGA according to claim 1, characterized in that: The initial value of the variable k for the number of simulated crystal oscillator output pulses is the mean of each time period. In each calculation, the variable k is adjusted according to the variance of the time period. When the difference in variance between adjacent time periods exceeds a preset threshold, it indicates that the crystal oscillator frequency fluctuates more violently, and then it is updated to the mean of the current time period. If the variance difference does not exceed the preset threshold, the mean of the previous time period will be maintained.

7. The high-precision self-timekeeping method based on FPGA according to claim 1, characterized in that, It also includes a strategy to determine whether to update the number of analog crystal oscillator output pulses by comparing the variance difference between adjacent time periods. The update condition is that the variance difference between adjacent time periods exceeds a set threshold. If the difference exceeds the threshold, the mean of the current time period is used as the new value; if the difference is below the threshold, the mean of the previous time period is used.

8. The high-precision self-timekeeping method based on FPGA according to claim 1, characterized in that: The satellite signal selection logic optimizes the selection process based on the number of satellites and data quality over multiple time periods. It also selects the best signal source by calculating the average quality and number of satellite signals within the current time period and combining historical data.

9. The high-precision self-timekeeping method based on FPGA according to claim 1, characterized in that: The satellite signal selection logic prioritizes multiple received satellite signals and selects the satellite data with the most satellites as the reference signal.

10. A high-precision self-timekeeping method based on FPGA according to claim 1, characterized in that: The adjustment strategy for the number of simulated crystal oscillator output pulses includes recursive analysis based on historical data to predict the trend of crystal oscillator frequency changes in the future time period.

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