Input / output circuit

Abstract

According to the input and output circuit, a PAD end voltage and a power supply voltage are compared through a high selection module, the higher voltage is output as a substrate control signal end voltage, and it is ensured that the substrate voltage of a pull-up PMOS tube is not lower than the PAD end voltage; meanwhile, a transmission gate switch structure in the related technology is replaced by a structure that an inverter is connected with a PMOS in series, a control module generates a driving control signal based on the working state of the power supply voltage end, and a switch module controls the on-off state of a pull-up PMOS tube in response to the driving control signal, so that the phenomenon of current backflow is prevented, and a chip and connecting equipment are protected.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to an input / output circuit. Background Technology

[0002] Input / output (I / O) circuits serve as interface circuits in electronic systems, performing signal transmission functions. When an I / O circuit is connected to a bus or transmits signals between two electronic systems, there exists an operating state where the I / O power supply voltage terminal (marked as VDDIO) of the I / O chip drops to zero or near zero, while the external bus or connected device remains powered on, causing the signal line to maintain a high level.

[0003] In conventional I / O circuits, the substrate of the pull-up PMOS transistor is directly coupled to the power supply voltage terminal. When the power supply voltage terminal is zero and the pad (Pad Area Device, hereinafter the same) voltage is at a high level, the parasitic diode of the pull-up PMOS transistor will conduct, resulting in current flowing back to the power supply. This phenomenon can affect the chip itself and connected external devices. Summary of the Invention

[0004] The purpose of this application is to provide an input / output circuit to solve the problem of current flowing back to the power supply in conventional IO circuits.

[0005] According to a first aspect of this application, an embodiment of this application provides an input / output circuit, comprising: an input / output module, the input / output module including a pull-up PMOS transistor, the source of the pull-up PMOS transistor being coupled to a power supply voltage terminal, and the drain of the pull-up PMOS transistor being coupled to a PAD terminal; a high-selection module, coupled to the PAD terminal and the power supply voltage terminal, for comparing the voltage at the PAD terminal with the power supply voltage, and outputting the higher of the two voltages as a substrate control signal terminal voltage; a control module, coupled to the high-selection module and the power supply voltage terminal, for generating a drive control signal based on the operating state of the power supply voltage terminal; and a switching module, coupled to the control module, for controlling the switching state of the pull-up PMOS transistor in response to the drive control signal; wherein the substrate of the pull-up PMOS transistor is coupled to the high-selection module through the substrate control signal terminal, such that the substrate voltage of the pull-up PMOS transistor is not lower than the PAD terminal voltage.

[0006] In some possible implementations, the high-selection module includes: a first PMOS transistor, the source of which is coupled to the power supply voltage terminal, the gate of which is coupled to the PAD terminal, the drain of which is coupled to the substrate control signal terminal, and the substrate of which is coupled to the drain of which; and a second PMOS transistor, the source of which is coupled to the PAD terminal, the gate of which is coupled to both the source of which is coupled to the power supply voltage terminal, the drain of which is coupled to the substrate control signal terminal, and the substrate of which is coupled to the drain of which.

[0007] In some possible implementations, the high-selection module is configured such that: when the power supply voltage terminal is operating normally, the voltage of the substrate control signal terminal is equal to the power supply voltage; when the power supply voltage terminal is powered off and the voltage of the PAD terminal is at a first logic level, the voltage of the substrate control signal terminal is equal to the voltage of the PAD terminal.

[0008] In some possible implementations, the control module includes: a first control PMOS transistor, the gate of which is coupled to a power supply voltage terminal, the substrate of which is coupled to a substrate control signal terminal, and the source of which is coupled to a PAD terminal; and a first control NMOS transistor, the gate of which is coupled to a power status signal terminal, and the source and substrate of which are coupled to ground potential; wherein the drain of the first control PMOS transistor is coupled to the drain of the first control NMOS transistor as a drive control signal terminal to output a drive control signal.

[0009] In some possible implementations, when the power supply voltage terminal is de-energized and the PAD terminal voltage is at a first logic level, the first control PMOS transistor is turned on, the first control NMOS transistor is turned off, and the voltage of the drive control signal terminal is equal to the voltage of the PAD terminal, so as to turn off the switching PMOS transistor; when the power supply voltage terminal is energized, the first control NMOS transistor is turned on, the first control PMOS transistor is turned off, and the voltage of the drive control signal terminal is at a second logic level, so as to turn on the switching PMOS transistor.

[0010] In some possible implementations, the control module includes: a second control PMOS transistor, the substrate of which is coupled to a substrate control signal terminal, and the source of which is coupled to a PAD terminal; a second control NMOS transistor, the gate of which is coupled to a power supply voltage terminal, and the source and substrate of which are coupled to ground potential; wherein the drain of the second control PMOS transistor is coupled to the drain of the second control NMOS transistor as a drive control signal terminal to output a drive control signal.

[0011] In some possible implementations, the switching module includes a switching PMOS transistor, the gate of which is coupled to a drive control signal terminal, the source of which is coupled to a power supply voltage terminal, the drain of which is coupled to the source of a pull-up PMOS transistor, and the substrate of which, together with the substrate of the pull-up PMOS transistor, is coupled to a substrate control signal terminal; the switching module is configured to turn off the switching PMOS transistor when the power supply voltage terminal is de-energized and the voltage at the PAD terminal is a first logic level.

[0012] In some possible implementations, an auxiliary module coupled to the control module is further included, which is used to establish an electrical connection path between the substrate control signal terminal and the power supply voltage terminal in response to the drive control signal.

[0013] In some possible implementations, the auxiliary module includes: an auxiliary PMOS transistor, the source of which is coupled to the substrate control signal terminal, the gate of which is coupled to the drive control signal terminal, and the drain of which is coupled to the power supply voltage terminal; when the power supply voltage terminal is powered on, the voltage of the drive control signal terminal is at a second logic level, the auxiliary PMOS transistor is turned on, and the voltage of the substrate control signal terminal is equal to the power supply voltage.

[0014] In some possible implementations, the input / output module further includes: a pull-down NMOS transistor, the drain of which is coupled to the drain of the pull-up PMOS transistor and the PAD terminal, respectively, and the source of which is coupled to ground potential; and a logic module coupled to the gate of the pull-up PMOS transistor and the gate of the pull-down NMOS transistor, respectively, and coupled to an input signal terminal. The logic module is configured to generate a pull-up control signal and a pull-down control signal according to the input signal, and to transmit the pull-up control signal to the pull-up PMOS transistor and the pull-down control signal to the pull-down NMOS transistor.

[0015] This application provides an input / output circuit that compares the PAD terminal voltage with the power supply voltage using a high-selection module and outputs the higher one as the substrate control signal voltage, ensuring that the substrate voltage of the pull-up PMOS transistor is not lower than the PAD terminal voltage. Simultaneously, it uses an inverter-connected PMOS structure instead of the transmission gate switch structure in related technologies. This control module generates a drive control signal based on the operating state of the power supply voltage terminal, and the switching module responds to this drive control signal to control the switching state of the pull-up PMOS transistor, thereby preventing current backflow and protecting the chip and connected devices. The circuit structure of this application eliminates the need for transmission gates, reducing the number of MOSFETs and chip area compared to related technologies. Furthermore, the elimination of complementary control signals for transmission gates lowers design complexity and simplifies circuit design and control logic. Additionally, by avoiding transmission gate intervention, the rise time delay at the output is reduced, with measured data showing a 70.98% improvement in the IO output duty cycle, thus enhancing circuit response speed, making it particularly suitable for high-frequency applications. Moreover, this circuit eliminates the dynamic power consumption generated by transmission gate switches during high-frequency operation in related technologies, and measured data shows that the current driving the PMOS transistor is only 13pA when backflow prevention is implemented. Simultaneously, this circuit solves the problem of high on-resistance of transmission gate switches under low-voltage operating conditions, which increases with temperature, thereby enhancing circuit stability under different operating conditions. It also surpasses related technologies in pull-up capability, as the control of the pull-up PMOS transistor in related technologies is limited by the transmission gate, while this application avoids this effect, thus possessing stronger pull-up capability and effectively ensuring signal integrity and transmission quality. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of a traditional I / O circuit.

[0018] Figure 2 This is a schematic diagram of an I / O circuit in related technologies.

[0019] Figure 3 This is a schematic diagram of an I / O circuit that uses a transmission gate switch.

[0020] Figure 4 This is a schematic diagram of the input / output circuit of this application.

[0021] Figure 5This is a schematic diagram of another embodiment of the control module of this application.

[0022] Figure 6 This is a schematic diagram illustrating the performance effects of this application and related technologies using simulation data. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] Input / output circuits (IO circuits, the same below) serve as interface circuits to perform signal transmission functions in electronic systems. When an IO circuit is connected to a bus or transmits signals between two electronic systems, there exists an operating state where the IO power supply voltage (i.e., VDDIO terminal voltage) of the IO chip drops to zero or close to zero, while the external bus or connected device remains powered on, causing the signal line to maintain a high level.

[0025] like Figure 1 As shown, in a conventional I / O circuit, the substrate of the pull-up PMOS transistor is directly coupled to the VDDIO terminal. When the VDDIO terminal voltage is zero and the PAD terminal voltage is high, the parasitic diode of the pull-up PMOS transistor will conduct, causing current to flow back to the power supply. This phenomenon not only affects the stability of the chip itself but may also damage connected external devices.

[0026] To address the aforementioned issues, related technologies propose that the substrate voltage of the pull-up PMOS transistor should not be lower than the PAD terminal voltage to prevent parasitic diodes from conducting and to avoid reverse current in the I / O circuit.

[0027] In the process of seeking a more effective solution, the researchers of this application discovered that, Figure 2As shown, for a pull-up PMOS transistor, when the VDDIO terminal is not powered and the PAD terminal voltage is high, the voltage of the pull-up control signal (P_signal) connected to its gate terminal is zero, the substrate voltage is equal to the PAD terminal voltage, and the source is coupled to the VDDIO terminal, while the drain is coupled to the PAD terminal. In this situation, since the PAD potential is higher than the VDDIO terminal voltage, according to the definition of a PMOS transistor (the source is the high potential terminal), the PAD terminal effectively acts as the source. Because the substrate voltage is equal to the PAD terminal voltage, a body effect occurs. This body effect changes the electric field distribution in the channel region, further causing the PAD terminal to become the actual source. Furthermore, the source-drain interchange makes the gate-source voltage difference an effective conduction condition. Therefore, the pull-up PMOS transistor is in a conducting state. This unexpected conduction of the pull-up PMOS transistor can cause current backflow, where current flows backward into the power supply, which may damage the stability of the circuit and related components.

[0028] Further analysis revealed that employing a switching design in the circuit can resolve the current backflow phenomenon caused by the pull-up PMOS transistor being turned on. For example... Figure 3 As shown, specifically, a switch design is added to the circuit. The switch used is a transmission gate switch. When the VDDIO terminal is powered down and the PAD terminal is in a high-level state, the signal for the gate of the pull-up PMOS transistor is switched from a zero-voltage pull-up control signal to a high-level signal at the PAD terminal. In this state, the pull-up PMOS transistor will be completely turned off, thereby effectively preventing current backflow.

[0029] However, while using a transmission gate switch can solve the current backflow problem, it introduces new technical issues: from multiple perspectives, transmission gate switches have several drawbacks. In terms of power consumption, the transmission gate generates significant dynamic power consumption when frequently switching states, especially at higher system operating frequencies, where this problem becomes more pronounced and may become a key factor limiting system performance. Performance-wise, there are several issues: First, the transmission gate's on-resistance is relatively high, a drawback that is more pronounced in low-voltage operating environments, leading to significant attenuation and delay during signal transmission. Second, due to the combined effect of on-resistance and parasitic capacitance, signals are prone to distortion when passing through the transmission gate, particularly in high-frequency applications or scenarios requiring long-distance transmission. Furthermore, parasitic capacitance and on-resistance together limit the switching speed of the transmission gate, posing a challenge to high-frequency applications requiring rapid response. Finally, the performance of the transmission gate is sensitive to temperature changes; in high-temperature environments, the on-resistance further increases, exacerbating the degradation of signal transmission quality. In terms of area, transmission gates typically require complementary control signals (such as positive and negative signal pairs) to ensure normal operation, which not only increases the complexity of circuit design but also occupies more valuable chip area resources.

[0030] To address the above issues, based on a comprehensive analysis of the shortcomings of the aforementioned transmission gate technology solutions, this application proposes an input / output circuit. This circuit uses a high-selection module to compare the PAD terminal voltage with the power supply voltage and outputs the higher voltage as the substrate control signal, ensuring that the substrate voltage of the pull-up PMOS transistor is maintained at or above the PAD terminal voltage. Simultaneously, an inverter-connected PMOS structure replaces the transmission gate switch structure in related technologies. The control module generates a drive control signal based on the operating state of the power supply voltage terminal, and the switching module responds to this drive control signal to control the switching state of the PMOS transistor, thereby preventing current backflow and protecting the chip and connected devices. The circuit design of this application has the following advantages: The circuit structure of this application eliminates the need for transmission gates, reducing MOS transistor devices and chip area. Furthermore, since there is no need to generate complementary control signals for the transmission gates, design complexity is reduced, simplifying circuit design and control logic. Additionally, because this application avoids the intervention of transmission gate switches, the rise time delay at the output is reduced, improving circuit response speed, making it particularly suitable for high-frequency applications. Moreover, the circuit of this application eliminates the dynamic power consumption generated by transmission gate switches during high-frequency operation in related technologies. Simultaneously, this circuit solves the problem of high on-resistance of transmission gate switches under low-voltage operating conditions, which increases with temperature, thereby enhancing the stability of the circuit under different operating conditions. In terms of pull-up capability, it surpasses circuits in related technologies. This is because the pull-up capability of the pull-up PMOS transistor in related technologies is limited by the influence of the transmission gate, while this application avoids such influence, thus possessing stronger pull-up capability and effectively ensuring signal integrity and transmission quality.

[0031] like Figure 4 As shown, this application embodiment provides an input / output circuit 1, which may include: an input / output module 60, a height selection module 10, a control module 20, a switch module 30, and an auxiliary module 40.

[0032] In this embodiment, the input / output module 60 may include a pull-up PMOS transistor MP5, the source of which is coupled to the power supply voltage terminal (i.e., VDDIO terminal), and the drain of which is coupled to the PAD terminal.

[0033] In this embodiment, the high selection module 10 is coupled to the PAD terminal and the power supply voltage terminal, and is used to compare the PAD terminal voltage with the power supply voltage (i.e., the VDDIO terminal voltage), and output the higher of the two voltages as the substrate control signal terminal voltage NW.

[0034] In one specific embodiment, the high-voltage selection module 10 may include a first PMOS transistor MP1 and a second PMOS transistor MP2. The source of the first PMOS transistor MP1 is coupled to the VDDIO terminal, the gate of the first PMOS transistor MP1 is coupled to the PAD terminal, the drain of the first PMOS transistor MP1 is coupled to the substrate control signal terminal, and the substrate of the first PMOS transistor MP1 is coupled to its drain. The source of the second PMOS transistor MP2 is coupled to the PAD terminal, the gate of the second PMOS transistor MP2 is coupled to both the source and VDDIO terminal of the first PMOS transistor MP1, the drain of the second PMOS transistor MP2 is coupled to the substrate control signal terminal, and the substrate of the second PMOS transistor MP2 is coupled to its drain. Through the above dual PMOS transistor structure design, the high-voltage selection module 10 can accurately compare the voltage at the PAD terminal and the voltage at the VDDIO terminal, and output the higher one as the substrate control signal terminal voltage NW. In the input / output circuit of this application, the substrate of the pull-up PMOS transistor MP5 is coupled to the high selection module 10 through the substrate control signal terminal. Based on this structural design, it is effectively ensured that the substrate voltage of the pull-up PMOS transistor MP5 is always not lower than the PAD terminal voltage, thereby preventing the reverse flow phenomenon caused by the conduction of parasitic diodes.

[0035] In this embodiment, the high-level selection module 10 is configured such that: when the VDDIO terminal is working normally, the substrate control signal terminal voltage NW is equal to the VDDIO terminal voltage; when the VDDIO terminal is powered off and the PAD terminal voltage is at a first logic level, the substrate control signal terminal voltage NW is equal to the PAD terminal voltage, wherein the first logic level is greater than or equal to a first threshold voltage, in other words, the first logic level is high. This can be understood as follows: when the VDDIO terminal is powered off and the PAD terminal voltage is high, the substrate control signal terminal voltage NW is high.

[0036] Continue reading Figure 4 As shown, in this embodiment, the control module 20 is coupled to the high-selection module 10 and the power supply voltage terminal. The control module 20 may include at least one pair of PMOS transistors and NMOS transistors, used to generate a drive control signal FS based on the operating state of the VDDIO terminal.

[0037] In one specific embodiment, the control module 20 may include a first control PMOS transistor MP3 and a first control NMOS transistor MN1. The gate of the first control PMOS transistor MP3 is coupled to a power supply voltage terminal, the substrate of the first control PMOS transistor MP3 is coupled to a substrate control signal terminal, and the source of the first control PMOS transistor MP3 is coupled to a PAD terminal. The gate of the first control NMOS transistor MN1 is coupled to a power state signal OE terminal, and the source and substrate of the first control NMOS transistor MN1 are coupled to ground potential VSS. Further, the drain of the first control PMOS transistor MP3 is coupled to the drain of the first control NMOS transistor MN1 as a drive control signal terminal to output a drive control signal FS. The control module 20 adopts an inverter-connected PMOS structure, where the first control NMOS transistor MN1 forms an inverter pull-down network, and the first control PMOS transistor MP3 forms a series switch network. This structure replaces the transmission gate switch structure in related technologies, offering advantages such as simple circuit structure and clear control logic, and eliminating the need for complementary control signals, thereby reducing circuit design complexity and power consumption. In this embodiment, the control module 20 may further include: a first resistor R1, the first end of which is coupled to the VDDIO terminal, and the second end of which is coupled to the gate of the first control PMOS transistor MP3.

[0038] In this embodiment, when the VDDIO terminal is powered down and the PAD terminal voltage is at the first logic level, the first control PMOS transistor MP3 is turned on, the first control NMOS transistor MN1 is turned off, the drive control signal FS is equal to the PAD terminal voltage, and the switching PMOS transistor MP4 of the switching module 30 is turned off, thereby cutting off the reverse flow path from the PAD terminal to the VDDIO terminal. It should be noted that the switching module 30 and its switching PMOS transistor MP4 will be described in detail below.

[0039] In this embodiment, when the VDDIO terminal is powered on, the first control NMOS transistor MN1 is turned on, the first control PMOS transistor MP3 is turned off, the drive control signal FS is at the second logic level, and the switch PMOS transistor MP4 is turned on.

[0040] In this embodiment, the power status signal terminal is coupled to the operating state of the power supply voltage terminal through a power status signal module (not shown). When the power supply voltage terminal is powered on, the power status signal OE of the power status signal terminal is high, and the first control NMOS transistor MN1 is turned on. When the power supply voltage terminal is powered off, the power status signal OE is low, causing the first control NMOS transistor MN1 to be turned off.

[0041] like Figure 5As shown, in another embodiment, the control module 20 may include a second control PMOS transistor MP7 and a second control NMOS transistor MN3. The substrate of the second control PMOS transistor MP7 is coupled to a substrate control signal terminal, and the source of the second control PMOS transistor MP7 is coupled to a PAD terminal. The gate of the second control NMOS transistor MN3 is coupled to a VDDIO terminal, and the source and substrate of the second control NMOS transistor MN3 are coupled to ground potential.

[0042] Furthermore, the drain of the second control PMOS transistor MP7 is coupled to the drain of the second control NMOS transistor MN3 as a drive control signal terminal to output a drive control signal FS. In this embodiment, the control module 20 may further include: a first resistor R1, the first end of which is coupled to the VDDIO terminal, and the second end of which is coupled to the gate of the second control PMOS transistor MP7.

[0043] In this embodiment, when the VDDIO terminal is powered off and the PAD terminal voltage is at the first logic level, the second control PMOS transistor MP7 is turned on and the second control NMOS transistor MN3 is turned off. The drive control signal FS is equal to the PAD terminal voltage, and the switch PMOS transistor MP4 is turned off, thereby shutting off the reverse flow path from the PAD terminal to the VDDIO terminal.

[0044] In the two embodiments of the control module described above, when the scheme of coupling the first control NMOS transistor MN1 to the power status signal terminal is adopted, not only can the power status signal OE be used to reduce power supply noise, but it can also avoid the situation where the second control PMOS transistor MP7 or the second control NMOS transistor MN3 is not fully turned on or off during the power-on process of the VDDIO terminal, causing the drive control signal FS to be in an intermediate state, as is the case with the scheme of coupling the second control NMOS transistor MN3 to the VDDIO terminal. Through the above circuit design, the control module 20 can accurately generate the drive control signal FS according to the different working states of the VDDIO terminal, so that the circuit can operate stably and reliably under different working conditions, especially exhibiting strong anti-interference ability in working environments with large fluctuations at the VDDIO terminal.

[0045] Continue reading Figure 4 As shown, in this embodiment, the switch module 30 is coupled to the control module 20 and is used to control the switching state of the pull-up PMOS transistor MP5 in response to the drive control signal FS.

[0046] In one specific embodiment, the switching module 30 may include a switching PMOS transistor MP4, the gate of which is coupled to a drive control signal terminal, the source of which is coupled to a VDDIO terminal, the drain of which is coupled to the source of a pull-up PMOS transistor MP5, and the substrates of which are coupled to a substrate signal terminal.

[0047] In this embodiment, the switching module 30 is configured to turn off the switching PMOS transistor MP4 when the VDDIO terminal is powered down and the PAD terminal voltage is at a first logic level, thereby cutting off the reverse current path from the PAD terminal to the VDDIO terminal. The first logic level is greater than or equal to a first threshold voltage, i.e., the first logic level is high. When the VDDIO terminal is powered down and the PAD terminal voltage is high, the drive control signal FS is high (i.e., FS = 1). At this time, the drain of the pull-up PMOS transistor MP5 is at a high level through the PAD terminal, the gate is at a low level through the pull-up control signal, and the substrate is at a high level through the substrate control signal terminal. When the drive control signal FS is high, the gate of the switching PMOS transistor MP4 is high and in a cutoff state, blocking the current path from the PAD terminal to the VDDIO terminal, thus avoiding reverse current flow. Compared with the traditional transmission gate switch structure, this structural design avoids signal attenuation and delay caused by high on-resistance when the signal passes through the transmission gate, improving the circuit's response speed and signal quality, making it particularly suitable for high-frequency applications.

[0048] Furthermore, when the VDDIO terminal is powered on, the drive control signal FS is low (i.e., FS = 0), and the switching PMOS transistor MP4 is in the on state.

[0049] Continue reading Figure 4 As shown, in this embodiment, the auxiliary module 40 is coupled to the control module 20 and is used to establish an electrical connection path between the substrate control signal terminal and the VDDIO terminal in response to the drive control signal FS under normal circuit conditions.

[0050] In one specific embodiment, the auxiliary module 40 may include an auxiliary PMOS transistor MP6. The source of the auxiliary PMOS transistor MP6 is coupled to the substrate control signal terminal, the gate of the auxiliary PMOS transistor MP6 is coupled to the drive control signal terminal, and the drain of the auxiliary PMOS transistor MP6 is coupled to the VDDIO terminal. When the power supply voltage terminal is powered on, the drive control signal FS is at the second logic level, the auxiliary PMOS transistor MP6 is turned on, and the voltage NW at the substrate control signal terminal is equal to the voltage at the VDDIO terminal. Through the design of the auxiliary module, it is possible to prevent the high-selection module from being unable to determine the higher voltage when both the VDDIO terminal voltage and the PAD terminal voltage are high. Through the design of the above auxiliary module, the stability and reliability of the circuit are enhanced, ensuring that the circuit can operate normally under various operating conditions, especially in the critical state where the VDDIO terminal voltage and the PAD terminal voltage are close, thus avoiding the potential risks caused by the uncertainty of the high-selection module.

[0051] Continue reading Figure 4 As shown, in this embodiment, the input / output module 60 of this application may further include: a pull-down NMOS transistor MN2 and a logic module. Specifically, the drain of the pull-down NMOS transistor MN2 is coupled to the drain of the pull-up PMOS transistor MP5 and the PAD terminal, respectively, and the source of the pull-down NMOS transistor MN2 is coupled to ground potential VSS. Further, the common node formed by the drain of the pull-down NMOS transistor MN2 and the drain of the pull-up PMOS transistor MP5 is coupled to the PAD terminal and the input terminal of the buffer / inverter U1, and the output terminal of the inverter / buffer U1 is marked as C.

[0052] In this embodiment, the logic module is coupled to the gate of the pull-up PMOS transistor MP5 and the gate of the pull-down NMOS transistor MN2, respectively. The logic module is coupled to the input signal IN and is configured to generate a pull-up control signal UP and a pull-down control signal DOWN based on the input signal IN. The pull-up control signal UP is transmitted to the pull-up PMOS transistor MP5, and the pull-down control signal DOWN is transmitted to the pull-down NMOS transistor MN2. Through this standard logic control structure, the input / output circuit of this application is seamlessly compatible with existing processors and control systems without the need for additional adaptation layers, facilitating integration into various electronic devices.

[0053] To verify the performance advantages of the input / output circuit of this application, a comparative simulation was performed on the circuit of this application and circuits using transmission gate switching structures in related technologies. The results are as follows: Figure 6 As shown in the diagram. In the simulation, both circuits operate under the same conditions: both use a 100MHz square wave input and a 10pF load. Circuit performance is evaluated by comparing the output signal waveforms. From... Figure 6As can be clearly observed, it is a linear scale (Lin) coordinate axis, where the horizontal axis represents time (in nanoseconds, abbreviated as n), and the vertical axis represents voltage (in volts, abbreviated as V). The blue line A represents the input square wave signal, the yellow curve B represents the output waveform of the circuit in this application, and the green curve C represents the output waveform of the circuit in the related technology. Simulation results show that the rise time response speed of the circuit in this application is significantly faster than that of the related technology circuit, and the duty cycle is significantly optimized. Specific data comparisons are as follows: the duty cycle of this application reaches 51.12%, compared to 46.14% of the related technology, the optimized duty cycle improvement rate is as high as 70.98%; in terms of the number of devices, the circuit in this application uses 8 MOS transistors, which significantly reduces the number of devices compared to the related technology solution using transmission gates; and in terms of power consumption, the drive current for both circuits to achieve the backflow prevention function is 13pA, indicating that this application maintains good power consumption performance while simplifying the circuit structure. Simulation results show that the pull-down capabilities of the two circuits are essentially the same. This is because the pull-down capability mainly depends on the NMOS driver, whose performance is unaffected by the reverse-current protection design. However, in terms of pull-up capability, the circuit in this application is significantly superior to the related technology circuit. This is because in the related technology design, the control of the pull-up PMOS is affected by the transmission gate, resulting in a weaker pull-up capability. The circuit in this application, however, does not require transmission gate control, thus possessing a stronger pull-up capability. Therefore, the circuit in this application achieves improved performance while simplifying the structure, especially in terms of response speed and pull-up capability, while maintaining good power consumption. It is highly suitable for high-frequency electronic systems with high requirements for signal quality and response speed.

[0054] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The features, structures, or characteristics described above can be combined in any suitable manner in one or more embodiments.

[0055] It is understood that those skilled in the art, guided by the above embodiments, can combine various implementation methods in the above embodiments to obtain technical solutions with multiple implementation methods. The above descriptions are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An input / output circuit, characterized in that, include: An input / output module, the input / output module including a pull-up PMOS transistor, the source of the pull-up PMOS transistor being coupled to a power supply voltage terminal, and the drain of the pull-up PMOS transistor being coupled to a PAD terminal; The high-selection module is coupled to the PAD terminal and the power supply voltage terminal, and is used to compare the voltage of the PAD terminal with the power supply voltage, and output the higher voltage of the two as the substrate control signal terminal voltage. The control module, coupled to the height selection module and the power supply voltage terminal, is used to generate drive control signals based on the working state of the power supply voltage terminal; A switching module, coupled to the control module, is used to control the switching state of the pull-up PMOS transistor in response to the drive control signal; The substrate of the pull-up PMOS transistor is coupled to the high-selection module through a substrate control signal terminal, so that the substrate voltage of the pull-up PMOS transistor is not lower than the PAD terminal voltage.

2. The input / output circuit as described in claim 1, characterized in that, The height selection module includes: The first PMOS transistor has its source coupled to the power supply voltage terminal, its gate coupled to the PAD terminal, its drain coupled to the substrate control signal terminal, and its substrate coupled to the drain of the first PMOS transistor. The second PMOS transistor has its source coupled to the PAD terminal, its gate coupled to the source of the first PMOS transistor and the power supply voltage terminal, its drain coupled to the substrate control signal terminal, and its substrate coupled to the drain of the second PMOS transistor.

3. The input / output circuit as described in claim 2, characterized in that, The height selection module is configured such that: when the power supply voltage terminal is working normally, the voltage of the substrate control signal terminal is equal to the power supply voltage; when the power supply voltage terminal is powered off and the voltage of the PAD terminal is at the first logic level, the voltage of the substrate control signal terminal is equal to the voltage of the PAD terminal.

4. The input / output circuit as described in claim 1, characterized in that, The control module includes: The first control PMOS transistor has its gate coupled to the power supply voltage terminal, its substrate coupled to the substrate control signal terminal, and its source coupled to the PAD terminal. The first control NMOS transistor has its gate coupled to a power state signal terminal, and its source and substrate coupled to ground potential. The drain of the first control PMOS transistor is coupled to the drain of the first control NMOS transistor to serve as the drive control signal terminal, so as to output the drive control signal.

5. The input / output circuit as described in claim 4, characterized in that, When the power supply voltage terminal is de-energized and the PAD terminal voltage is at the first logic level, the first control PMOS transistor is turned on, the first control NMOS transistor is turned off, and the voltage of the drive control signal terminal is equal to the voltage of the PAD terminal, so as to turn off the switching PMOS transistor. When the power supply voltage terminal is powered on, the first control NMOS transistor is turned on, the first control PMOS transistor is turned off, and the voltage of the drive control signal terminal is at the second logic level to turn on the switching PMOS transistor.

6. The input / output circuit as described in claim 1, characterized in that, The control module includes: The second control PMOS transistor has its substrate coupled to the control signal terminal of the substrate, and its source coupled to the PAD terminal. The second control NMOS transistor has its gate coupled to the power supply voltage terminal, and its source and substrate coupled to ground potential. The drain of the second control PMOS transistor is coupled to the drain of the second control NMOS transistor to serve as the drive control signal terminal, so as to output the drive control signal.

7. The input / output circuit as described in claim 1, characterized in that, The switching module includes a switching PMOS transistor, the gate of which is coupled to a drive control signal terminal, the source of which is coupled to a power supply voltage terminal, the drain of which is coupled to the source of a pull-up PMOS transistor, and the substrate of the switching PMOS transistor and the substrate of the pull-up PMOS transistor are both coupled to the substrate control signal terminal. The switching module is configured to turn off the switching PMOS transistor when the power supply voltage terminal is de-energized and the PAD terminal voltage is at a first logic level.

8. The input / output circuit as described in claim 1, characterized in that, Also includes: An auxiliary module, coupled to the control module, is used to establish an electrical connection path between the substrate control signal terminal and the power supply voltage terminal in response to the drive control signal.

9. The input / output circuit as described in claim 8, characterized in that, The auxiliary module includes: an auxiliary PMOS transistor, the source of which is coupled to the substrate control signal terminal, the gate of which is coupled to the drive control signal terminal, and the drain of which is coupled to the power supply voltage terminal. When the power supply voltage terminal is powered on, the voltage of the drive control signal terminal is at the second logic level, the auxiliary PMOS transistor is turned on, and the voltage of the substrate control signal terminal is equal to the power supply voltage.

10. The input / output circuit as described in claim 1, characterized in that, The input / output module also includes: A pull-down NMOS transistor, the drain of which is coupled to the drain of the pull-up PMOS transistor and the PAD terminal, respectively, and the source of which is coupled to ground potential; The logic module is coupled to the gate of the pull-up PMOS transistor and the gate of the pull-down NMOS transistor, respectively. The logic module is coupled to the input signal terminal. The logic module is configured to generate a pull-up control signal and a pull-down control signal according to the input signal, and transmit the pull-up control signal to the pull-up PMOS transistor and the pull-down control signal to the pull-down NMOS transistor.

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