Method for selectively etching silicon nitride

Abstract

Embodiments of the present disclosure are directed to selective etch processes. The process includes flowing a precursor into a semiconductor processing chamber containing a substrate, the precursor including one or more of an inter-halogen compound, a halogen-containing species, a pseudo-halogen species, a mixture of one or more of the inter-halogen compound, the halogen-containing species, or the pseudo-halogen species and an amine or phosphine, or a mixture of one or more of an inter-halogen compound, a halogen-containing species or a pseudo-halogen species and a sulfur-containing species, and an activating species that forms a precursor to etch the substrate. The substrate has a plurality of alternating layers of silicon oxide and silicon nitride thereon and trenches formed through the plurality of alternating layers. The silicon nitride layer is selectively etched with respect to the silicon oxide layer with an etch selectivity greater than or equal to 500: 1.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the field of semiconductor manufacturing. More particularly, embodiments of the present disclosure relate to selectively etching silicon nitride relative to silicon oxide. BACKGROUND

[0002] Integrated circuits are made possible by processes that create intricate patterned layers of material on a substrate surface. Creating patterned material on a substrate requires a controlled method to remove exposed material. Chemical etching is used for a variety of purposes, including transferring a pattern in a photoresist to an underlying layer, thinning a layer, or thinning lateral dimensions of features already present on a surface. A chemical etching process typically includes a chemical that etches one material faster than another, facilitating, for example, a pattern transfer process. Such an etching process is said to be selective to the first material. Due to the variety of materials, circuits, and processes, etching processes have evolved to be selective to a variety of materials.

[0003] Manufacturing of three-dimensional (3D)-NAND devices includes forming alternating layers of silicon oxide (e.g., Si02) and silicon nitride (e.g., Si3N4). After forming the stack of alternating layers, the silicon nitride layers are selectively etched to form recesses that are eventually filled with a conductor (e.g., tungsten).

[0004] Etching processes can be referred to as "wet" or "dry" based on the materials used in the process. Wet HF etching preferentially removes silicon oxide compared to other dielectrics and materials. However, wet processes can have difficulty penetrating some constrained trenches and can also sometimes distort remaining material. Dry etching, created in a localized plasma within a substrate processing region, can penetrate more constrained trenches and exhibit less distortion of fine remaining structures. However, localized plasma can damage a substrate as it discharges due to arcing. Improved systems and methods are needed that can be used to create high quality devices and structures.

[0005] Currently, wet etching processes are used to selectively remove silicon nitride layers. However, in a drying process after a wet etching process, suspended silicon oxide layers can collapse due to the surface tension of the liquid. This results in yield loss. Another problem with wet etching processes is that as 3D-NAND devices are scaled in the future, the number of layers of silicon oxide and silicon nitride will increase. This is problematic because liquid etchants will have difficulty filling into deeper trenches. This results in non-uniform etching such that the etching of the top of a 3D-NAND structure is different than the etching of the bottom of the 3D-NAND structure.

[0006] Current dry etching techniques also etch silicon and silicon oxide in addition to silicon nitride, thereby reducing the selectivity of such processes. Therefore, improved etching processes that will achieve improved etching selectivity are needed. Summary of the Invention

[0007] One or more embodiments of this disclosure relate to a selective etching method. The selective etching method includes introducing a precursor into a semiconductor processing chamber containing a substrate. The precursor includes one or more of an interhalogen compound, a halogen-containing substance, and a pseudohalogen substance; a mixture of one or more of an interhalogen compound, a halogen-containing substance, or a pseudohalogen substance with an amine or phosphine; or a mixture of one or more of an interhalogen compound, a halogen-containing substance, or a pseudohalogen substance with a sulfur-containing substance. The substrate has multiple alternating layers of silicon oxide and silicon nitride thereon, and trenches formed through the multiple alternating layers. The selective etching method further includes forming an activating material for the precursor and etching the substrate. The silicon nitride layer is selectively etched relative to the silicon oxide layer.

[0008] Additional embodiments of this disclosure relate to a method for selectively etching silicon nitride relative to silicon oxide. The method includes introducing a precursor into a semiconductor processing chamber containing a substrate. The precursor includes one or more of an interhalogen compound, a halogen-containing substance, and a pseudohalogen substance; a mixture of one or more of an interhalogen compound, a halogen-containing substance, or a pseudohalogen substance with an amine or phosphine; or a mixture of one or more of an interhalogen compound, a halogen-containing substance, or a pseudohalogen substance with a sulfur-containing substance. The substrate has a plurality of alternating layers of silicon oxide and silicon nitride thereon, and trenches formed through the plurality of alternating layers. The method further includes forming an activating material for the precursor and etching the substrate. The silicon nitride layer is selectively etched relative to the silicon oxide layer with an etch selectivity greater than or equal to 500:1. In some embodiments, the semiconductor processing chamber is maintained at a pressure in the range of 5 mTorr to 100 Torr and a temperature less than or equal to 500°C. Attached Figure Description

[0009] To gain a more detailed understanding of the features described above in this disclosure, a more specific description of the disclosure, which has been briefly outlined above, can be obtained by referring to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only typical embodiments of this disclosure and should therefore not be construed as limiting its scope, as other equally effective embodiments are permissible. The embodiments described herein are illustrated in the accompanying drawings by way of example rather than limitation, wherein the same element symbols indicate similar elements.

[0010] Figure 1A A cross-sectional view of a portion of a 3D-NAND structure having alternating silicon oxide and silicon nitride layers is illustrated according to one or more embodiments of the present disclosure.

[0011] Figure 1BOne or more embodiments of this disclosure illustrate the process after selectively etching a silicon nitride layer. Figure 1A A cross-sectional view of a portion of a 3D-NAND structure;

[0012] Figure 2 A cross-sectional schematic diagram of a microwave plasma chamber for dry etching 3D-NAND structures is illustrated according to one or more embodiments of this disclosure; and

[0013] Figure 3 A process flow diagram illustrating a method for selectively etching silicon nitride relative to silicon oxide is shown according to one or more embodiments of this disclosure. Detailed Implementation

[0014] Before describing several exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the details of the construction or process steps set forth in the following description. This disclosure can have other embodiments and can be practiced or implemented in various ways.

[0015] As used in this specification and the appended claims, the term "substrate" means a surface or part thereof on which a process is performed. Those skilled in the art will also understand that reference to substrate may also refer to only a portion of a substrate, unless the context clearly indicates otherwise. Furthermore, the reference to deposition on a substrate can mean both a bare substrate and a substrate on which one or more films or features are deposited or formed.

[0016] As used herein, “substrate” (also referred to as “wafer”) means any substrate on which a film treatment is performed during a manufacturing process, or a material surface formed on a substrate. For example, depending on the application, substrate surfaces on which treatments can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulating layer (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor substrates. Substrates may be exposed to pretreatment processes such as polishing, etching, reduction, oxidation, hydroxylation, annealing, UV curing, electron beam curing, and / or baking of the substrate surface. In addition to performing film treatments directly on the surface of the substrate itself, any of the disclosed film treatment steps may also be performed on an underlayer formed on the substrate, as disclosed in more detail below, and the term “substrate surface” is intended to include such an underlayer as indicated by the context. Thus, for example, where a film / layer or a portion of a film / layer has been deposited onto the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0017] As used in this specification and the appended claims, the terms “precursor,” “reactant,” “reactive gas,” and the like are used interchangeably to represent any gaseous substance that can react with the surface of a substrate or with a film formed on the surface of a substrate.

[0018] In the transition from 2D-NAND to 3D-NAND, many process operations have been modified from vertical to horizontal operations. Additionally, as the number of cells formed in 3D-NAND structures increases, the aspect ratios of memory vias and other structures increase, sometimes significantly. During 3D-NAND processing, the stacking of placeholder layers and dielectric materials can form inter-electrode dielectric layers or IPD layers. These placeholder layers allow for various operations to be performed to position the structure before the material is completely removed and replaced with metal. While metallization can be incorporated on one side of the cell structure, operations may have previously been performed on the other side of the structure, such as forming floating gates or charge trapping layers. Although these layers can be formed within memory vias, crosstalk can occur between vertically separated memory cells. One way to reduce this communication is to etch the placeholder material before forming these layers, allowing the dielectric material to further separate individual cell material layers from adjacent cells.

[0019] Fabrication of 3D-NAND devices involves forming alternating layers of silicon oxide and silicon nitride. After the stacking of alternating layers is formed, the silicon nitride layer is selectively etched to form recesses that are ultimately filled with conductors (such as tungsten).

[0020] Currently, wet etching is used to selectively remove the silicon nitride layer. However, during the drying process following wet etching, the suspended silicon oxide layer may collapse due to the surface tension of the liquid. This leads to yield loss. Another problem with wet etching is that the number of silicon oxide and silicon nitride layers will increase as 3D-NAND devices scale up in the future. This is problematic because the liquid etchant will have difficulty filling deeper trenches. This results in non-uniform etching, causing the top of the 3D-NAND structure to be etched differently than the bottom.

[0021] Therefore, wet etching of 3D-NAND structures remains challenging, especially as devices continue to scale to larger stacks that include alternating silicon oxide and silicon nitride layers. In addition to silicon nitride, current dry etching techniques also etch silicon and silicon oxide, thereby reducing the selectivity of this process.

[0022] Embodiments of this disclosure advantageously provide an improved etching process comprising a variety of chemicals that, when performed together in a process cycle, achieve improved etching selectivity.

[0023] Without intending to be bound by theory, it is understood that when implemented together in a process cycle, various chemicals, depending on process parameters, achieve improved uniformity and / or increased etching rate. Those skilled in the art can optimize process parameters to utilize the various chemicals of this disclosure to achieve improved uniformity and / or increased etching rate.

[0024] Embodiments of this disclosure provide etching chemicals, such as precursors, including one or more of interhalogen compounds, halogen-containing substances, or pseudohalogen substances. In some embodiments, a dry etching process is constructed using a precursor including one or more of interhalogen compounds, halogen-containing substances, or pseudohalogen substances. Thus, there is no post-etching drying step that could potentially damage the resulting structure.

[0025] Additional embodiments provide precursors comprising a mixture of etching chemicals and passivating chemicals. In some embodiments, the precursor comprises one or more of an interhalogen compound, a halogen-containing substance, or a pseudohalogen-containing substance together with an amine or a phosphine, or one or more of an interhalogen compound, a halogen-containing substance, or a pseudohalogen-containing substance together with a sulfur-containing substance.

[0026] In embodiments in which the precursors include a mixture of an interhalogen compound and an amine or phosphine, a mixture of an interhalogen compound and a sulfur-containing substance, a mixture of a halogen-containing substance and an amine or phosphine, a mixture of a halogen-containing substance and a sulfur-containing substance, a mixture of a pseudohalogen and an amine or phosphine, or a mixture of a pseudohalogen and a sulfur-containing substance, each of the interhalogen compound, the halogen-containing substance, and the pseudohalogen constitutes an etching chemical, and each of the amine, the phosphine, and the sulfur-containing substance constitutes a passivation chemical.

[0027] Embodiments of this disclosure provide an activating material for forming a precursor. In some embodiments, forming the activating material includes one or more of a thermal process, a plasma that generates the precursor, or heating a substrate to a temperature less than or equal to 500°C using an optical radiation source.

[0028] Embodiments of this disclosure advantageously provide etching chemicals and passivation chemicals that, when implemented together in a process cycle and activated to form an activating material, achieve improved etching selectivity.

[0029] Embodiments of this disclosure are described with the aid of figures illustrating elements (e.g., a portion of a 3D-NAND structure) and processes for forming portions of the 3D-NAND structure according to one or more embodiments of this disclosure. The processes shown are merely illustrative of possible uses of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the illustrated applications.

[0030] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments. It will be apparent to those skilled in the art that the embodiments may be practiced without such specific details. In other instances, known aspects have not been described in detail so as not to unnecessarily obscure the embodiments. Furthermore, it should be understood that the various embodiments shown in the accompanying drawings are illustrative representations and are not necessarily drawn to scale.

[0031] Figure 1A A cross-sectional view of a portion of a 3D-NAND structure with alternating silicon oxide and silicon nitride layers is shown. Figure 1B The diagram illustrates the process after selective etching of the silicon nitride layer. Figure 1A A cross-sectional view of a portion of a 3D-NAND structure.

[0032] In one or more embodiments, the methods described herein are implemented on a 3D structure 100. For example, the 3D structure 100 may be a structure for a 3D-NAND device. The 3D structure 100 includes a substrate 101, such as a polysilicon substrate, wherein polysilicon pillars 102 extend upward from the substrate 101. In one or more embodiments, each pillar 102 is lined with silicon oxide (e.g., SiO2). x )103 and silicon nitride (e.g., Si) X N Y Alternating layers of silicon nitride layer 104 and silicon oxide layer 103. The sidewalls of silicon nitride layer 104 and silicon oxide layer 103 can be exposed by trenches 106 between the layers through pillars 102.

[0033] In some embodiments, the silicon nitride layer 104 is a sacrificial layer. In embodiments where the silicon nitride layer 104 is a sacrificial layer, such as... Figure 1B As shown, the silicon nitride layer 104 is etched away. Removing the silicon nitride layer 104 results in the formation of recesses 105 between the silicon oxide layers 103. In some embodiments, the recesses 105 are then filled with a conductive layer (not shown), which includes any suitable conductive material known to those skilled in the art, such as tungsten (W).

[0034] Advantageously, embodiments of this disclosure utilize etch chemicals that provide high etch selectivity of the silicon nitride layer 104 relative to the silicon oxide layer 103. Embodiments of this disclosure advantageously increase the etch rate of silicon nitride and thereby reduce the time required to etch the silicon nitride layer 104. Embodiments of this disclosure include the use of optical radiation or plasma sources (such as modular microwave sources) to generate activating materials for precursors, which include etch chemicals, and in some embodiments also include passivating chemicals.

[0035] exist Figure 1A and Figure 1BIn this embodiment, structure 100 is shown as suitable for use in 3D-NAND devices. The use of the etching process described herein is particularly advantageous for use in 3D-NAND devices. In one or more embodiments, the etching uniformity in highly scaled 3D-NAND devices (such as in structures with high aspect ratios and numerous silicon nitride layers 104 and silicon oxide layers 103) is substantially uniform at the top and bottom of the structure. Additionally, the etching process of one or more embodiments provides complete removal of the silicon nitride layer 104 without significantly damaging the silicon oxide layer 103. In some embodiments, a passivation chemical forms a passivation layer over the exposed portions of the silicon oxide layer 103 to protect the silicon oxide layer 103. As used herein, each of amines, phosphine, and sulfur-containing substances may be independently referred to as "passivation chemistry" or "passivating chemistry". In specific embodiments, the etching process of one or more embodiments provides complete removal of the silicon nitride layer 104 without damaging the silicon oxide layer 103 thereon with the passivation layer.

[0036] Those skilled in the art will understand that embodiments of this disclosure are not limited to etching of 3D-NAND structures. For example, a similar etching process can be used wherever it is necessary to selectively etch a silicon nitride structure relative to a silicon oxide layer. For instance, a silicon nitride layer may be provided over the silicon oxide layer, wherein the disclosed etching process etches through the silicon nitride layer and terminates on the oxide layer. In such embodiments, the silicon oxide layer can be considered as an etching termination layer.

[0037] While examples of specific semiconductor device architectures that benefit from the use of plasma sources (such as modular microwave sources) to generate microwave plasmas of precursors are provided, those skilled in the art will understand that the examples provided are non-limiting and that many different applications and architectures may exist that benefit from the etch chemicals and passivation chemicals according to one or more embodiments herein.

[0038] Figure 2 A cross-sectional view of a processing tool 280 (e.g., a microwave plasma chamber) including component 270 is illustrated according to one or more embodiments of this disclosure.

[0039] Those skilled in the art will understand that while this disclosure refers to a microwave plasma chamber, any remote plasma source, inductively coupled plasma (ICP) source, capacitively coupled plasma (CCP) source, or microwave plasma source may be implemented in the disclosed process.

[0040] In some embodiments, the processing tool 280 includes a processing chamber 278 sealed by component 270. For example, component 270 may abut against one or more O-rings 281 to provide a vacuum seal to the chamber space 283 of the processing chamber 278. In other embodiments, component 270 is interface-connected to the processing chamber 278. In other words, in some embodiments, component 270 may be part of a cover sealing the processing chamber 278. In some embodiments, a chuck 279, such as an electrostatic chuck, may support a workpiece 274 (e.g., a wafer, substrate, etc.).

[0041] In some embodiments, component 270 may include a monolithic source array 250, a housing 272, and a cover plate 276. The monolithic source array 250 may include a dielectric plate 260 and a plurality of protrusions 266 extending upward from the dielectric plate 260. Although the monolithic source array 250 is shown, it should be understood that the protrusions 266 may differ from the dielectric plate 260. The protrusions 266 may be insulating bodies located on top of the dielectric plate 260. In some embodiments, there may be five or more protrusions 266, or ten or more protrusions 266. In some embodiments, there are 19 protrusions 266.

[0042] The protrusion 266 may comprise any suitable material known to a person skilled in the art. In some embodiments, the protrusion 266 comprises a dielectric material. In some embodiments, the protrusion 266 serves as a dielectric resonator to couple microwaves into the cavity space 283. In some embodiments, as used herein, the protrusion 266 may be referred to as an “applier” or a “plasma applier” or a “microwave applier.”

[0043] In some embodiments, housing 272 includes an opening sized to receive protrusion 266. Housing 272 may be made of a conductive material. In some embodiments, housing 272 is grounded. Figure 2 In the illustrated embodiment, housing 272 is directly supported by dielectric plate 260; however, it should be understood that a thermal interface material or the like may separate housing 272 from dielectric plate 260. In some embodiments, monopole antenna 268 may extend into a hole in protrusion 266. In some embodiments, the hole in protrusion 266 is larger than monopole antenna 268 to allow thermal expansion in order to prevent damage to monolithic source array 250. In some embodiments, monopole antenna 268 extends through housing 272 and cover plate 276 over protrusion 266. In one or more embodiments, each of monopole antennas 268 is coupled to a different power source. Those skilled in the art will appreciate that the power source may have any suitable configuration.

[0044] Chamber space 283 is adapted to ignite plasma 282. In other words, chamber space 283 may be a vacuum chamber. In some embodiments, a vacuum source may be fluidly coupled to chamber space 283. To ignite plasma 282, a process gas may flow into chamber space 283. The process gas may enter assembly 270 via one or more gas lines 218. The process gas then enters housing 272 via orifice 235 through orifice 214 through cover plate 276. Orifice 235 intersects with gas distribution channel 230 for laterally distributing process gas. Although shown as a plurality of discrete gas distribution channels 230, those skilled in the art will understand that the gas distribution channels 230 are in Figure 2 They are fluidly coupled to each other outside the plane.

[0045] The process gas exits the channel 230 through a group 232 of holes 237 in the cover above the channel 230. The process gas then enters the chamber space 283 through gas distribution holes 263 passing through the dielectric plate 260 of the monolithic source array 250.

[0046] In some embodiments, the processing tool 280 includes components configured to generate optical radiation. Those skilled in the art will appreciate that any optical radiation source suitable for generating optical radiation can be implemented for the disclosed process.

[0047] In one or more embodiments not shown, the processing tool 280 includes a cover on top of the processing chamber 278. In some embodiments, the cover includes an optical radiation lamp that generates optical radiation. In one or more embodiments not shown, the processing tool 280 includes a loading locking chamber that includes an optical radiation lamp that generates optical radiation.

[0048] Figure 3 A process flow diagram of a method 300 for selectively etching silicon nitride relative to silicon oxide is illustrated according to one or more embodiments of the present disclosure.

[0049] In some embodiments, method 300 includes a pretreatment operation (not shown). Pretreatment may include any suitable pretreatment method known to a person skilled in the art. Suitable pretreatment processes include, but are not limited to, preheating, cleaning, soaking, metal oxidation, or depositing a protective layer to block the bottom of the trench.

[0050] In some embodiments, method 300 is a selective etching method for a 3D structure. The 3D structure may be a 3D-NAND structure, or more specifically, an intermediate structure for manufacturing a 3D-NAND structure. In some embodiments, the 3D structure is as described above... Figure 1A The described structure. Although a specific 3D structure is described as an example, those skilled in the art will understand that any architecture with silicon nitride and oxide layers can be provided in the processing chamber according to various embodiments.

[0051] In some embodiments, method 300 begins at operation 310, which includes flowing a precursor into a semiconductor processing chamber containing a substrate. In some embodiments, the precursor includes an etching chemical substance, which includes one or more of an interhalogen compound, a halogen-containing substance, or a pseudohalogen substance. In some embodiments, the etching chemical substance includes a mixture of an interhalogen compound and a halogen-containing substance, a mixture of an interhalogen compound and a pseudohalogen substance, or a mixture of a halogen-containing substance and a pseudohalogen substance.

[0052] In some embodiments, the precursor includes a mixture of one or more of an interhalogen compound, a halogenated substance or a pseudohalogenated substance with an amine or a phosphine, or a mixture of one or more of an interhalogen compound, a halogenated substance or a pseudohalogenated substance with a sulfur-containing substance.

[0053] In a specific embodiment, the precursor comprises a mixture of an interhalogenated compound and an amine or phosphine. In a specific embodiment, the precursor comprises a mixture of an interhalogenated compound and a sulfur-containing substance.

[0054] In a specific embodiment, the precursor includes a mixture of a halogen-containing substance and an amine or phosphine. In a specific embodiment, the precursor includes a mixture of a halogen-containing substance and a sulfur-containing substance.

[0055] In a specific embodiment, the precursor includes a mixture of a pseudohalogen and an amine or phosphine. In a specific embodiment, the precursor includes a mixture of a pseudohalogen and a sulfur-containing substance.

[0056] As used herein, the term "interhalogen compound" refers to a substance comprising two or more distinct halogen atoms and excluding atoms or elements from any other group in the periodic table. Interhalogen compounds may include any suitable interhalogen compounds known to those skilled in the art as described herein. In some embodiments, interhalogen compounds include one or more of chlorine trifluoride (ClF3), bromine trifluoride (BrF3), bromine pentafluoride (BrF5), iodine trifluoride (IF3), iodine pentafluoride (IF5), iodine monobromide (IBr), or iodine monochloride (ICl).

[0057] In one or more embodiments, the halogen-containing substance includes one or more of fluorine (F2), bromine (Br2), chlorine (Cl2), iodine (I2), boron trifluoride (BF3), or boron trichloride (BCl3).

[0058] In one or more embodiments, the pseudohalogen substance comprises one or more of isocyano, thioalkyl, cyanate, isocyanate, thiocyanate, or isothiocyanate. The pseudohalogen substance may include any suitable compound comprising one or more of isocyano, thioalkyl, cyanate, isocyanate, thiocyanate, or isothiocyanate. In some embodiments, the pseudohalogen substance comprising one or more of isocyano, thioalkyl, cyanate, isocyanate, thiocyanate, or isothiocyanate further comprises alkyl groups, including but not limited to acyclic groups, such as straight-chain alkyl or branched-chain alkyl, and cyclic alkyl groups.

[0059] In one or more specific embodiments, the pseudohalogen substance including the isocyanate group is (Tri-butyl isocyanate). In one or more specific embodiments, the pseudohalogenating substance comprising a thioalkyl group is hydrogen sulfide (H2S).

[0060] In one or more specific embodiments, the pseudohalogen substance comprising the isocyanate group is (1-Propyl isocyanate).

[0061] In one or more specific embodiments, the pseudohalogenated substance including the thiocyanate group is H3CSCN (methyl thiocyanate).

[0062] In one or more specific embodiments, the pseudohalogen substance including the isothiocyanate group is H3CH2CNCS (ethyl isocyanate).

[0063] In some embodiments, the precursor flowing at operation 310 includes etching chemicals and passivating chemicals. In embodiments in which the precursor includes a mixture of an interhalogen compound and an amine or phosphine, a mixture of an interhalogen compound and a sulfur-containing substance, a mixture of a halogen-containing substance and an amine or phosphine, a mixture of a halogen-containing substance and a sulfur-containing substance, a mixture of a pseudohalogen and an amine or phosphine, or a mixture of a pseudohalogen and a sulfur-containing substance, each of the interhalogen compound, the halogen-containing substance, and the pseudohalogen constitutes an etching chemical, and each of the amine, the phosphine, and the sulfur-containing substance constitutes a passivating chemical.

[0064] The amine or phosphine may comprise any suitable compound known to those skilled in the art containing an amine group and / or a phosphine group. In one or more embodiments, the amine comprises one or more of diethylamine or triethylamine. In one or more embodiments, the phosphine comprises alkylphosphine, such as methylphosphine.

[0065] In one or more embodiments, the sulfur-containing substance includes one or more of hydrogen sulfide (H2S) or carbon disulfide (CS2). In one or more embodiments, the sulfur-containing substance includes disulfide-bonded molecules. In some embodiments, the disulfide-bonded molecules include... (Dimethyl disulfide) (Disulfide dichloride) or One or more of (disulfur tetrachloride).

[0066] In method 300, at operation 310, an etching chemical etches a silicon nitride layer 104 relative to a silicon oxide layer 103. In some embodiments, a passivation chemical forms a passivation layer over exposed portions of the silicon oxide layer 103 to protect the silicon oxide layer 103. In other words, the passivation chemical can be provided without etching the structure. In some embodiments, the passivation chemical promotes healing of the etched surface. In some embodiments, the passivation chemical restricts, prevents, or regenerates silicon oxide, thereby maintaining the silicon oxide layer 103 during the etching chemical process.

[0067] In a specific embodiment, one or more of the interhalogen compound, halogen-containing substance or pseudohalogen substance etch the silicon nitride layer 104 relative to the silicon oxide layer 103, and one or more of the amine, phosphine or sulfur-containing substance independently form a passivation layer on the exposed portion of the silicon oxide layer 103 to protect the silicon oxide layer 103.

[0068] In some embodiments, at operation 320, method 300 includes forming an activating substance (e.g., a free radical) that forms a precursor.

[0069] Without intending to be bound by any particular theory, it is believed that etching chemicals and passivation chemicals contribute to their effectiveness by using activating substances that form precursors to carry out the corresponding chemicals.

[0070] It has been advantageously discovered that the activating material forming the precursor weakens the underlying bonds of the silicon nitride layer 104, thereby allowing the removal of the silicon nitride layer 104.

[0071] In some embodiments, forming the activating material includes one or more of the following: a thermal process, a plasma process for generating precursors, or heating the substrate to a temperature of less than or equal to 500°C using an optical radiation source.

[0072] Thermal processes may include any suitable process known to a technician that does not employ plasma.

[0073] The precursor plasma can be generated using any suitable plasma source. In one or more embodiments, a remote plasma source, an inductively coupled plasma (ICP) source, a capacitively coupled plasma (CCP) source, or a microwave plasma source can be used to generate the precursor plasma.

[0074] Those skilled in the art will understand that any remote plasma source, inductively coupled plasma (ICP) source, capacitively coupled plasma (CCP) source, or microwave plasma source suitable for generating plasma can be implemented for the disclosed process.

[0075] One or more embodiments of this disclosure include modular microwave plasma processing tools, such as processing tool 280, for selectively etching silicon nitride relative to silicon oxide. The modular microwave plasma source has a high plasma density and a very low plasma potential (e.g., less than or equal to 10 eV). Compared to a typical inductively coupled plasma (ICP) source (as an example) with a higher plasma potential (e.g., greater than or equal to about 20 eV), the high plasma density and low plasma potential result in less sputtering damage to the etched structure.

[0076] One or more embodiments of this disclosure use an optical radiation source to heat the substrate to a temperature of less than or equal to 500°C. As used herein, the term "optical radiation" includes ultraviolet (UV) wavelengths, visible wavelengths, and infrared (IR) wavelengths in the electromagnetic spectrum. In one or more embodiments, the IR radiation used has a wavelength in the range of 780 nm to 1 mm. In one or more embodiments, the UV-visible radiation has a wavelength in the range of 190 nm to 900 nm.

[0077] Optical radiation can be generated by any suitable source known to a person skilled in the art. In some embodiments, the optical radiation used to activate the precursor is UV radiation, visible light radiation, or IR radiation. In some embodiments, the optical radiation used to activate the precursor is UV radiation.

[0078] Method 300 includes flowing the precursor (operation 310) and forming an activating material (e.g., free radical) of the precursor (operation 320) to advantageously etch the silicon nitride layer 104 relative to the silicon oxide layer 103 with improved etch selectivity (operation 330, which includes operations 310 and 320).

[0079] In some embodiments, during the formation of the activating material, the semiconductor processing chamber is maintained at a pressure ranging from 5 mTorr to 100 Torr. In some embodiments, during the formation of the activating material, the pressure is in the range of 5 mTorr to 20 Torr, in the range of 5 mTorr to 10 Torr, or in the range of 5 mTorr to 5 Torr. In some embodiments, during the formation of the activating material, the semiconductor processing chamber is maintained at a temperature of less than or equal to 500°C.

[0080] In some embodiments, the distance between the plasma source and the substrate having a 3D structure may be less than or equal to 5 inches (12.7 cm), less than or equal to 1 inch (2.54 cm), less than or equal to 0.25 inches (0.635 cm), or less than or equal to 0.1 inches (0.254 cm). In some embodiments, the plasma may be generated from multiple plasma applicators, such as... Figure 2 The structure shown.

[0081] In some embodiments, the microwave power source provides microwave plasma at a power of at least 50 watts per cycle. In some embodiments, method 300 is repeated, and multiple cycles of providing microwave plasma are performed. In some embodiments, method 300 is repeated until the microwave power source provides a total delivery power of 1500 watts. In some embodiments, method 300 is repeated until the microwave power source provides a total delivery power of 2250 watts. In some embodiments, method 300 is repeated until the microwave power source provides a total delivery power of 2850 watts. In some embodiments, method 300 is repeated until the microwave power source provides a total delivery power of 5000 watts. Therefore, the total delivery power from the microwave power source is in the range of 50 watts to 5000 watts.

[0082] In some embodiments, the distance between the optical radiation source and the substrate having a 3D structure may be less than or equal to 5 inches (12.7 cm), less than or equal to 1 inch (2.54 cm), less than or equal to 0.25 inches (0.635 cm), or less than or equal to 0.1 inches (0.254 cm).

[0083] In some embodiments, method 300 includes flowing the precursor and forming an activating material of the precursor (operations 310 and 320) for a time period ranging from 5 seconds to 10 minutes. In some embodiments, method 300 may include purifying the precursor and the activating material of the precursor (not shown) in the semiconductor processing chamber.

[0084] As used herein, purging a semiconductor processing chamber removes unreacted precursors, gas mixtures, reaction products, and byproducts. For example, in a spatially separated sector of a processing chamber, a portion of the processing chamber adjacent to the substrate surface is purged of unreacted precursors by any suitable technique, including but not limited to moving the substrate via a gas curtain to a portion or sector of the processing chamber (containing no or substantially no precursors). In one or more embodiments, purging the processing chamber includes applying a vacuum. In some embodiments, purging the processing chamber includes flowing a purging gas across the substrate. In some embodiments, a portion of the processing chamber refers to a micro-volume or small-volume process station within the processing chamber. The term “adjacent” as used to refer to the substrate surface means the physical space immediately adjacent to the substrate surface, which provides sufficient space for surface reactions (e.g., precursor adsorption) to occur.

[0085] In one or more embodiments, the purifying gas includes one or more of argon (Ar), helium (He), krypton (Kr), neon (Ne), xenon (Xe), hydrogen (H2), oxygen (O2), or nitrogen (N2). In some embodiments, purifying the semiconductor processing chamber includes a time period in the range of 0.5 seconds to 10 minutes for purifying the gas (e.g., helium (He)) to flow across the substrate.

[0086] In one or more embodiments, method 300 includes a cyclic process: flowing the precursor (operation 310), purging, forming an activating substance of the precursor (operation 320), purging, and then continuing method 300.

[0087] In some embodiments, method 300 involves one or more of an interhalogen compound, a halogen-containing substance, or a pseudohalogen substance flowing sequentially or in a co-current manner (operation 310), purging, forming an activating material for the precursor (operation 320), purging again, and then continuing method 300. In one or more embodiments, one or more of the interhalogen compound, halogen-containing substance, or pseudohalogen substance flows at operation 310, is activated at operation 320, and is used at operation 330 to selectively etch silicon nitride relative to silicon oxide without purging.

[0088] In embodiments where the precursor comprises a mixture of an interhalogen compound and an amine or phosphine, the interhalogen compound and the amine or phosphine may flow sequentially or co-flow. In embodiments where the precursor comprises a mixture of an interhalogen compound and an amine or phosphine, the interhalogen compound and the amine or phosphine may flow without purification. In one or more embodiments, method 300 includes flowing the interhalogen compound, purifying it, flowing the amine or phosphine, purifying it, and then continuing method 300.

[0089] In embodiments where the precursor comprises a mixture of interhalogen compounds and sulfur-containing substances, the interhalogen compounds and sulfur-containing substances may flow sequentially or co-flow. In embodiments where the precursor comprises a mixture of interhalogen compounds and sulfur-containing substances, the interhalogen compounds and sulfur-containing substances may flow without purification. In one or more embodiments, method 300 includes flowing the interhalogen compound, purifying it, flowing the sulfur-containing substance, purifying it, and then continuing method 300.

[0090] In embodiments where the precursor comprises a mixture of a halogenated substance and an amine or phosphine, the halogenated substance and the amine or phosphine may flow sequentially or co-flow. In embodiments where the precursor comprises a mixture of a halogenated substance and an amine or phosphine, the halogenated substance and the amine or phosphine may flow without purification. In one or more embodiments, method 300 includes flowing the halogenated substance, purifying it, flowing the amine or phosphine, purifying it, and then continuing method 300.

[0091] In embodiments where the precursor comprises a mixture of a halogen-containing substance and a sulfur-containing substance, the halogen-containing substance and the sulfur-containing substance may flow sequentially or in a co-current manner. In embodiments where the precursor comprises a mixture of a halogen-containing substance and a sulfur-containing substance, the halogen-containing substance and the sulfur-containing substance may flow without purification. In one or more embodiments, method 300 includes flowing the halogen-containing substance, purifying it, flowing the sulfur-containing substance, purifying it, and then continuing method 300.

[0092] In embodiments where the precursor comprises a mixture of a pseudohalogen and an amine or phosphine, the pseudohalogen and the amine or phosphine may flow sequentially or co-flow. In embodiments where the precursor comprises a mixture of a pseudohalogen and an amine or phosphine, the pseudohalogen and the amine or phosphine may flow without purification. In one or more embodiments, method 300 includes flowing the pseudohalogen, purifying, flowing the amine or phosphine, purifying, and then continuing method 300.

[0093] In embodiments where the precursor comprises a mixture of pseudohalogen and sulfur-containing substances, the pseudohalogen and sulfur-containing substances may flow sequentially or co-flow. In embodiments where the precursor comprises a mixture of pseudohalogen and sulfur-containing substances, the pseudohalogen and sulfur-containing substances may flow without purification. In one or more embodiments, method 300 includes flowing the pseudohalogen, purifying it, flowing the sulfur-containing substance, purifying it, and then continuing method 300.

[0094] In some embodiments, at operation 330, method 300 includes selective etching of a substrate. Operation 330 includes the processes described in operations 310 and 320, which, when performed together in a process cycle, achieve improved etch selectivity.

[0095] In one or more embodiments, the etching selectivity of silicon nitride relative to silicon oxide is greater than or equal to 500:1, greater than or equal to 700:1, greater than or equal to 1000:1, greater than or equal to 1200:1, or greater than or equal to 1600:1.

[0096] In some embodiments (such as when the substrate is) Figure 1A (As shown in the substrate 101), the substrate 101 has a plurality of alternating layers of silicon oxide 103 and silicon nitride 104 thereon, and trenches 106 formed via the plurality of alternating layers. In some embodiments, at operation 350, the silicon nitride layer 104 is selectively etched relative to the silicon oxide layer 103.

[0097] It can be argued that method 300 improves etching uniformity in significantly scaled 3D-NAND devices, such as structures with high aspect ratios and numerous silicon nitride layers 104 and silicon oxide layers 103, such that etching is substantially uniform at the top and bottom of the structure. The etching process of one or more embodiments advantageously provides complete removal of the silicon nitride layer 104 without significantly damaging the silicon oxide layer 103. For example, the etching rate of silicon nitride at the top of the 3D NAND structure can be substantially similar to the etching rate of silicon nitride at the bottom of the 3D NAND structure. In some embodiments, the ratio of the etching rates of silicon nitride between the top and bottom of the structure can be in the range of about 5:1 to about 1:1.

[0098] Those skilled in the art will understand that the etching temperatures (i.e., substrate temperatures) of the embodiments disclosed herein can be considered as low-temperature processes. In some embodiments, maintaining the semiconductor processing chamber at temperatures less than or equal to 500°C, less than or equal to 400°C, less than or equal to 300°C, less than or equal to 200°C, less than or equal to 100°C, less than or equal to 50°C, less than or equal to 0°C, less than or equal to -50°C, or less than or equal to -100°C. Those skilled in the art will understand that maintaining the semiconductor chamber at temperatures less than or equal to 100°C (such as in the range of less than or equal to 100°C to less than or equal to -100°C) will require the implementation of additional processing equipment, such as a cryogenic chamber.

[0099] Although method 300 is described as including discrete processing operations (operations 310-320) to selectively etch the substrate at operation 330, this disclosure is not limited thereto. For example, method 300 may include any combination of various chemical substances (etching chemicals and passivation chemicals).

[0100] One or more embodiments of this disclosure relate to a non-transitory computer-readable medium that includes instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform one or more of the illustrated and unillustrated operations of the method 300 described herein.

[0101] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms are used herein to describe the relationship between one element or feature and another (additional) element or feature as illustrated in the figures. It should be understood that, in addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of elements in use or operation. For example, if an element in one of the figures is flipped, an element described as “below” or “under” another element or feature would then be oriented “above” that element or feature. Thus, the exemplary term “below” can cover both above and below orientations. Elements may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein will be interpreted accordingly.

[0102] Unless otherwise indicated herein or clearly contradicted by the context, the terms “a”, “an”, and “the,” and similar pronouns used in the context of describing the materials and methods discussed herein (particularly in the context of the following claims) should be construed as covering both the singular and plural. Unless otherwise indicated herein, descriptions of value ranges herein are intended only as a shortened form of referring individually to each individual value within that range, and each individual value is incorporated into the specification as if it were described separately herein. Unless otherwise indicated herein or clearly contradicted by the context, all methods described herein may be performed in any suitable order. Unless otherwise asserted, the use of any and all examples or exemplary language (e.g., “such as”) provided herein is intended only to better illustrate the materials and methods and does not impose any limitation on the scope. No language in the specification should be construed as indicating that any unclaimed element is essential to the practice of the disclosed materials and methods.

[0103] Throughout this specification, references to "an embodiment," "some embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. Therefore, the appearance of phrases such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in one embodiment" throughout this specification does not necessarily represent the same embodiment of this disclosure. In one or more embodiments, a particular feature, structure, material, or characteristic is combined in any suitable manner.

[0104] Although the disclosure herein has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of this disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatus of this disclosure without departing from the spirit and scope of this disclosure. Therefore, it is contemplated that this disclosure includes modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A selective etching method, comprising the following steps: A precursor is introduced into a semiconductor processing chamber containing a substrate. The precursor includes one or more of an interhalogen compound, a halogen-containing substance, and a pseudohalogen substance; a mixture of one or more of the interhalogen compound, the halogen-containing substance, or the pseudohalogen substance with an amine or phosphine; or a mixture of one or more of the interhalogen compound, the halogen-containing substance, or the pseudohalogen substance with a sulfur-containing substance. The substrate has a plurality of alternating layers of silicon oxide and silicon nitride thereon and trenches formed through the plurality of alternating layers. The activating substance that forms the precursor; as well as The substrate is etched, wherein the silicon nitride layer is selectively etched relative to the silicon oxide layer.

2. The method of claim 1, wherein the interhalogen compound comprises one or more of chlorine trifluoride (ClF3), bromine trifluoride (BrF3), bromine pentafluoride (BrF5), iodine trifluoride (IF3), iodine pentafluoride (IF5), iodine monobromide (IBr), or iodine monochloride (ICl).

3. The method of claim 1, wherein the halogen-containing substance includes fluorine (F2), bromine (Br2), and chlorine (Cl). 2) One or more of iodine (I2), boron trifluoride (BF3), or boron trichloride (BCl3).

4. The method of claim 1, wherein the sulfur-containing substance comprises disulfide-bonded molecules.

5. The method of claim 4, wherein the disulfide bonded molecule comprises (Dimethyl disulfide) (Disulfide dichloride) or One or more of (disulfur tetrachloride).

6. The method of claim 1, wherein the pseudohalogen substance comprises one or more of isocyanate, thioalkyl, cyanate, isocyanate, thiocyanate, or isothiocyanate.

7. The method of claim 1, wherein the step of forming the activating material comprises one or more of a thermal process, generating plasma of the precursor, or heating the substrate to a temperature less than or equal to 500°C using an optical radiation source.

8. The method of claim 7, wherein the plasma is generated by one or more of a microwave plasma source, a remote plasma source, an inductively coupled plasma (ICP) source, or a capacitively coupled plasma (CCP) source.

9. The method of claim 7, wherein the activating substance is generated by UV radiation.

10. The method of claim 1, wherein the step of flowing the precursor, which is the mixture of the interhalogen compound and the amine or the phosphine, the mixture of the halogen-containing substance and the amine or the phosphine, or the mixture of the pseudohalogen substance and the amine or the phosphine, comprises the following steps: The substrate is sequentially exposed to the interhalogen compound, the halogen-containing substance or the pseudohalogen, and the amine or the phosphine.

11. The method of claim 1, wherein the step of flowing the precursor of the mixture of the interhalogen compound and the sulfur-containing substance, the mixture of the halogen-containing substance and the sulfur-containing substance, or the mixture of the pseudohalogen and the sulfur-containing substance comprises the following steps: The substrate is sequentially exposed to the interhalogen compound, the halogen-containing substance or the pseudohalogen, and the sulfur-containing substance.

12. The method of claim 1, wherein the etching selectivity of silicon nitride relative to silicon oxide is greater than or equal to 500:

1.

13. The method of claim 1, wherein the semiconductor processing chamber is maintained at a pressure ranging from 5 millitor to 100 tort.

14. The method of claim 1, wherein the semiconductor processing chamber is maintained at a temperature of less than or equal to 500°C.

15. The method of claim 1, further comprising the following steps: The semiconductor processing chamber is purified by using a purifying gas.

16. The method of claim 15, wherein the purifying gas comprises one or more of argon (Ar), helium (He), krypton (Kr), neon (Ne), xenon (Xe), hydrogen (H2), oxygen (O2), or nitrogen (N2).

17. A method for selectively etching silicon nitride relative to silicon oxide, the method comprising the steps of: A precursor is introduced into a semiconductor processing chamber containing a substrate. The precursor includes one or more of an interhalogen compound, a halogen-containing substance, and a pseudohalogen substance; a mixture of one or more of the interhalogen compound, the halogen-containing substance, or the pseudohalogen substance with an amine or phosphine; or a mixture of one or more of the interhalogen compound, the halogen-containing substance, or the pseudohalogen substance with a sulfur-containing substance. The substrate has a plurality of alternating layers of silicon oxide and silicon nitride thereon and trenches formed through the plurality of alternating layers. The activating substance that forms the precursor; as well as The substrate is etched, wherein the silicon nitride layer is selectively etched relative to the silicon oxide layer with an etch selectivity greater than or equal to 500:1, and the semiconductor processing chamber is maintained at a pressure ranging from 5 mTorr to 100 Torr and a temperature less than or equal to 500°C.

18. The method of claim 17, wherein the step of forming the activating material comprises one or more of a thermal process, a plasma process for forming the precursor, or heating the substrate to a temperature less than or equal to 500°C using an optical radiation source.

19. The method of claim 18, wherein the plasma is generated by one or more of a microwave plasma source, a remote plasma source, an inductively coupled plasma (ICP) source, or a capacitively coupled plasma (CCP) source.

20. The method of claim 18, wherein the activating substance is generated by UV radiation.

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