Memory management method and memory controller

Abstract

The invention provides a memory management method and a memory controller. The method is applied to a memory controller, and in response to a failure of a read operation performed on a physical page, a voltage offset identification operation is performed on the physical page to obtain an offset attribute, and the offset attribute is used for indicating a main offset trend of a critical voltage distribution of the physical page. And recording an offset attribute of the entity page, and obtaining target data and a data attribute corresponding to the target data based on the write-in instruction. And according to the data attribute of the target data, selecting a target entity page of which the offset attribute corresponds to the data attribute from a plurality of entity pages of the memory module, so as to write the target data into the target entity page. The method can allocate the storage entities according to the actual offset condition of the storage unit, prolong the service life of the memory and improve the data reliability.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of memory, in particular to a memory management method based on critical voltage shift identification and a memory controller. BACKGROUND

[0002] Flash memory, as a kind of non-volatile storage medium, is used as the core component of storage devices in various electronic devices due to its high storage density, low power consumption and fast read speed. However, the physical characteristics of flash memory also bring its inherent limitations.

[0003] The storage principle of flash memory is based on the amount of charge captured by the floating gate in the memory cell. By injecting or removing electrons from the floating gate, the threshold voltage (Vth) of the memory cell can be changed, thereby representing different data states. As the storage device is used, the program / erase (P / E) operations of the flash memory will continue to accumulate, which will cause wear to the physical structure of the memory cell, resulting in the distribution of its threshold voltage becoming unstable, i.e. the so-called "Vth shift".

[0004] Vth shift usually exhibits two main trends. One is that the threshold voltage tends to decrease, also known as "left shift". This is usually due to the decrease in the charge retention capability of the floating gate, causing electrons to gradually drain. This trend can cause data retention problems, and for "cold data" that needs to be stored for a long time, there is a risk of data loss. The other is that the threshold voltage tends to increase, also known as "right shift". This is usually due to the generation of electron traps in the tunnel oxide layer, causing too many electrons to be captured during the programming operation. This trend can make the memory cell more susceptible to programming operations of adjacent cells, i.e. program disturb errors, affecting the accuracy of data writing.

[0005] When the number of memory cells with Vth shift increases in the storage device, the controller needs to rely more frequently on error correction code (ECC) mechanisms to correct data. This not only increases the delay and power consumption of the read operation, but when the number of error bits exceeds the correction capability of the ECC, it will cause unrecoverable data read failure. SUMMARY

[0006] Therefore, the present disclosure provides a memory management method and a memory controller. The method can dynamically identify the critical voltage offset trend of a storage entity (e.g., an entity page), and perform targeted storage management based on the trend, so that the entity pages with different offset properties are used to store suitable data, thereby maintaining the reliability of the data and improving the problem of reduced reliability and shortened service life of the storage device caused by the inability to differentiate the management of storage units with different aging characteristics in the prior art.

[0007] The one or more embodiments of the present disclosure provide a memory management method applied to a memory controller. The memory controller is used to control a storage device configured with a memory module. The memory module includes a plurality of entity pages. The method includes: in response to a read failure operation performed by a certain entity page of the plurality of entity pages in the memory module, performing a voltage offset identification operation on the entity page to obtain an offset property of the entity page; recording the offset property of the entity page in an offset entity page list; based on a write instruction, obtaining target data and a data property corresponding to the target data; and selecting a target entity page corresponding to the data property from the plurality of entity pages of the memory module according to the data property of the target data, so as to write the target data to the target entity page.

[0008] The one or more embodiments of the present disclosure provide a memory controller used to control a storage device configured with a memory module. The memory module includes a plurality of entity pages. The memory controller includes: a memory interface control circuit electrically connected to the memory module; and a processor electrically connected to the memory interface control circuit. The processor is configured to: in response to a read failure operation performed by a certain entity page of the plurality of entity pages in the memory module, perform a voltage offset identification operation on the entity page to obtain an offset property of the entity page; record the offset property of the entity page in an offset entity page list; based on a write instruction, obtain target data and a data property corresponding to the target data; and select a target entity page corresponding to the data property from the plurality of entity pages of the memory module according to the data property of the target data, so as to write the target data to the target entity page.

[0009] Based on the above, the memory management method and the memory controller provided by the present disclosure can achieve the following technical effects.

[0010] Through the voltage offset identification operation triggered in response to the read operation failure, the present disclosure can accurately obtain the critical voltage offset property of the entity page, and provide reliable basic data for subsequent intelligent storage allocation. This identification mechanism triggered based on actual failure avoids unnecessary detection overhead and improves system efficiency.

[0011] Further, the disclosure records the offset attribute of the entity page, so that the system can make decisions based on the offset attribute of the entity page in real time, and select the target entity page with the corresponding offset attribute according to the data attribute of the target data to store the target data, so that the disclosure realizes intelligent matching of data characteristics and storage area characteristics, thereby effectively utilizing the aged entity page to store suitable data. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a block schematic diagram of a host system and a storage device according to an embodiment of the disclosure;

[0013] Figure 2 is a flowchart of a memory management method according to an embodiment of the disclosure;

[0014] Figure 3 is a flowchart of a voltage offset identification operation according to an embodiment of the disclosure;

[0015] Figure 4 is a schematic diagram of a critical voltage distribution of a single-level cell (SLC) according to an embodiment of the disclosure;

[0016] Figure 5 is a schematic diagram of a critical voltage distribution of a multi-level cell (MLC) according to an embodiment of the disclosure;

[0017] Figure 6 is a schematic diagram of a critical voltage offset according to an embodiment of the disclosure;

[0018] Figure 7 is a flowchart of data write matching according to an embodiment of the disclosure;

[0019] Figure 8 is a flowchart of a data write matching method according to another embodiment of the disclosure;

[0020] Figure 9 is a schematic diagram showing offset inventory management according to an embodiment of the disclosure;

[0021] Figure 10 is a flowchart of a data write method based on an offset entity block inventory according to an embodiment of the disclosure. DETAILED DESCRIPTION

[0022] Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the drawings and the description to refer to the same or like parts.

[0023] Figure 1FIG. 1 shows a block diagram of a host system and a storage device according to an embodiment of the present disclosure. Please refer to FIG. 1. Figure 1 The host system 10 is, for example, a personal computer, a notebook computer, a server. The host system 10 includes a processor 110 (also referred to as a second processor) and a host memory 120 (also referred to as a host internal memory), a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled to (also referred to as electrically connected to) the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120 and the data transfer interface circuit 130 are electrically connected to each other by a system bus. In this embodiment, the processor 110, the host memory 120 and the data transfer interface circuit 130 can be disposed on a host board of the host system 10.

[0024] The storage device 20 includes a memory controller 210, a memory module 220 (also referred to as a rewritable non-volatile memory module), a connection interface circuit 230. The memory controller 210 includes a processor 211 (also referred to as a first processor), a data management circuit 212, a memory interface control circuit 213 and a buffer memory 214.

[0025] In this embodiment, the host system 10 is electrically connected to the storage device 20 through the data transfer interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operations. For example, the host system 10 can store data to the storage device 20 or read data from the storage device 20 via the data transfer interface circuit 130.

[0026] In the present embodiment, the number of data transfer interface circuits 130 can be one or more. Through the data transfer interface circuits 130, the host board can be electrically connected to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, a USB flash drive, a memory card, a solid state drive (SSD), or a wireless memory storage device. The wireless memory storage device can be, for example, a Near Field Communication (NFC) memory storage device, a WiFi memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. In addition, the host board can also be electrically connected to various I / O devices such as a Global Positioning System (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, and the like via a system bus.

[0027] In the present embodiment, the data transfer interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In addition, data transfer between the data transfer interface circuit 130 and the connection interface circuit 230 is performed using the Non-Volatile Memory express (NVMe) communication protocol.

[0028] In another embodiment, the connection interface circuit 230 can be packaged in a chip with the memory controller 210, or the connection interface circuit 230 can be disposed outside a chip containing the memory controller 210.

[0029] In the present embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. In the present embodiment, the host memory 120 can be a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), or the like. However, it must be understood that the present disclosure is not limited thereto, and the host memory 120 can also be other suitable memories.

[0030] The memory controller 210 is configured to execute a plurality of logic gates or control instructions implemented in a hardware or firmware manner, and to perform corresponding data writing, data reading, data erasing, and the like in the memory module 220 according to instructions of the host system 10. In particular, the memory controller 210 is configured to perform a memory management method provided by the present disclosure to identify critical voltage shift attributes of physical pages and to implement intelligent classified storage of data.

[0031] In more detail, the processor 211 in the memory controller 210 is a hardware with computing capability, which is configured to control overall operations of the memory controller 210. In particular, the processor 211 is programmed with a plurality of control instructions / program codes, which are executed to perform data writing, reading, erasing, and the like when the memory device 20 is in operation. In addition, the processor 211 is configured to perform a memory management method provided by the present disclosure. In particular, the processor 211 is configured to perform a voltage shift identification operation on a physical page in response to a failed read operation on the physical page in the memory module 220 to obtain a shift attribute of the physical page, where the shift attribute is used to indicate a main shift trend of a critical voltage distribution of the physical page. The processor 211 records the shift attribute of the physical page, and obtains target data and a data attribute of the target data based on a write instruction. The processor 211 selects one or more target physical pages from a plurality of physical pages in the memory module 220 based on the data attribute of the target data, where the one or more target physical pages have shift attributes corresponding to the data attribute, and writes the target data to the one or more target physical pages.

[0032] It is worth mentioning that, in the present embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a micro-processor, or other programmable processing units (Microprocessor), a digital signal processor (DSP), a programmable controller, an application specific integrated circuit (ASIC), a programmable logic device (PLD), or other similar circuit components, and the present disclosure is not limited thereto.

[0033] In the present embodiment, as described above, the memory controller 210 further includes the data management circuit 212 and the memory interface control circuit 213. It should be noted that operations performed by the components of the memory controller 210 can also be considered as operations performed by the memory controller 210.

[0034] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 is configured to accept instructions from the processor 211 to perform data transfer. For example, data is read from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230, and the read data is written into the memory module 220 via the memory interface control circuit 213. For another example, in response to a read instruction from the host system 10, data is read from one or more physical units of the memory module 220 via the memory interface control circuit 213, and the read data is written into the host system 10 via the connection interface circuit 230.

[0035] In another embodiment, the data management circuit 212 can be integrated into the processor 211. The memory interface control circuit 213 is configured to accept instructions from the processor 211 to perform physical operations such as writing (also referred to as programming), reading, or erasing on the memory module 220 in cooperation with the data management circuit 212.

[0036] In addition, data to be written into the memory module 220 is converted into a format acceptable to the memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 wants to access the memory module 220, the processor 211 sends corresponding instruction sequences to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform corresponding operations. For example, the instruction sequences can include write instruction sequences to instruct writing of data, read instruction sequences to instruct reading of data, erase instruction sequences to instruct erasing of data, and corresponding instruction sequences to instruct various memory operations. The instruction sequences can include one or more signals, or data on a bus. The signals or data can include instruction codes or program codes. For example, in a read instruction sequence, information such as a read identification code, a memory address, a physical address, and the like can be included.

[0037] In addition, the memory controller 210 establishes a logical to physical address mapping table and a physical to logical address mapping table to record the mapping relationship between the logical address of a logical unit (e.g., a logical block, a logical page) configured to the memory module 220 and the physical address of a physical unit (e.g., a physical erase unit / physical block, a physical page). In other words, the memory controller 210 can find the physical unit mapped by a logical unit (e.g., find the physical page mapped by a logical page; find the physical address mapped by a logical address) through the logical to physical address mapping table (also referred to as a logical to physical mapping table), and the memory controller 210 can find the logical unit mapped by a physical unit (e.g., find the logical page mapped by a physical page; find the logical address mapped by a physical address) through the physical to logical address mapping table (also referred to as a physical to logical mapping table).

[0038] The buffer memory 214 is electrically connected to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the memory module 220, and various system data (e.g., various mapping tables, statistical data, offset attribute records, etc.) for managing the storage device 20.

[0039] In embodiments of the present disclosure, the core use of the buffer memory 214 is as a data storage area for offset attribute management to achieve dynamic tracking and management of the physical page offset state. Specifically, the buffer memory 214 stores the physical page offset attribute records obtained by the processor 211 through the voltage offset identification operation. When the host system 10 sends a write instruction, the processor 211 queries the corresponding offset physical page list from the buffer memory 214 according to the data attribute of the target data to select a target physical page with offset attributes matching the data attribute for data writing.

[0040] In some embodiments, to achieve more refined management, the buffer memory 214 can store an offset physical page list that records the physical page information with a first offset attribute (trend of critical voltage tends to decrease) and a second offset attribute (trend of critical voltage tends to increase). Meanwhile, the buffer memory 214 can also store an offset physical block list that records the offset attribute of an offset physical block when the number of offset physical pages with the same offset attribute in the offset physical block reaches an offset quantity threshold. In addition, the buffer memory 214 can also temporarily store intermediate data in the voltage offset identification process, such as soft information and logical likelihood ratio (LLR) values read from the physical page.

[0041] To support the operation of the above offset attribute management strategy, the buffer storage 214 is further configured to store relevant runtime data and management information. This includes: (1) a data structure for recording the comparison result of the current threshold voltage and the initial threshold voltage of each entity page; (2) a counter data for counting the storage cells of different offset directions in the entity page; (3) a counter data for counting the entity pages of different offset attributes in the entity block; and (4) a logical-to-physical address (L2P) mapping information for updating the available state of the offset entity page. Through the above dynamic management strategy based on the offset attribute, the present disclosure can realize the intelligent matching of the data characteristics and the storage region characteristics, prolong the service life of the memory, and improve the data storage reliability.

[0042] The memory module 220 is electrically connected to the memory controller 210 (specifically, to the memory interface control circuit 213) and is configured to store the user data sent by the host system 10. In an embodiment, the memory unit structure of the memory module 220 can be understood as a multi-level physical organization architecture. Specifically, the memory module 220 includes a plurality of chips, each chip has a plurality of planes, and each plane internally includes a plurality of entity blocks, each entity block is composed of a plurality of entity pages. Each entity page includes a plurality of storage cells, which can be single-level storage cells (SLC) or multi-level storage cells (MLC, TLC, QLC, etc.). Each storage cell has an initial threshold voltage value, and the threshold voltage of the storage cell can be left-shifted or right-shifted as the use time is prolonged. It should be noted that the present disclosure is not limited to the specific capacity size of the memory module 220 or the specific number of entity pages.

[0043] The processor 211 performs the voltage offset identification operation (e.g., compares the initial threshold voltage value and the current threshold voltage value) on the entity page when the read operation on the entity page in the memory module 220 fails, to determine the offset attribute of the entity page and record it in the buffer storage 214 or / and the memory module 220, by executing the memory management method of the present disclosure. When the processor 211 needs to write target data, the corresponding target entity page is selected from the entity pages with recorded offset attributes according to the data attribute of the target data, to realize the matching storage of the data characteristics and the storage region characteristics.

[0044] Figure 2 is a flowchart of the memory management method according to an embodiment of the present disclosure.

[0045] Referring to Figure 2 In step S210, the memory controller 210 performs the voltage offset identification operation on the entity page in response to the read operation failure on a certain entity page in the plurality of entity pages in the memory module 220, to obtain the offset attribute of the entity page. The offset attribute is used to indicate the main offset trend of the threshold voltage distribution of the entity page.

[0046] In particular, when the processor 211 performs a regular read operation on a physical page via the memory interface control circuit 213, if a read failure occurs, such as an error correction code (ECC) decoding operation failure, the system will trigger a voltage shift identification operation. The purpose of this operation is to diagnose the physical health of the physical page in depth to obtain its shift attribute. The shift attribute can indicate the main shift trend of the threshold voltage (Vth) of a large number of storage units in the physical page in a statistical sense, for example, whether the overall trend is to decrease (also known as left shift) or to increase (also known as right shift).

[0047] It is worth mentioning that in another embodiment, the condition for triggering the voltage shift identification operation is not limited to read operation failure. The processor 211 can also be configured to actively or opportunistically perform the voltage shift identification operation under other preset conditions to obtain the shift attribute of the physical page preventively.

[0048] In particular, in an active prediction implementation, the processor 211 can continuously monitor the health parameter of each physical block 210 in the memory module 220. For example, when the number of program / erase (P / E) cycles of a certain physical block 210 accumulates to a preset aging threshold, the processor 211 can target all or part of the physical pages 220 in the physical block 210 and actively perform the voltage shift identification operation thereon. This aging-based triggering method can identify high-risk physical pages in advance before serious read errors occur.

[0049] In another opportunistic monitoring implementation, the processor 211 can trigger the voltage shift identification operation while performing internal background management tasks. For example, the storage device 20 usually performs background tasks such as data scrubbing or patrol read during idle periods to check and refresh stored data. During the execution of these background read tasks, the processor 211 can perform the voltage shift identification operation on the physical pages 220 being read. Since these background tasks have a relatively low priority, the relatively time-consuming voltage identification operation during their execution has less impact on user experience.

[0050] In addition, in one embodiment of quasi-real-time feedback, the triggering condition can be a "quasi-failure" signal. Specifically, even if a read operation eventually succeeds with error correction code (ECC) decoding, the processor 211 can still obtain the number of error bits corrected in the decoding process. If the number of error bits exceeds a pre-set error bit threshold, this can also be considered as a signal of significant degradation of the physical page health. Thus, the processor 211 can also perform a voltage shift identification operation on the physical page 220 in response to the number of error bits corrected exceeding the error bit threshold. This way, the problematic physical page can be intervened and identified earlier before a complete read failure occurs.

[0051] In more detail, in one embodiment, when a read operation on a physical page encounters a failure, in the voltage shift identification operation performed, the processor 211 measures and records the actual threshold voltage (also referred to as the current threshold voltage) of each memory cell of the physical page at the current time by performing a series of physical layer operations. Then, the processor 211 compares the current threshold voltage of all memory cells of the physical page with the initial threshold voltage value that the memory cells should have at the time of factory shipment or under ideal conditions. Through the comparison, the processor 211 can recognize the voltage shift of each memory cell in the physical page. The voltage shift is, for example, "left shift" which is lower than the initial threshold voltage value, and "right shift" which is higher than the initial threshold voltage value.

[0052] Then, the processor 211 examines the overall shift direction distribution trend of all memory cells in the physical page from a more macro perspective. For example, through statistical analysis, it is determined whether the total number of memory cells in a certain shift direction dominates (e.g., the total number is greater than a pre-set threshold). In this way, the processor 211 can determine the shift characteristics of the physical page (e.g., the shift characteristics correspond to the dominant shift direction), and assign a corresponding shift attribute to the physical page, thereby providing a basis for decision-making for subsequent intelligent data management.

[0053] The following uses Figures 3-5 to illustrate the details of the voltage shift identification operation.

[0054] Figure 3 is a flowchart of the voltage shift identification operation according to an embodiment of the present disclosure.

[0055] When the processor 211 performs a read operation on a physical page, a read failure is detected. In one specific example, the read failure can be manifested as a failure of an error correction code (ECC) decoding operation performed on data read from the physical page. The failure event is a prerequisite condition for triggering a subsequent voltage shift identification operation.

[0056] Referring to Figure 3 At step S310, the processor 211 needs to obtain the current threshold voltage (Vth_current) of each memory cell in the physical page (the physical page whose decoding operation fails). In one embodiment, this step can be implemented in the following way: first, the processor 211 recovers the correct data stored in the physical page based on the physical layer information (e.g. soft information obtained by soft decision read operation) obtained when the read operation fails; then, the processor 211 takes the recovered correct data as a logical reference, and combines it with the physical layer information to accurately calculate the current threshold voltage of each memory cell.

[0057] The specific implementation mechanism will be described below in connection with Figure 5 the multi-level memory cell threshold voltage distribution shown in FIG. 2.

[0058] Figure 5 FIG. 1 is a schematic diagram of a multi-level memory cell (MLC) threshold voltage distribution according to an embodiment of the present disclosure.

[0059] In one embodiment, the specific implementation of how the processor 211 recovers the correct data by combining the physical layer information after the read failure, and finally determines the current threshold voltage of each memory cell, will be further described.

[0060] When a regular hard decision read operation fails due to too many errors, the processor 211 instructs the memory interface control circuit 213 to perform a soft decision read operation on the faulty physical page. The soft decision read scans the memory cells by applying a series of fine voltage levels, thereby obtaining soft information that quantitatively represents the reliability level of the data bits. These soft information, for example, are Log-likelihood Ratio (LLR) values. Then, the processor 211 inputs these soft information into its internal error correction code (ECC) decoder to perform a soft decoding operation, thereby recovering the original correct data stored in the physical page.

[0061] After successfully obtaining the correct data, the processor 211 takes this known correct data as a reference to re-interpret the soft information obtained by the soft decision read, and by combining the logical correct value with the voltage response information at the physical layer, the processor 211 can accurately infer the current threshold voltage of each memory cell in the physical page, thereby providing accurate physical layer data for subsequent offset direction judgment.

[0062] For example, after a regular hard decision read operation fails, for example, error correction code decoding fails, the processor 211 initiates a soft decision read operation. Referring to Figure 5For example, assume that the memory controller 210 normally distinguishes the four states by setting three read reference voltages Vreadi at 1 V, Vread2 at 2 V, and Vread3 at 3 V.

[0063] In this example, assume that the storage cell corresponding to state S2 with data "00" at the time of writing has an initial threshold voltage of 2.5 V. As the number of program-erase cycles increases, the storage cell experiences charge leakage, causing its current actual threshold voltage to decrease to 1.9 V. In this case, a conventional hard-decision read would incorrectly interpret it as state Si corresponding to data "01", resulting in a failed error correction code (ECC) decoding. The processor 211 would then attempt to re-scan the storage cell using a soft-decision read operation.

[0064] In one embodiment, in a soft-decision read operation, the processor 211 does not blindly scan all voltages, but instead uses information provided by the ECC decoder at the time of initial read failure to perform a targeted scan.

[0065] For example, when a hard-decision read terminates due to ECC decoding failure, the ECC decoder itself can output reliability information for each data bit within the page. By "reliability information", we do not mean the log-likelihood ratios (LLRs) used in the soft-decision decoding process, but rather diagnostic output provided by the ECC decoder from its internal decoding process after a hard-decision read terminates due to ECC decoding failure.

[0066] Specifically, an ECC decoder (not shown), such as one using a low-density parity-check (LDPC) algorithm, is integrated within the memory controller 210 and works by iteratively attempting to satisfy a set of predetermined check equations (also known as parity constraints). When a hard-decision decoding ultimately fails, it usually means that the decoder was unable to satisfy some of the check equations after reaching a maximum number of iterations. In this case, the decoder is able to identify and output the locations of specific data bits associated with these "unsatisfied check equations". These identified bits, which are considered to be the "most unreliable" bits in this read, form the "reliability information" used by the processor 211 to locate the error region.

[0067] For example, the processor 211 can identify those "least reliable bits" whose log-likelihood ratios (LLRs) are closest to zero. In one embodiment, the processor 211 knows which particular read reference voltage is used to decide different data bits (e.g., the most significant bits MSB or the least significant bits LSB) in the data encoding scheme of the MLC. For example, in the scenario of Figure 2, the reference voltage that distinguishes between states S1 and S2 is Vread2, which mainly affects the decision of the MSB. Therefore, if the ECC decoder reports that multiple MSB bits within the page are "least reliable bits," the processor 211 can determine that the read error mainly occurs near the decision boundary of Vread2. Figure 5

[0068] Based on this determination, the processor 211 no longer needs to perform scanning around all three reference voltages (Vreadl, Vread2, Vread3), but only around the decision boundary where the error is most likely to occur (in this example, the region where Vread2 equals 2V). A pre-determined fine multi-voltage sequence is applied for repeated scanning read around this region. For example, the sequence can include 1.8V, 1.9V, 2.0V, 2.1V, and 2.2V (centered at Vread2, with pre-determined offset voltage values to set this voltage sequence).

[0069] Next, the processor 211 starts to perform soft-decoding operation. Specifically, the processor 211 controls the memory interface control circuit 213 to apply these voltages one by one. For example, for the memory cell with a threshold voltage of 1.9V, the read result is "1" when 1.8V is applied because 1.9V is greater than 1.8V, the read result is "0" when 1.9V is applied because the voltages are approximately equal, and the read result is "0" when 2.0V, 2.1V, and 2.2V are applied because 1.9V is less than these voltage values. In this way, the processor 211 obtains the read result vector [1, 0, 0, 0, 0] for this memory cell, which constitutes the physical layer information in this embodiment.

[0070] Subsequently, the processor 211 calculates a log-likelihood ratio (LLR) vector for each data bit in the physical page based on the physical layer information. In one embodiment, the calculation can be done by querying a pre-calibrated probability lookup table. The LLR value quantitatively represents the reliability of a bit being "0" or "1." Generally, the closer the actual threshold voltage of a memory cell is to a decision boundary, the smaller the absolute value of its corresponding LLR, indicating that the bit is less reliable. The LLR vector is then inputted into the ECC decoder that supports soft-decoding and low-density parity-check code (LDPC) algorithm as soft information.

[0071] ​The ECC decoder recovers the correct data stored in the physical page using the LLR vector and the syndrome information of the entire physical page, and performs a soft-decoding operation. In the above example, the soft-decoding operation corrects the erroneous data "01" back to the original correct data "00". Specifically, the decoder prioritizes the high-reliability bits with larger absolute values of LLRs, and uses these reliable bits to correct the low-reliability bits with smaller absolute values of LLRs.

[0072] After obtaining the correct data, the processor 211 can use the recovered correct data as a certain logical reference to interpret the physical layer information obtained in the multi-voltage scan, and to infer the current threshold voltage of the memory cell.

[0073] In an embodiment, the processor 211 uses the correct data as a reference, and combines the soft information to determine the current threshold voltage of each memory cell in the physical page.

[0074] Specifically, the implementation of this process is mainly based on the analysis of the cause of the hard-decision read failure. In the above embodiment, the failure of a regular hard-decision read operation is due to the fact that the actual threshold voltage (1.9V) of the memory cell is lower than the reference voltage Vread2, and thus a high-level read result is physically generated when the processor 211 applies the reference voltage Vread2 (2V) to the memory cell. According to the preset encoding rule (e.g., Table 1), the high-level result is initially interpreted by the ECC decoder as state S1, corresponding to data "01". However, in a healthy case, the threshold voltage of the memory cell should be higher than Vread2, and thus a low-level read result is generated, which should be interpreted as state S1, corresponding to data "01". It is this mismatch between the physical reality and the logical expectation that leads to the final ECC check failure. Figure 5

[0075] In short, the direct cause of the hard-decision read failure is that the physical characteristics (current threshold voltage) of the memory cell have deviated from the range of physical characteristics (initial threshold voltage) that the logical state (S2) represented by the memory cell should have.

[0076] In an embodiment, after obtaining the physical layer information (i.e., the read result vector [1, 0, 0, 0, 0]) and the logical layer reference (i.e., the correct data "00" recovered by the soft-decoding operation), the processor 211 performs the following analysis process:

[0077] (1) Determine the logical state: According to the result of the soft-decoding operation, the processor 211 confirms that the correct data stored in the memory cell is "00", and the corresponding logical state is S2.

[0078] ​(2) Analysis of physical behavior: The processor 211 analyzes the read result vector [1, 0, 0, 0, 0], which objectively indicates that the flipping point of the physical conduction state of the memory cell occurs in the voltage interval of 1.8V to 1.9V, i.e., the actual physical threshold voltage thereof is about 1.9V.

[0079] (3) Comprehensive inference: The processor 211 combines the above two points and concludes that a memory cell that should be in state S2 in logic has an actual physical threshold voltage of 1.9V, which has caused the previous misjudgment state S1. Therefore, the processor 211 finally determines that the current threshold voltage of the memory cell is 1.9V.

[0080] By analogy, through the above process, the processor 211 can establish a corresponding relationship between the misjudgment fact of the logical state and the actual physical threshold voltage of each memory cell in the physical page, so as to obtain the current threshold voltage. The processor 211 extends the above operation for a single memory cell to all memory cells in the entire physical page to obtain the threshold voltage distribution of the physical page.

[0081] In an embodiment, after the processor 211 obtains the respective current threshold voltage of each memory cell in the physical page, it enters the final determination stage of the overall shift attribute of the physical page.

[0082] Specifically, the processor 211 counts the memory cells with different shift directions respectively. For example, it counts the total number (first number) of the first memory cells whose threshold voltage tends to decrease (first shift direction) and the total number (second number) of the second memory cells whose threshold voltage tends to increase (second shift direction) in the physical page.

[0083] Subsequently, the processor 211 compares the counted numbers with a pre-set threshold value of the number of shifted cells. When the first number exceeds the threshold value, it indicates that the memory cells with "left shift" in the page have dominated, and the processor 211 determines the overall shift attribute of the physical page as the first shift direction. Correspondingly, if the second number exceeds the threshold value, it indicates that "right shift" is the main aging trend of the page, and the processor 211 determines the shift attribute as the second shift direction. In this way, the system can assign a physically meaningful shift attribute to each diagnosed physical page.

[0084] In an embodiment, the threshold value of the number of shifted cells is pre-set as half of the total number of memory cells in the physical page, for example.

[0085] For example, after the processor 211 has completed obtaining the current critical voltage of all memory cells in the physical page (e.g., a physical page containing 1000 memory cells), it can proceed to the next step S320, where the processor 211 compares the current critical voltage with the initial critical voltage to determine the offset direction (left offset / right offset) of each memory cell in the physical page.

[0086] Specifically, processor 211 compares the current critical voltage of each memory cell in the physical page with the initial critical voltage to statistically determine the overall offset distribution of the physical page. For example, the statistical results might be: 750 memory cells have critical voltages lower than the initial value, indicating a left offset; 100 memory cells have critical voltages higher than the initial value, indicating a right offset; and 150 memory cells remain relatively stable. Based on this statistical analysis, processor 211 performs an offset attribute determination operation. For example, when processor 211 sets a threshold of 500 memory cells, since the number of left-off memory cells (750) exceeds this threshold, processor 211 determines the dominant offset direction of the physical page as left offset and assigns it a corresponding first offset attribute (e.g., left offset attribute). Through this statistical determination mechanism, processor 211 can identify the overall aging characteristics of the physical page, providing a basis for subsequent data classification and storage.

[0087] In summary, the core of the process for obtaining the current critical voltage of each memory cell lies in a comprehensive method that combines logic-level correction with physical-level observation. This method first uses physical-level information obtained when a read operation fails (e.g., the read result vector [1,0,0,0,0] obtained through multi-voltage scanning) to recover the correct data stored in the physical page through a global verification operation (e.g., correcting "01" back to "00"). Then, the recovered correct data ("00", corresponding to logic state S2) is used as a logic reference, combined with physical-level information (indicating the voltage inversion point is approximately 1.9V), to definitively infer the current critical voltage of each memory cell.

[0088] In one specific implementation, the above general logic is achieved through, as follows: Figure 5 The implementation is achieved using the soft-decision and soft-decoding techniques described in the embodiments. Specifically, processor 211 performs a soft-decision read operation on the physical page to obtain soft information (e.g., an LLR vector containing the read result vector and calculated from it). Subsequently, processor 211 performs a soft-decoding operation on the stored data based on the soft information to obtain the correct data. Finally, processor 211 uses the correct data as a reference and combines it with the soft information to determine the current critical voltage of each memory cell.

[0089] By restoring logical correctness first and then deducing the physical state value, the method of the present disclosure can determine the direction of the shift of the threshold voltage of each memory cell after a read error occurs, providing a reliable data basis for subsequent statistical-based physical page attribute determination.

[0090] It is worth mentioning that, for the sake of completeness, the following references Figure 5 and another embodiment are described to illustrate the right shift determination.

[0091] In another embodiment, also with reference to Figure 5 , we describe a situation where the read fails due to the threshold voltage tending to rise (right shift). In this example, assume that an MLC memory cell has the same data "00" as written, corresponding to state S2, and its measured initial threshold voltage (Vth_initial) is 2.5V. After a large number of program / erase (P / E) cycles, electron traps (Electron Traps) may be generated in the tunnel oxide layer of the memory cell, causing excessive electrons to be trapped during programming. This causes the current actual threshold voltage (Vth_current) of the memory cell to abnormally rise to 3.1V, which is higher than Vread3 (3V).

[0092] In this case, when the memory controller 210 performs a regular hard decision read operation, it will apply the read reference voltages Vread1 (1V), Vread2 (2V) and Vread3 (3V) in turn, and obtain the following results: when Vread1 is applied, since the actual threshold voltage 3.1V is greater than 1V, the read result is low; when Vread2 is applied, since the actual threshold voltage 3.1V is greater than 2V, the read result is low; when Vread3 is applied, since the actual threshold voltage 3.1V is greater than 3V, the read result is also low.

[0093] Then, according to the read result sequence (low, low, low), the memory controller 210 will incorrectly determine the state of the memory cell as S3, corresponding to the data "10". This determination result is inconsistent with the original written data "00", thus triggering the ECC decoding failure.

[0094] After triggering the voltage shift identification operation, the processor 211 can determine, according to the reliability information provided by the ECC decoder, that the read error mainly occurs near the decision boundary of Vread3. Therefore, the processor 211 controls the memory interface control circuit 213 to apply a multi-voltage sequence for repeated scanning read only near the decision boundary (the region where Vread3 is equal to 3V). For example, the sequence can include 2.9V, 3.0V, 3.1V, 3.2V and 3.3V.

[0095] Taking the storage unit with the current actual threshold voltage of 3.1V as an example, the processor 211 can obtain a read result vector as follows: when 2.9V and 3.0V are applied, the read result is “1” because 3.1V is greater than both of the two voltage values; when 3.1V is applied, the read result flips to “0” because the voltage is approximately equal; when 3.2V and 3.3V are applied, the read result remains “0” because 3.1V is less than both of the two voltage values. That is, the processor 211 obtains the read result vector of the storage unit, for example, [1, 1, 0, 0, 0], in this way.

[0096] In addition, it is assumed that after the LLR vector is calculated based on the vector and the soft decoding operation is performed, the processor 211 restores that the correct data of the storage unit should be “00” (corresponding to state S2).

[0097] Accordingly, the processor 211 takes the correct data “00” as a logical reference, and in combination with the physical layer information indicating that the bit flipping point occurs near 3.1V, the current threshold voltage (Vth_current) of the storage unit is accurately inferred to be 3.1V. After obtaining the voltage, the processor 211 can compare it with the initial threshold voltage (2.5V) to determine that the storage unit has “right shift” (the second shift attribute).

[0098] It should be noted that the above two examples are described for the MLC storage unit, but the present disclosure is not limited thereto. For example, the present disclosure is also applicable to the SLC storage unit.

[0099] Figure 4 FIG. 3 is a schematic diagram of a threshold voltage distribution of a single-level storage unit (SLC) according to an embodiment of the present disclosure.

[0100] Referring to Figure 4 For the SLC type storage unit, each storage unit 230 has two threshold voltage states S0 and S1 corresponding to data “1” (usually an erased state) and “0” (usually a programmed state) respectively. The memory controller 210 distinguishes the two states by setting a read reference voltage Vread (for example, 1.5V) between the states S0 and S1.

[0101] In an embodiment, it is assumed that an SLC storage unit has an initial threshold voltage (Vth_initial) of 2.0V after writing data “0” (corresponding to state S1). After a period of use or long-term storage, the floating gate of the storage unit has charge leakage, causing its current actual threshold voltage (Vth_current) to abnormally drop to 1.2V, which is a phenomenon of “left shift”.

[0102] In this case, when the processor 211 performs a regular read operation, the hard decision read will incorrectly interpret the state of the memory cell as S0 and output an erroneous data "1" because its actual threshold voltage 1.2V has already fallen below the read reference voltage Vread (e.g., 1.5V). When this error occurs and causes the ECC decoding to fail, the voltage shift identification operation of the present disclosure is triggered.

[0103] In the identification process, the processor 211 performs a fine multi-voltage sequence scan on the memory cell and recovers its correct data as "0" through soft decoding or the like.

[0104] In more detail, in an embodiment, the specific process of obtaining the current threshold voltage is as follows:

[0105] First, based on the fact that a cell that should be "0" is misread as "1" when the hard decision read fails, the processor 211 can infer that the actual threshold voltage of the memory cell has already fallen below the read reference voltage Vread (e.g., 1.5V). Based on this inference, the processor 211 can focus the subsequent fine scan on the voltage interval "below" the read reference voltage Vread to efficiently locate the actual threshold voltage (because the threshold voltage that leads to the interpretation of state S0 "1" must be below Vread 1.5V).

[0106] Subsequently, the processor 211 controls the memory interface control circuit 213 to apply a preset multi-voltage sequence in the focused voltage interval. For example, the sequence can include 1.1V, 1.2V, 1.3V, and 1.4V.

[0107] The memory interface control circuit 213 applies these voltages in sequence and reads the results, and the processor 211 generates a "read result vector" according to these results. Taking the memory cell with the current actual threshold voltage of 1.2V as an example: when 1.1V is applied, since the actual threshold voltage 1.2V is greater than 1.1V, the read result is "1"; when 1.2V is applied, since the voltages are approximately equal, the critical point of the on state is reached, and the read result flips to "0"; when 1.3V and 1.4V are applied, since the actual threshold voltage 1.2V is less than both of these voltage values, the read result remains "0".

[0108] In this way, the processor 211 obtains the read result vector of the memory cell, for example, [1, 0, 0, 0]. This vector constitutes the physical layer information in this embodiment. By analyzing the read result vector, the processor 211 can determine that the position of the bit flip (i.e., the position where "1" changes to "0") occurs in the scanning interval of 1.1V to 1.2V. This physical layer evidence objectively indicates that the current actual threshold voltage of the memory cell is close to 1.2V.

[0109] Then, after taking the correct data "0" recovered by soft decoding as a logical reference, and combining the above-mentioned physical layer information, the processor 211 can determine that the physical actual threshold voltage of a storage unit which logically should store data "0" is 1.2V.

[0110] Next, the processor 211 compares the current threshold voltage (1.2V) with the initial threshold voltage (2.0V), and since 1.2V is less than 2.0V, the processor 211 determines that the storage unit has "left shift".

[0111] By analogy, after completing the operation on all storage units of the entire physical page, if the processor 211 finds that the number of storage units with "left shift" characteristics exceeds the preset number threshold, the processor 211 determines that the shift attribute of the physical page is the first shift attribute (left shift attribute) indicating that the threshold voltage tends to decrease. The physical page will then be recorded in the shift physical page list and will be preferentially used to store frequently accessed hot data in subsequent data write operations.

[0112] Figure 6 is a schematic diagram of threshold voltage shift according to an embodiment of the present disclosure.

[0113] Referring to Figure 6 , Figure 6 shows two typical cases of shift of threshold voltage of storage units from the initial distribution state.

[0114] Figure 6 The initial threshold voltage distribution in the initial threshold voltage distribution state represents the standard threshold voltage distribution state of the storage units in the memory module 220 when the manufacturing is completed or initially used. The initial distribution presents a concentrated bell-shaped curve feature, indicating that the threshold voltages of most storage units are distributed around the design target value, with relatively stable voltage characteristics. This initial state provides an important reference for subsequent shift attribute identification. In an embodiment, the threshold voltage used for comparison with the current threshold voltage can be a recorded standard threshold voltage or a preset initial threshold voltage.

[0115] For example, in an embodiment, the initial threshold voltage value of each storage unit can be set according to the chip specifications of the memory module 220 at the time of factory shipment, so that the corresponding storage unit can be programmed to the required bit value. The initial threshold voltage value can also represent the threshold voltage value that each storage unit should have under ideal conditions.

[0116] Figure 6The left dotted curve in FIG. 2B represents the "first shift attribute". This attribute indicates that the threshold voltage distribution of the physical page 220 tends to decrease as a whole, also known as "left shift". This situation is usually related to charge leakage from the floating gate of the memory cell 230, and the main negative impact is the degradation of the data retention capability. According to the method of the present disclosure, the physical page 220 with the first shift attribute will be preferentially used to store frequently accessed hot data.

[0117] Figure 6 The right dotted curve in FIG. 2B represents the "second shift attribute". This attribute indicates that the threshold voltage distribution of the physical page 220 tends to increase as a whole, also known as "right shift". This situation is usually related to the generation of electron traps in the tunnel oxide layer, and the main negative impact is the reduction of the program window margin and the increase of the sensitivity to program disturb. According to the method of the present disclosure, the physical page 220 with the second shift attribute will be preferentially used to store cold data that needs to be stored for a long time.

[0118] Through the voltage shift identification operation of the present disclosure, the processor 211 can accurately determine the shift trend of the threshold voltage distribution of each physical page 220 that has failed to read, and assign a corresponding shift attribute to it. This classification mechanism based on the real physical state is the management basis for the subsequent intelligent data placement.

[0119] Please refer back to Figure 3 After obtaining the current threshold voltage of each memory cell, the flow proceeds to step S320. The processor 211 compares the current threshold voltage (Vth_current) of each memory cell with the initial threshold voltage (Vth_initial) of each memory cell. Through the comparison, the processor 211 can determine the shift direction of each memory cell, for example, whether the threshold voltage tends to decrease in the "left shift" direction (e.g., the first shift attribute), or the threshold voltage tends to increase in the "right shift" direction (e.g., the second shift attribute).

[0120] After completing the determination of the shift direction of all memory cells in the page, the flow enters step S330. Here, the processor 211 counts the respective number of memory cells with different shift directions, and determines whether the corresponding total number is greater than a preset threshold of the number of shifted cells.

[0121] If the result of the judgment is "Yes" (i.e., the number of shift cells in a certain direction exceeds the threshold of shift cell number), the flow proceeds to step S340. In this step, the processor 211 determines the entity page as a "shifted entity page" and assigns and records a corresponding shift attribute to it. For example, if the number of storage cells in the "left shift" direction exceeds the first threshold of shift cell number, the shift attribute of the entity page is determined as the first shift attribute indicating that the threshold voltage tends to decrease; if the number of storage cells in the "right shift" direction exceeds the second threshold of shift cell number, the shift attribute of the entity page is determined as the second shift attribute indicating that the threshold voltage tends to increase. After the shift attribute is determined, the relevant information is recorded for subsequent data write matching.

[0122] On the contrary, if the result of the judgment in step S330 is "No" (i.e., the number of cells in any shift direction does not reach the threshold), the flow proceeds to step S350. In this step, the processor 211 determines the entity page as a "standard entity page". A standard entity page will not be recorded and can be used in subsequent operations to store general data without specific attribute requirements.

[0123] In summary, through the voltage shift identification operation flow shown in Figure 3 The disclosure realizes the identification of the shift attribute of the entity page based on actual physical measurement, laying a technical foundation for subsequent intelligent data allocation. The identification mechanism can distinguish the shift attribute of the entity page through the identification and statistical analysis of the threshold voltage shift of each storage cell, thereby ensuring the appropriate matching of data with different data attributes and storage entities with different shift attributes.

[0124] Returning to Figure 2 In step S220, the processor 211 associates the obtained shift attribute with the entity address (physical address) and other information of the entity page and records it. This recording process not only includes the entity address information of the entity page, but also contains its corresponding shift attribute type, such as the first shift attribute (e.g., left shift) or the second shift attribute (e.g., right shift).

[0125] In an embodiment, the recording operation can be specifically manifested as creating or updating an entry in a shifted entity page list stored in the buffer memory 214. The entry is used to persistently save the health status information of the entity page, thereby providing a basis for subsequent data write decision.

[0126] For example, in one embodiment, when the storage device 20 is powered on, the processor 211 needs to rebuild the running environment, which includes loading the offset entity page list stored in the memory module 220 into the buffer memory 214. To do so, the processor 211 reads data from a reserved specific physical area of the memory module 220 during the firmware initialization process. This area is specifically used to store various system metadata, including the offset entity page list. The processor 211 loads the read list data (e.g., offset entity page list or offset entity block list) into a pre-allocated memory space in the buffer memory 214. Through this loading process, all the entity page health status information accumulated before the power-off of the storage device 20 is recovered, providing the basis for the next round of write operations.

[0127] In one embodiment, during the normal operation of the storage device 20, when the processor 211 successfully determines a new offset entity page through the voltage offset identification operation, for example, it is determined that the entity page with physical address "entity block B1_entity page P1" has the first offset attribute (left offset attribute), it directly updates the offset entity page list in the buffer memory 214 in real time. This update operation specifically represents the creation of a new entry. Referring to Table T91 in Figure 9 The entry can include multiple fields, such as: physical address field: fill in "B1_P1"; offset direction field: fill in "left"; available state field: initially fill in "1", indicating that the page is currently free. The offset entity page list in the buffer memory 214 provides a direct basis for subsequent data write decisions.

[0128] In one embodiment, when the storage device 20 receives a shutdown instruction or detects an unexpected power-off event, the processor 211 triggers the shutdown process. In this process, the latest version of the list data in the buffer memory 214 is written back to the reserved physical area of the memory module 220. This "write-back" or "flush" operation ensures that all newly diagnosed offset entity page information and state updates during this running period are safely and persistently saved to the non-volatile storage medium. In this way, these offset entity page lists can be loaded and utilized again at the next system startup, thereby realizing the continuity of the list information across the shutdown period.

[0129] In some embodiments, the processor 211 also periodically updates the available state of each entity page in the offset entity page list through the logical-to-physical address mapping table. In this way, the processor 211 can directly select available offset entity pages through the offset entity page list to write corresponding data, thereby improving write efficiency.

[0130] Specifically, the core of this maintenance task is to utilize the logical-to-physical address mapping table (L2P mapping table) and supplement it with the physical-to-logical address mapping table (P2L table) or metadata recording the state of physical blocks.

[0131] In one embodiment, the processor 211 can set a timer, for example, every 5 minutes, to trigger the state update procedure once. When the timer expires, the processor 211 will iterate through the offset physical page list. For each entry in the list, for example, the physical page with physical address "B1_P8", the processor 211 will perform the following judgment procedure:

[0132] The processor 211 will first check whether there is any logical address in the L2P mapping table that maps to "B1_P8". If there is, it means that "B1_P8" currently stores valid data. The processor 211 will update or maintain its "available state" field to "0" (not available).

[0133] If there is no entry in the L2P mapping table that maps to "B1_P8", it can only mean that the page does not contain valid data, but it may contain invalid data or has been erased. For this purpose, the processor 211 will further judge:

[0134] Case 1 (contains invalid data): The processor 211 queries the P2L table, and if it finds a record that maps from "B1_P8" to a certain logical address, it proves that the page stores invalid data and is waiting for garbage collection. In this case, the page is still "not available", and its "available state" field will be updated or maintained to "0".

[0135] Case 2 (no data): If there is no record about "B1_P8" in the P2L table, or by querying the block metadata, it is found that the entire physical block B1 to which "B1_P8" belongs is in the state of "erased / free", which finally proves that the page is a truly available free page. In this case, the processor 211 will judge that the physical page is in the "available" state, and update its "available state" field in the offset physical page list to "1".

[0136] Through this dual-checking mechanism combining L2P and P2L (or block metadata), the processor 211 can extremely accurately distinguish between the "contains invalid data" and "completely free" states of the physical page, thereby updating the available state of the offset physical page list and providing the most reliable space information for subsequent write decision-making.

[0137] By performing this periodic maintenance operation of synchronously updating the available state of the offset physical page to the offset physical page list, the processor 211 ensures that the "available state" field in the offset physical page list can always accurately reflect the latest space allocation situation.

[0138] In this way, in another embodiment, when data needs to be written, the processor 211 can directly filter the entries in the list with an "available status" of "1" to select the target entity page, avoiding the overhead of querying the L2P mapping table for secondary confirmation during writing, thereby significantly improving the efficiency of data matching and writing operations.

[0139] Next, in step S230, the processor 211 acquires the target data and its corresponding data attributes based on the write instruction. The acquisition of data attributes can be achieved in two main ways: one is by the host system 10 actively providing them, and the other is by the memory controller 210 internally determining them.

[0140] In one embodiment, the first approach involves the host system 10 determining and providing data attributes. In this implementation, the host system 10 can leverage its global understanding of the operating system, file system, and even the behavior of specific applications to predict data access characteristics. For example, the host system 10 can generate a clear identifier for the target data to be written based on information such as the file's access frequency and the data's role in the application (e.g., database index vs. archived log). This identifier indicates to the storage device 20 whether the data's attribute is a "hot data attribute" or a "cold data attribute."

[0141] When host system 10 needs to write data, it constructs a write instruction and encapsulates the generated identifier along with the corresponding write data within that instruction. For example, this identifier can be a specific field in the write instruction metadata.

[0142] When the memory controller 210 receives the write instruction, the processor 211 performs a parsing operation. It precisely parses the identifier and the corresponding write data from the instruction. Then, the processor 211 determines the data attributes of the write data based on the parsed identifier content. For example, if the identifier's bit value is the first bit, the processor 211 interprets it as hot data according to a preset rule; if the identifier's bit value is the second bit, the processor 211 interprets it as cold data according to a preset rule. After determining the data attributes, the processor 211 not only stores the write data in the selected target entity page, but in some embodiments, it may also write the identifier itself for reference in subsequent internal data management tasks. In this way, the storage device 20 can directly utilize the global awareness of the host system to achieve accurate hot and cold data classification and storage.

[0143] Figure 7 This is a flowchart illustrating data writing and matching according to an embodiment of this disclosure.

[0144] Referring to Figure 7 In step S710, the processor 211 obtains a write instruction and determines the target data to be written and its corresponding data attribute, e.g. hot data attribute or cold data attribute.

[0145] After determining the data attribute, the flow enters different branches according to the type of the data attribute.

[0146] If the data attribute of the target data is a hot data attribute, the flow enters step S720. In this step, the processor 211 queries the offset entity page list and selects one or more available target first entity pages with the first offset attribute (i.e. left offset attribute) from the list. Subsequently, the processor 211 controls the writing of the target data into the selected target first entity pages.

[0147] For example, a log file frequently accessed by the host system 10 (whose data attribute is determined to be a hot data attribute) needs to be written into the storage device 20. Upon receiving the write instruction, the processor 211 retrieves the offset entity page list, finds one or more free offset entity pages marked with the first offset attribute, and then writes the data of the log file into these entity pages.

[0148] Conversely, if the data attribute of the target data is a cold data attribute, the flow enters step S730. In this step, the processor 211 also queries the offset entity page list, but this time selects one or more available target second entity pages with the second offset attribute (i.e. right offset attribute) from the list. Subsequently, the processor 211 controls the writing of the target data into the selected target second entity pages.

[0149] For example, a backup file for long-term archiving (whose data attribute is determined to be a cold data attribute) needs to be written into the storage device 20. Upon receiving the write instruction, the processor 211 retrieves the offset entity page list, finds one or more free offset entity pages marked with the second offset attribute, and then writes the data of the backup file into these entity pages.

[0150] By Figure 7 The method of the present disclosure can ensure that data with different access patterns are precisely written into physical storage areas that best suit their characteristics, thereby maximizing the use of aging storage cells while improving the overall reliability of the data.

[0151] However, it is worth mentioning that this matching strategy ensures that hot data is stored in entity pages with a critical voltage trend that tends to decrease, while cold data is stored in entity pages with a critical voltage trend that tends to increase, thereby achieving the matching pairing of data characteristics and physical characteristics of storage areas.

[0152] In more detail, the technical principle of the matching rule is that, by corresponding configuration of the data attribute with a specific access pattern and the offset attribute with a specific physical failure mode, the access characteristics of the data itself can be used to circumvent or suppress the physical defects of the storage area, thereby continuing to use the already aged physical page while ensuring data reliability.

[0153] When the data attribute of the target data is determined to be a hot data attribute, the processor 211 selects a physical page with a first offset attribute as a storage location from the offset physical page list. The first offset attribute indicates that the critical voltage distribution of the physical page tends to decrease. The root cause of this physical phenomenon is the charge leakage of the storage cell due to aging, and the main technical challenge is the weakening of the data retention capability, which is a static failure risk related to long-term data storage. Due to the frequent reading or updating characteristics of hot data, its static residence time in a certain physical location is short.

[0154] On the one hand, for frequently updated hot data, each update or rewrite operation is essentially a programming operation. This programming operation re-injects a target charge amount into the storage cell, thereby refreshing the physical state of the storage cell and resetting its data retention period. In addition, many target data identified as hot data also have a short effective life cycle. For example, the swap file of the operating system or the temporary data of the application program, whose content is updated rapidly, the old version of the data will soon be marked as invalid data. Writing such data into a physical page with a first offset attribute (left bias) takes advantage of the "ephemeral" nature of the data. Since the data itself does not need to be stored for a long time, the inherent defects of the physical page in data retention capability do not pose a substantial threat to the integrity of such data. This matching method not only takes advantage of the access pattern of hot data to circumvent the physical defects of the physical page, but also takes advantage of the life cycle characteristics of hot data, further improving the rationality and technical benefits of this pairing strategy.

[0155] On the other hand, for frequently read hot data, it also has a positive effect on circumventing the data retention risk. The memory controller 210 can monitor the health of the data during each read operation, for example, by recording the number of error bits corrected by the error correction code (ECC) mechanism. When the processor 211 detects that the number of error bits of a frequently read physical page has a rising trend, even if the data has not reached the read failure level, the processor 211 can trigger an internal data refresh or data relocation operation. The action specifically can include: reading out the data in the physical page and re-writing it to a new or original physical location after correction. This preventive refresh mechanism triggered by frequent reading can also effectively reset the data retention period.

[0156] Therefore, no matter through the direct overwrite of the update operation or through the indirect refresh triggered by the frequent reading, the dynamic access behavior of the hot data constitutes a periodic compensation for the static charge leakage defect of the storage unit, so that the data is always refreshed before being invalidated due to charge leakage, thereby avoiding the risk of data retention failure.

[0157] Correspondingly, when the data attribute of the target data is determined as a cold data attribute, the processor 211 selects an entity page with a second offset attribute as a storage location from the offset entity page list. The second offset attribute indicates that the threshold voltage distribution of the entity page tends to rise. This physical phenomenon is usually related to electron traps in the tunnel oxide layer, and the main technical challenge is the reduction of the programming window margin and the increase of the sensitivity to program disturb, which is a dynamic failure risk related to the write operation. And because of the characteristics of long-term static and sparse access after writing, the programming operation frequency of the cold data and its adjacent physical area is extremely low. Writing cold data into such entity pages can reduce the probability of triggering program disturb events from the source, thereby avoiding the defect that the entity page is sensitive to the write operation. In addition, the storage unit with a higher threshold voltage usually has its internal charge bound more firmly, which objectively has a relatively better data retention capability. This feature is exactly matched with the need for long-term and stable storage of cold data.

[0158] Through the above matching logic, the method of the present disclosure matches the most suitable storage data type for entity pages with different aging characteristics, so that the entity pages can continue to provide services under the conditions that can best avoid their main physical defects, thereby prolonging the effective service life of the entire memory module 200.

[0159] Through the systematic execution of the above four steps, the memory management method of the present disclosure realizes dynamic storage management based on the actual physical state, can intelligently match according to the real offset condition of the entity page and the access characteristics of the data, effectively prolongs the overall service life of the memory and improves the reliability of data storage.

[0160] Figure 8 is a flowchart of a data write matching method according to another embodiment of the present disclosure.

[0161] Referring to Figure 8 The flowchart depicts two different write decision modes: threshold mode and dynamic mode. These two modes provide the memory controller 210 with flexibility to balance performance overhead and management accuracy under different system conditions.

[0162] The process starts at step S810, where the processor 211 obtains a write instruction and determines the target data to be written and its corresponding data attribute (e.g. hot data attribute or cold data attribute).

[0163] In one embodiment, the memory controller 210 can be configured to operate in a "threshold mode". This mode is designed to avoid frequent execution of futile matching attempts when the available off-set physical page resources are insufficient, thereby reducing system overhead. In this mode, the process proceeds to decision step S820. The processor 211 queries the off-set physical page inventory to obtain the total available capacity of the off-set physical pages corresponding to the data attribute of the current target data. For example, if the target data is hot data, the total available capacity of all first off-set attribute (left off-set) physical pages is obtained. Subsequently, the processor 211 compares the total available capacity with a pre-determined total capacity threshold.

[0164] If the total available capacity is greater than the corresponding total capacity threshold (the result of step S820 is "Yes"), it indicates that the system has accumulated sufficient number of specific type of off-set physical pages that can be used for targeted writing. In this case, the process proceeds to step S830, where the processor 211 performs the matching selection operation, i.e. selects the target physical page corresponding to the data attribute from the off-set physical page inventory.

[0165] On the contrary, if the total available capacity is not greater than the corresponding total capacity threshold (the result of step S820 is "No"), it indicates that the current available specific type of off-set physical page resources are insufficient. To avoid futile search overhead, the processor 211 will skip the matching selection step and the process proceeds directly to step S850, where the target data is written into a regular standard physical page.

[0166] In another embodiment, the memory controller 210 can be configured to operate in a "dynamic mode". This mode performs instant resource check for each write request to achieve the most refined data placement. In this mode, the process proceeds to decision step S821. The processor 211 again obtains the total available capacity of the off-set physical pages corresponding to the data attribute of the current target data, but this time compares it with the size of the target data to be written.

[0167] If the total available capacity is greater than the size of the target data (the result of step S821 is "Yes"), it indicates that there is sufficient space to perform targeted writing. The process then proceeds to step S830, where the processor 211 performs the matching selection operation.

[0168] On the contrary, if the total available capacity is not greater than the size of the target data (the result of step S821 is "No"), it indicates that there is not enough specific type of offset entity page to accommodate the data. The flow also skips the matching selection step and directly enters step S850 to write the target data into a standard entity page.

[0169] After step S830 is performed (a matching target entity page is selected), the flow enters step S840, and the processor 211 writes the target data into the selected target entity page. For those flows that skip the matching due to the failure of the conditions in steps S820 or S821, they all enter step S850, and the processor 211 writes the target data into a standard entity page that is not recorded in the offset entity page list to ensure the completion of the write operation.

[0170] By Figure 8 The method of the present disclosure can flexibly adjust its data placement strategy according to the design requirements or the running state of the system in the two optional modes shown. The threshold mode focuses on the macro system efficiency, and the dynamic mode focuses on matching the write data to the appropriate entity page as much as possible for each write operation.

[0171] In more detail, the core idea of the dynamic mode is to immediately perform matching write as long as there is enough type-matched offset entity page to accommodate the current write data. When receiving a write request each time, the processor 211 will calculate the total available capacity of the offset entity page matching the target data attribute in real time, and compare it with the size of the current data to be written. For example, if a 2MB hot data is to be written, as long as the total available capacity of all the left offset pages is greater than or equal to 2MB, the matching will be performed.

[0172] On the other hand, the threshold mode is a macro-control idea management strategy, and its core idea is to start the matching write mechanism for a type only when the resources of the offset entity page of the type accumulate enough to form a scale effect. The processor 211 will compare the total available capacity of the offset entity page matching the target data attribute with a preset fixed total capacity threshold. For example, the system can set an 8GB left offset page total capacity threshold. Only when the total capacity of all available left offset pages exceeds 8GB, the system will start to write hot data into these left offset pages. Before that, even if there are scattered left offset pages available, the hot data will be written as ordinary data into a standard entity page.

[0173] In some embodiments, the processor 211 switches between the threshold mode and the dynamic mode based on workload characteristics.

[0174] When the workload is low, it indicates that the system is not heavily loaded and there are sufficient CPU cycles to perform fine-grained matching decisions. Thus, a more fine-grained and immediate dynamic mode can be utilized to prioritize the data reliability of each write.

[0175] Conversely, when the workload is high, it indicates that the system is under high concurrency pressure and I / O throughput and low latency should be prioritized at this time. Thus, the processor 211 can switch to the threshold mode to reduce decision overhead and thus improve overall write performance.

[0176] In other embodiments, the health status of the device can also be used as a basis for switching strategies.

[0177] For example, when the overall wear level (e.g., average P / E times) of the storage device 20 reaches a high level, or the proportion of offset physical pages in the total available space is high, the risk of data reliability increases. At this time, the dynamic mode should be switched to find the safest storage location for each piece of data as much as possible to extend the remaining service life of the device.

[0178] Conversely, in the early stage of the life cycle of the storage device 20, most of the storage units are in a healthy state, and the Vth offset problem is not prominent. At this time, the performance-priority threshold mode can be used by default to provide the best user experience.

[0179] Figure 9 is a schematic diagram showing offset inventory management according to an embodiment of the present disclosure.

[0180] Referring to Figure 9 In an embodiment, the processor 211 records the information of the identified offset physical pages in an offset physical page inventory after performing the voltage offset identification operation. As shown in Figure 9 As shown in the upper half of the table T91, the inventory is used to record the state of each offset physical page in detail.

[0181] Specifically, the inventory can include the following fields:

[0182] (1) Physical address (also referred to as physical address): This field is used to uniquely identify a physical page, and its format can be "physical block number_ physical page number", for example, "B1_P1" means the first physical page belonging to physical block B1.

[0183] (2) Offset direction: This field records the offset attribute of the physical page, for example, "left" means that the physical page has the first offset attribute of the critical voltage tending to decrease, and "right" means that it has the second offset attribute of the critical voltage tending to increase.

[0184] (3) Available: This field is used to indicate whether the entity page is currently available for data write operation. For example, the value "1" can represent available, and the value "0" can represent occupied. It should be noted that the field of available status is optional. For example, in other embodiments, the offset entity page list only contains the physical address and the offset direction fields. The processor 211 can determine whether an offset entity page is available by looking up the logical-to-entity address mapping table or the entity-to-logical address mapping table.

[0185] In another embodiment, the processor 211 records the determined offset entity block and the offset attribute of the entity block in the offset entity block list. For example, during the execution of step S220, the processor 211 can also implement an optimized management strategy based on entity blocks to improve management efficiency. When the number of offset entity pages with the same offset attribute in a certain entity block reaches an offset number threshold, the processor 211 records the entity block and its same offset attribute in the offset entity block list, and removes the individual records of these entity pages from the offset entity page list, thereby reducing the management burden and cache requirements.

[0186] The optimization process is shown by arrows A91 to A94. First, as shown by arrow A91, the processor 211 scans the entire offset entity page list T91 to count the number of entity pages with the same offset attribute in the same entity block. In this example, the processor 211 sets an offset page number threshold, for example, 4. The processor 211 finds by scanning that in the entity block B1, there are 6 entity pages (B1_P1 to B1_P6) with the "left" offset attribute, and the number (6) exceeds the preset threshold (4).

[0187] Next, as shown by arrow A92, based on the above statistical result, the processor 211 determines the overall offset attribute of the entire entity block B1 as "left offset", i.e., the first offset attribute.

[0188] Subsequently, the processor 211 performs a list update operation. Specifically, as shown by arrow A93, the processor 211 removes all entity page information related to the entity block B1 (i.e., the entries of B1_P1 to B1_P8) from the original offset entity page list T91. Meanwhile, in operation A94, the processor 211 records the physical address of the entity block B1 and its determined overall offset attribute ("left") as a new entry in an offset entity block list. As Figure 9 As shown in the lower part of the table T92, the data structure of the offset entity block list is simplified, and only the block-level address and attribute need to be recorded.

[0189] After the optimization of the list is completed, the data write matching logic of the processor 211 is also adjusted accordingly. When a target data with a specific data attribute (e.g., a hot data attribute) needs to be written, the processor 211 can select one or more target entity blocks (in this example, the entity block B1) with a corresponding offset attribute (e.g., the first offset attribute) from the offset entity block list T92 to write the target data to one or more target entity pages of the one or more target entity blocks (the processor 211 expects that all entity pages of the target entity block correspond to the same offset attribute as the target entity block). After the target entity block is selected, the processor 211 can further find a specific available target entity page inside the target entity block to write the target data by using an internal bitmap or other free space management mechanism. In this case, the processor 211 presets that all available entity pages of the entity block B1 are of the first offset attribute (the left offset attribute).

[0190] By Figure 9 The offset list management optimization mechanism shown in the figure, the method of the present disclosure can further realize dynamic adjustment of the management granularity from the page level to the block level, while maintaining the accuracy of the offset attribute management, and reducing the storage overhead and query complexity of the list.

[0191] Figure 10 is a flowchart of a data write method based on an offset entity block list according to an embodiment of the present disclosure.

[0192] Referring to Figure 10 In step S1010, after the voltage offset identification operation is performed, the processor 211 records the offset attributes of the obtained entity pages in an offset entity page list.

[0193] Next, in step S1020, the processor 211 performs a list optimization conversion operation. Specifically, when the processor 211 finds by statistics that the number of offset entity pages with the same offset attribute located in a certain entity block reaches a preset offset page number threshold, the processor 211 records the entity block and the corresponding same offset attribute as a new entry in an offset entity block list. At the same time, the processor 211 removes the information of all offset entity pages belonging to the entity block from the original offset entity page list. Through this step, the system realizes the aggregation of the management granularity from the page level to the block level, thereby reducing the subsequent query and management overhead.

[0194] After the optimization of the list is completed, the process enters the data write matching phase of step S1030. When the processor 211 receives a write instruction and determines the data attribute of the target data, it directly queries the offset entity block list. The processor 211 selects one or more target entity blocks with corresponding offset attributes from the offset entity block list according to the data attribute of the target data. After the target entity block is selected, the processor 211 further searches for one or more specific available target entity pages within the target entity block to finally write the target data.

[0195] By the process shown in the figure, the adaptive management mechanism from the page level to the block level of the present disclosure enables the method of the present application to maintain a high management efficiency after long-term use, and is particularly suitable for large-capacity storage devices. Figure 10

[0196] It should be noted that the offset entity page list or the offset entity block list is not only used to passively respond to the execution of the write instruction, but also can be adapted to active management of the memory module.

[0197] In another embodiment, after the processor 211 establishes and records the offset entity page list or the offset entity block list according to the method of the present disclosure, the list can not only be used to guide the writing of new data, but also be used as a basis for performing differential background management tasks. In this way, the memory controller 210 can actively and more targetedly manage storage areas with different aging characteristics.

[0198] For example, the processor 211 can perform a differential garbage collection (GC) strategy. When it is necessary to recover storage space, the processor 211 can preferentially select entity blocks marked as having a first offset attribute (left offset) as the target of garbage collection. The technical reason is that, according to the matching rule of the present application, the entity blocks mainly store hot data, and hot data generally has a high invalidation rate (i.e., quickly becomes invalid data). Therefore, the recovery efficiency (i.e., the proportion of invalid data that can be recovered) of garbage collection performed on these entity blocks is generally higher, and the valid data that needs to be moved is less, thereby reducing the write amplification caused by the garbage collection operation itself. In addition, the valid data in these entity blocks with left offset attributes is more suitable for being moved to other entity blocks through the GC operation to avoid the risk of long-term storage caused by the left bias of the critical voltage distribution.

[0199] ​In another example, the memory controller 210 periodically reads data and checks its ECC correction status as a background task to maintain data integrity. Based on the offset entity page list, the processor 211 can set a shorter inspection period (e.g., once a week) for entity pages with the first offset attribute (left offset) than a standard setting, and set a longer regular period (e.g., once a month) for entity pages with the second offset attribute (right offset) or standard. By checking the area with weaker data retention ability more frequently, problems can be detected earlier and data refresh can be performed before the data becomes completely unreadable due to charge leakage, thereby improving the reliability of long-term data.

[0200] In other embodiments, the processor 211 can perform a dynamic error correction code (ECC) strength configuration strategy. In some special cases (e.g., both the available standard entity pages and the right offset entity pages are exhausted), an important cold data may have to be temporarily written to a left offset entity page. In this case, in order to compensate for the lack of data retention ability of the entity page, the processor 211 can apply an ECC encoding with higher strength and stronger error correction ability than the standard ECC scheme when writing to the page. Although this will bring some storage overhead, it can provide additional security for data stored in the known risk area as a dynamic and targeted compensation measure. It should be noted that the present disclosure is not limited thereto, for example, any data written to a left offset entity page / entity block can be written with enhanced ECC encoding.

[0201] The embodiment also provides a computer program product comprising computer readable code, or a non-volatile computer readable storage medium carrying computer readable code, which, when executed in a processor, causes the processor to perform the steps of the above-mentioned memory management method. The computer program product can be implemented by hardware, firmware, software or a combination thereof. In an optional embodiment, the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK) and the like.

[0202] In summary, the memory management method and the memory controller provided by the present disclosure achieve intelligent configuration of storage resources and effective extension of the service life of the memory through systematic voltage offset identification and data classification storage mechanisms.

[0203] Firstly, the technical solution of the present disclosure establishes an opportunistic and low-overhead health monitoring mechanism by triggering a voltage shift identification operation in response to a read operation failure. Instead of performing periodic and comprehensive scanning on all storage entities, the method performs in-depth physical characteristic diagnosis on the corresponding entity page when a read error actually occurs. This enables the memory controller to accurately capture entity pages that begin to show signs of aging and obtain the main shift trend of their critical voltage distribution, which is the key health status information, without increasing the burden of normal read-write operations.

[0204] In addition, the present disclosure realizes the acquisition of the current critical voltage of the storage unit by the combined application of soft decision reading and soft decoding technology. This method of combining logical correction with physical measurement can accurately infer the current critical voltage of the storage unit in the case of read failure, providing a reliable data basis for subsequent shift attribute determination.

[0205] In terms of statistical determination of shift attributes, the present disclosure uses a statistical analysis mechanism based on a quantity threshold to determine the dominant shift direction of the entity page. By comparing the number distribution of left-shift and right-shift storage units, the system can identify the overall aging characteristics of the entity page, ensuring the stability of the overall shift attribute classification of the entity page.

[0206] The shift entity page list management mechanism established by the present disclosure realizes dynamic tracking and recording of the storage state. The list not only records the physical address and shift attribute of the entity page, but also improves the efficiency of data writing through the available state field. In order to improve management efficiency, the present disclosure further provides an optimization strategy for converting from page level to block level. When the number of entity pages with the same shift attribute in the same entity block reaches a preset threshold, the system automatically raises the management granularity to the block level, thereby reducing storage overhead and query complexity.

[0207] Most importantly, the method of the present disclosure introduces the data attribute (e.g., hot data attribute or cold data attribute) of the target data as the key information of the data placement decision. This enables the management strategy to take into account both the "physical failure mode" of the storage medium and the "logical access mode" of the data to be stored. By identifying the data attribute of the data, the memory controller can predict the tolerance of different types of data to physical defects of a specific storage unit, thereby providing a prerequisite for intelligent matching. Specifically, by matching the data attribute with the offset attribute of the entity page to select the target storage entity and write data, this is the core link to achieve the technical effect: writing frequently accessed "hot data" to an entity page with a tendency to decrease in critical voltage (first offset attribute), which can naturally refresh the data using the frequent read-write operations of hot data, thereby avoiding the weak data retention capability of such entity pages; accordingly, writing infrequently accessed "cold data" to an entity page with a tendency to increase in critical voltage (second offset attribute), which can take advantage of the long-term static characteristics of cold data after writing to avoid the programming interference sensitivity of such entity pages. This targeted matching strategy makes the entity pages with different aging characteristics be reasonably utilized, avoids the physical defects of entity pages with different aging characteristics, and prolongs the space utilization rate of the storage device and improves the reliability of data retention.

[0208] The technical contribution of the present disclosure lies in not only identifying the universal phenomenon of flash aging, but also further distinguishing different aging physical characteristics, i.e., leftward offset and rightward offset of critical voltage. Based on this distinction, the present disclosure proposes a differentiated data management scheme that matches data with different access characteristics (e.g., hot data and cold data) with storage areas with specific physical failure modes. This management mechanism, which starts from physical layer characteristics and optimizes data write destinations, provides an effective technical architecture for improving the durability and reliability of modern storage systems, enabling the performance and reliability of the storage device to decay more smoothly over its life cycle, thereby providing users with a more stable and longer-lasting user experience.

[0209] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for part or all of the technical features; and these modifications or substitutions do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory management method applied to a memory controller, the memory controller being used to control a storage device configured with a memory module, characterized in that, The method includes: In response to a read failure operation of a certain entity page among multiple entity pages in the memory module, a voltage offset identification operation is performed on the entity page to obtain the offset attribute of the entity page; Record the offset attribute of the entity page in the offset entity page list; Based on the write command, obtain the target data and its corresponding data attributes; and Based on the data attributes of the target data, a target entity page whose offset attribute corresponds to the data attribute is selected from the plurality of entity pages of the memory module, so as to write the target data into the target entity page.

2. The method according to claim 1, characterized in that, The physical page includes multiple storage units, and the voltage offset identification operation includes: Obtain the current critical voltage of each memory cell in the physical page; Each current critical voltage is compared with the initial critical voltage of the corresponding memory cell to determine the offset direction of all memory cells; and The offset attribute of the entity page is determined based on the offset direction of all the storage units in the entity page.

3. The method according to claim 2, characterized in that, Determining the offset attribute of the entity page based on the offset direction of all the storage units in the entity page includes: Count the first number of first storage units corresponding to the first offset direction and the second number of second storage units corresponding to the second offset direction; When the first quantity exceeds the offset unit quantity threshold, the offset attribute of the entity page is determined to be the first offset direction; and When the second quantity exceeds the offset unit quantity threshold, the offset attribute of the entity page is determined to be the second offset direction.

4. The method according to claim 2, characterized in that, The step of obtaining the current critical voltage of the storage cell in the entity page includes: Based on the physical layer information obtained when the read operation fails, the correct data stored in the entity page is recovered; and Using the correct data as a logical benchmark, and in conjunction with the physical layer information, the current critical voltage of each memory cell in the physical page is determined.

5. The method according to claim 4, characterized in that, The process of recovering the correct data stored in the entity page based on the physical layer information obtained when the read operation fails includes: Perform a soft decision read operation on the entity page to obtain soft information; Based on the soft information, a soft decoding operation is performed on the data stored in the entity page to obtain the correct data stored in the entity page; and Using the correct data as a logical benchmark, and combining it with the soft information, the current critical voltage of each memory cell in the physical page is determined.

6. The method according to claim 1, characterized in that, The data attributes obtained based on the write command for the target data include: Parse the target data from the write instruction to extract the identifier generated by the host system to indicate whether the data attribute is a hot data attribute or a cold data attribute, and the corresponding write data. Determine the data attribute of the write data based on the identifier, and write the identifier and the write data to the target entity page.

7. The method according to claim 6, characterized in that, The offset attribute includes a first offset attribute and a second offset attribute, and the method further includes: When the data attribute of the target data is the hot data attribute, the first entity page corresponding to the first offset attribute is selected from the offset entity page list as the target first entity page to store the target data; and When the data attribute of the target data is the cold data attribute, the second entity page corresponding to the second offset attribute is selected from the offset entity page list as the target second entity page to store the target data.

8. The method according to claim 7, characterized in that, Before selecting the target entity page corresponding to the offset attribute and the data attribute, the method further includes: Obtain the first total capacity of the first entity page and the second total capacity of the second entity page recorded in the offset entity page list. The step of selecting the first entity page corresponding to the offset attribute from the offset entity page list as the target first entity page is performed only when the first total capacity is sufficient to store the target data. The step of selecting the second entity page corresponding to the second offset attribute from the offset entity page list as the target second entity page is performed only when the second total capacity is sufficient to store the target data.

9. The method according to claim 7, characterized in that, Before selecting the target entity page corresponding to the offset attribute and the data attribute, the method further includes: Obtain the first total capacity of the first entity page and the second total capacity of the second entity page recorded in the offset entity page list. The step of selecting the first entity page corresponding to the offset attribute from the offset entity page list as the target first entity page is performed only when the first total capacity is greater than the first total capacity threshold. The step of selecting the second entity page corresponding to the second offset attribute from the offset entity page list as the target second entity page is performed only when the second total capacity is greater than the second total capacity threshold.

10. The method according to claim 1, characterized in that, The availability status of each offset entity page in the offset entity page list is periodically obtained through the logical-to-entity address mapping table.

11. The method according to claim 1, characterized in that, The method further includes: Record the offset attribute of the entity page in the offset entity page list; When the number of multiple offset entity pages with the same offset attribute in a certain entity block reaches the offset page number threshold, the entity block and the same offset attribute are recorded in the offset entity block list, and the information of the multiple offset entity pages is removed from the offset entity page list.

12. The method according to claim 11, characterized in that, The step of selecting the target entity page whose offset attribute corresponds to the data attribute from the plurality of entity pages of the memory module according to the data attribute of the target data, and writing the target data to the target entity page, includes: Based on the data attributes of the target data, a target entity block corresponding to the offset attribute is selected from the offset entity block list to write the target data into an entity page in the target entity block, wherein the entity page is the target entity page corresponding to the offset attribute and the data attribute.

13. A memory controller for controlling a storage device configured with a memory module, the memory module comprising a plurality of physical pages, characterized in that, The memory controller includes: A memory interface control circuit, for electrically connecting to the memory module; and A processor, electrically connected to the memory interface control circuit, wherein the processor is configured to: In response to a read failure operation of a certain entity page among multiple entity pages in the memory module, a voltage offset identification operation is performed on the entity page to obtain the offset attribute of the entity page; Record the offset attribute of the entity page in the offset entity page list; Based on the write command, obtain the target data and its corresponding data attributes; and Based on the data attributes of the target data, a target entity page whose offset attribute corresponds to the data attribute is selected from the plurality of entity pages of the memory module, so as to write the target data into the target entity page.

14. The memory controller according to claim 13, characterized in that, The physical page includes multiple storage units, and the voltage offset identification operation includes: Obtain the current critical voltage of each memory cell in the physical page; Each current critical voltage is compared with the initial critical voltage of the corresponding memory cell to determine the offset direction of all memory cells; and The offset attribute of the entity page is determined based on the offset direction of all the storage units in the entity page.

15. The memory controller according to claim 14, characterized in that, Determining the offset attribute of the entity page based on the offset direction of all the storage units in the entity page includes: Count the first number of first storage units corresponding to the first offset direction and the second number of second storage units corresponding to the second offset direction; When the first quantity exceeds the offset unit quantity threshold, the offset attribute of the entity page is determined to be the first offset direction; and When the second quantity exceeds the offset unit quantity threshold, the offset attribute of the entity page is determined to be the second offset direction.

16. The memory controller according to claim 14, characterized in that, The step of obtaining the current critical voltage of the storage cell in the entity page includes: Perform a soft decision read operation on the entity page to obtain soft information; Based on the soft information, a soft decoding operation is performed on the data stored in the entity page to obtain the correct data stored in the entity page; and Using the correct data as a logical benchmark, and combining it with the soft information, the current critical voltage of each memory cell in the physical page is determined.

17. The memory controller according to claim 13, characterized in that, The data attributes obtained based on the write command for the target data include: Parse the target data from the write instruction to extract the identifier generated by the host system to indicate whether the data attribute is a hot data attribute or a cold data attribute, and the corresponding write data. Determine the data attribute of the write data based on the identifier, and write the identifier and the write data to the target entity page.

18. The memory controller according to claim 17, characterized in that, The offset attribute includes a first offset attribute and a second offset attribute, and the processor is further configured to: When the data attribute of the target data is the hot data attribute, the first entity page corresponding to the first offset attribute is selected from the offset entity page list as the target first entity page to store the target data; as well as When the data attribute of the target data is the cold data attribute, the second entity page corresponding to the second offset attribute is selected from the offset entity page list as the target second entity page to store the target data.

19. The memory controller according to claim 13, characterized in that, The processor is also configured to: Record the offset attribute of the entity page in the offset entity page list; When the number of multiple offset entity pages with the same offset attribute in a certain entity block reaches the offset page number threshold, the entity block and the same offset attribute are recorded in the offset entity block list, and the information of the multiple offset entity pages is removed from the offset entity page list.

20. The memory controller according to claim 19, characterized in that, The step of selecting the target entity page whose offset attribute corresponds to the data attribute from the plurality of entity pages of the memory module according to the data attribute of the target data, and writing the target data to the target entity page, includes: Based on the data attributes of the target data, a target entity block corresponding to the offset attribute is selected from the offset entity block list to write the target data into an entity page in the target entity block, wherein the entity page is the target entity page corresponding to the offset attribute and the data attribute.

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