Embedded wireless sensing test wafer

Abstract

The embedded wireless sensing test wafer is characterized in that the embedded wireless sensing test wafer comprises an upper silicon wafer, a lower silicon wafer and a circuit board, the upper silicon wafer and the lower silicon wafer are clamped on the two sides of the circuit board, the surfaces, facing the circuit board, of the upper silicon wafer and the lower silicon wafer are subjected to laser engraving or mechanical fine carving to form containing grooves, and the circuit board is embedded in the containing grooves; the thickness of the upper silicon wafer is 0.7-0.9 mm, the thickness of the lower silicon wafer is 0.3-0.4 mm, and the overall total thickness of the upper silicon wafer and the lower silicon wafer clamping the circuit board is smaller than or equal to 1.2 mm. The thickness similar to that of an actually produced wafer is realized, the authenticity of measurement is improved, the internal stress of the wafer is effectively eliminated by the heat treatment process, the reliability of a product is improved, the service life of the product is prolonged, the risk of processing fragments is reduced by the overall processing process, and the production cost is reduced.

Description

An embedded wireless sensor test wafer Technical Field

[0001] This invention relates to the field of semiconductor fabrication technology, and more specifically to an embedded wireless sensing test wafer for in-situ multiphysics detection in semiconductor manufacturing processes. Background Technology

[0002] In the semiconductor integrated circuit (IC) wafer manufacturing process, it is necessary to monitor various parameters of the wafer in real time and in situ, such as temperature, pressure, current, and voltage, to ensure process stability and improve product yield. Wireless wafer testing systems, leveraging wireless communication technology, enable data transmission between the wafer and external testing equipment without the need for wired connections. This offers advantages such as high testing flexibility and no interference with the manufacturing process, making it a mainstream monitoring solution.

[0003] Existing wireless wafers typically embed sensors and test circuits on or inside the wafer surface. The sensors collect parameters and convert them into digital signals, which are then encoded by a wireless communication chip and transmitted to external devices. For example, the semiconductor vacuum chamber wireless temperature measurement device disclosed in Chinese Patent Publication No. CN119124394A uses a structure where the wireless temperature measurement component is sandwiched between upper and lower silicon wafers. It collects the wafer temperature through the temperature measurement device and uploads it to the cloud, eliminating the contamination problems associated with wired temperature measurement and reducing manufacturing difficulty by eliminating the need for through-holes in the chamber.

[0004] However, existing wireless sensor wafers and similar sensor carrier wafers still have significant technical defects: First, their overall thickness is too large, and their shape differs greatly from that of wafers used in actual production. This makes it impossible to accurately reproduce the stress, heat, and electrical environment experienced by the wafer in actual manufacturing processes, leading to distorted monitoring data. Furthermore, due to the thickness discrepancy, they cannot be directly adapted to existing semiconductor production line equipment, requiring additional line adjustments and increasing production costs. Second, their anti-interference capability is insufficient. In high electromagnetic interference environments such as radio frequency plasma and electrostatic chuck processes, they are easily affected by electromagnetic fields and electrostatic high voltages, resulting in poor circuit stability and reduced monitoring accuracy. Third, their etching resistance is poor. In plasma etching processes, the wafer surface is easily corroded by etching gases, leading to the exposure of internal electronic components. This not only affects the lifespan of the equipment but also contaminates the process chamber. Fourth, for advanced processes such as 3D integrated circuit stacking, traditional wafer thickness cannot meet the intercalation monitoring requirements, and thermal stress concentration is easily generated during high-temperature and high-pressure stacking, resulting in wafer breakage and decreased measurement accuracy. Fifth, the silicon wafer thickness design lacks scientific consideration and cannot simultaneously meet the multiple requirements of wireless signal penetration, circuit embedded installation, mechanical structural strength, and production line size adaptation. Thick silicon wafers are prone to shielding radio frequency signals, while thin silicon wafers are prone to breakage during automated operations.

[0005] To solve the above technical problems, there is an urgent need to develop an embedded wireless sensing test wafer with a thickness verified by scientific experiments, which is highly matched with the shape and size of actual production wafers, has excellent anti-interference and etching resistance, and is compatible with advanced semiconductor manufacturing processes. Summary of the Invention

[0006] The purpose of this invention is to address the shortcomings of existing technologies by providing an embedded wireless sensing test wafer that improves the authenticity and accuracy of measurements, is unaffected by interference from radio frequency plasma or electrostatic chucks, and greatly enhances the ability and efficiency of semiconductor process monitoring.

[0007] The present invention achieves the above-mentioned objectives by adopting the following technical solution: an embedded wireless sensing test wafer, characterized in that it includes an upper silicon wafer, a lower silicon wafer, and a circuit board, wherein the upper and lower silicon wafers clamp the circuit board, and the area of ​​the circuit portion is hollowed out on the surface of the upper and lower silicon wafers by laser engraving or mechanical precision engraving to accommodate the circuit board; the thickness of the upper silicon wafer is 0.8mm, the thickness of the lower silicon wafer is 0.38mm, and the total thickness of the upper and lower silicon wafers clamping the circuit board is controlled within 1.2mm, which is close to the thickness of the actual production wafer.

[0008] The system includes an upper silicon wafer, a lower silicon wafer, and a circuit board. The upper and lower silicon wafers are clamped together on both sides of the circuit board. Receiving grooves are formed on the surfaces of the upper and lower silicon wafers facing the circuit board by laser engraving or mechanical precision carving. The circuit board is fitted into the receiving grooves. The thickness of the upper silicon wafer is 0.7-0.9mm, and the thickness of the lower silicon wafer is 0.3-0.4mm. The total thickness of the upper and lower silicon wafers clamping the circuit board is controlled within 1.2mm. The above thickness parameters are the optimal parameter combination obtained after hundreds of experiments to meet four core requirements: embedded installation of wireless sensor circuit boards, penetration and transmission of wireless signals, mechanical structural strength of wafers, and size adaptation with actual wafers in semiconductor production lines. This achieves a precise balance of multiple technical effects.

[0009] As a further explanation of the above solution, the circuit board is a polyimide FPC flexible circuit board, and the electronic components integrated on the circuit board are all surface mount type or unpackaged type, so as to minimize the overall thickness of the circuit board and adapt to the accommodating slot design of the upper and lower silicon wafers to ensure the accurate realization of the wafer thickness parameters.

[0010] Furthermore, after the upper and lower silicon wafers are laser-engraved / mechanically precision-carved, they need to undergo a heat treatment process to eliminate the internal stress generated during the silicon wafer processing and prevent wafer breakage due to stress concentration in subsequent processes. The heat treatment process uses a wafer rapid heat treatment equipment, which introduces argon gas to form a positive pressure protective environment after vacuuming, and heat-treats at a constant temperature of 1000℃ for 30 minutes. Argon gas protection can prevent the silicon wafer surface from reacting with oxygen and nitrogen to form oxide films and nitrides, ensuring the stability of silicon wafer performance.

[0011] Furthermore, an etch-resistant coating is formed on the surface of the upper silicon wafer away from the circuit board. The etch-resistant coating is deposited by PVD physical vapor deposition. The main component of the coating is yttrium oxide, which can effectively resist the erosion of the silicon wafer by the etching gas in the plasma etching process, avoid the exposure of the internal circuit board, greatly improve the service life of the sensing test wafer, and at the same time prevent the components from being exposed and contaminating the process chamber.

[0012] Furthermore, both the upper and lower silicon wafers are phosphorus-doped silicon wafers. The phosphorus atoms doped in the silicon wafers can form an electromagnetic shielding layer, effectively shielding electromagnetic interference in the process environment. Alternatively, ion implantation can be used to inject elements such as phosphorus and boron into the surface of the silicon wafer, further improving the electromagnetic shielding effect and enhancing the wafer's anti-interference capability.

[0013] Furthermore, an insulating film is laid between the upper silicon wafer, the lower silicon wafer, and the circuit board. The main components of the insulating film are polyimide and radio frequency shielding coating. Polyimide can effectively isolate electrostatic high voltage, and radio frequency shielding coating further enhances the radio frequency interference shielding effect. It can resist the 1-3KV DC electrostatic high voltage generated by the electrostatic chuck at the bottom of the wafer, and avoid electrostatic interference with the normal operation of the circuit board.

[0014] Furthermore, the upper and lower silicon wafers are bonded together with an adhesive with a thickness controlled within 0.05mm. The bonding surfaces of the upper and lower silicon wafers are not on the same plane as the mounting surface of the circuit board, forming a misaligned structure. This prevents radio frequency interference from entering the wafer through side gaps, structurally blocking the interference path and ensuring circuit stability. Tests have shown that this structure allows the wafer to operate normally in common radio frequency environments of 2MHz, 13.56MHz, and 60MHz, without signal distortion or circuit stalling.

[0015] Furthermore, the circuit board integrates a battery, charging coil, charging device, communication chip, data storage module, main control chip, and array sensor module. The battery is a solid-state or semi-solid-state battery to avoid expansion in vacuum and high-temperature process environments. The charging coil and charging device are both located at the exact center of the sensing test wafer. Regardless of how the wafer rotates during the process, wireless charging can be achieved simply by aligning the center of the wafer with the center of the charging carrier, improving ease of use. The communication chip uses a wireless communication chip such as Bluetooth to achieve wireless transmission of monitoring data. The data storage module is a data storage chip that can store monitoring data in real time to avoid data loss. The main control chip uses an STM32 microcontroller to realize the acquisition, processing, and coordinated control of sensor data and various modules. The array sensor module uses a digital sensor chip or an analog sensor chip. If an analog sensor chip is used, an analog-to-digital converter circuit is added to the circuit board to convert analog signals to digital signals to meet data processing and transmission requirements.

[0016] The beneficial effects that can be achieved by adopting the above-mentioned technical solution in this invention are:

[0017] This invention employs an embedded wireless sensing test wafer structure primarily composed of an upper silicon wafer, a lower silicon wafer, and a circuit board. The upper and lower silicon wafers clamp the circuit board, and the circuit area is carved out on the surfaces of the upper and lower silicon wafers using laser engraving or mechanical precision carving to accommodate the circuit board. Through special structural design and processing technology, a thickness and shape similar to actual production wafers are achieved, improving the authenticity and accuracy of measurements. An innovative anti-etching and anti-interference structure allows the sensing test wafer to operate normally in a vacuum plasma environment, unaffected by interference from radio frequency plasma or electrostatic chucks. Multiple functional modules are integrated, enabling wireless communication, data storage, and multi-physics detection, significantly improving the capability and efficiency of semiconductor process monitoring. Through these innovations, this invention successfully solves the problem in existing technologies where sensor carrier wafers cannot accurately reflect the actual production status, providing a more accurate and reliable in-situ detection method for semiconductor processes. Attached Figure Description

[0018] Figure 1 is a schematic diagram of the structure of the present invention.

[0019] Figure 2 is a schematic diagram of the circuit connection of the present invention.

[0020] Figure 3 is a schematic diagram of the anti-etching structure of the present invention.

[0021] Explanation of reference numerals in the attached diagram: 1. Upper silicon wafer, 2. Lower silicon wafer, 3. Circuit board, 4. Battery, 5. Charging coil, 6. Charging device, 7. Communication chip, 8. Data storage, 9. Main control chip, 10. Array sensor module, 11. Etching-resistant coating, 12. Adhesive, 13. Insulating film. Detailed Implementation

[0022] In the description of this invention, it should be noted that the directional terms such as "center", "lateral", "longitudinal", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", and "counterclockwise" indicate the orientation and positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. They should not be construed as limiting the specific protection scope of this invention.

[0023] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features. Thus, the use of "first" and "second" to define a feature may explicitly or implicitly include one or more of that feature, and in the description of this invention, "at least" means one or more, unless otherwise explicitly specified.

[0024] In this invention, unless otherwise explicitly specified and limited, the terms "assembly," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can also refer to a mechanical connection; they can refer to a direct connection or a connection through an intermediate medium; or they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0025] In this invention, unless otherwise specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "below," and "over" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Above," "below," and "below" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0026] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings, making the technical solution and beneficial effects of the present invention clearer and more explicit. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, but should not be construed as limiting the present invention.

[0027] As shown in Figures 1-3, this invention relates to an embedded wireless sensor test wafer. Structurally, it employs a sandwich structure with upper and lower silicon wafers sandwiching a circuit board 3. The upper silicon wafer 1 has a thickness of 0.8 mm, and the lower silicon wafer 2 has a thickness of 0.38 mm, with the total thickness controlled within 1.2 mm, close to the thickness of actual production wafers. This thickness parameter has been verified through hundreds of experiments and can simultaneously meet the requirements of wireless signal penetration, circuit installation, mechanical strength, and production line compatibility. The upper silicon wafer 1 and lower silicon wafer 2 are hollowed out on their surfaces using laser engraving or mechanical precision carving, minimizing the height occupied by the circuit board 3 sandwiched between the upper and lower silicon wafers. Sharp parts should be minimized during silicon wafer hollowing, as sharp structures easily lead to stress concentration, causing wafer breakage during subsequent processing and use.

[0028] The advantages of simultaneously slotting the upper silicon wafer 1 and the lower silicon wafer 2 are:

[0029] 1. It can avoid excessive mechanical stress concentration caused by sinking the groove too deep on a wafer, which can easily cause the silicon wafer to break. The depth of the groove can also make the mechanical strength of the grooved part too low.

[0030] 2. The purpose of slotting is to embed the circuit inside the wafer. The thickness of the circuit is mainly on the electronic components. Therefore, the area of ​​the circuit board is slotted on one side of the silicon wafer, while the other side of the silicon wafer only needs to be slotted for the position of the components. This can reduce processing time, reduce the risk of processing debris, and reduce the cost of debris.

[0031] After processing, both upper silicon wafer 1 and lower silicon wafer 2 require heat treatment to eliminate internal stress before proceeding to the next step. The heat treatment equipment used is a rapid wafer heat treatment system at 1000℃. A vacuum is drawn, and then argon gas (oxygen forms an oxide film on the silicon wafer surface, and nitrogen at 1000℃ also forms a certain amount of nitrides on the wafer surface) is introduced as a protective gas. The process is carried out under positive argon pressure (at normal pressure, external oxygen may enter the reaction chamber) for 30 minutes.

[0032] In terms of circuit design, due to the thickness requirements of circuit board 3, polyimide (i.e., FPB circuit board) is selected as the circuit board material. The electronic components are surface-mount type, and the chips are preferably unpackaged. This is because the fabrication process of the sensor test wafer can be considered as chip packaging, thus saving some height. The circuit structure includes battery 4, charging coil 5, charging device 6, communication chip 7, data storage 8, main control chip 9, and array sensor module 10. Battery 4 uses a solid-state or semi-solid-state battery; other types of batteries are prone to expansion in a vacuum environment or after heating. Charging coil 5 and charging device 6 are located at the exact center of the sensor test wafer, so that regardless of the wafer's rotation, as long as the center of the sensor test wafer is aligned with the center of the charging carrier, the wireless sensor test wafer can be charged. Communication chip 7 uses a Bluetooth or other wireless communication chip; data storage 8 uses a data storage chip; the main control chip 9 can be an STM32 microcontroller; the array sensor 10 uses a digital sensor chip or an analog sensor, with an analog-to-digital conversion circuit added to read the sensor values.

[0033] Anti-etching treatment: Etching mainly focuses on the upper surface of the wireless sensor test wafer. By creating an anti-etching coating 11 on the surface of the upper silicon wafer 1, the etching effect on the sensor test wafer surface when the vacuum plasma chamber is filled with etching gas can be reduced, greatly improving the lifespan of the sensor test wafer. Without this coating, the upper silicon wafer 1 is easily etched, exposing electronic components, thus causing the anti-interference structure to fail and contaminating the chamber. The anti-etching coating is mainly composed of yttrium oxide. The anti-etching coating 11 is processed by PVD to deposit yttrium oxide onto the surface of the upper silicon wafer.

[0034] Anti-interference structure: The upper silicon wafer 1 and lower silicon wafer 2 are both phosphorus-doped silicon wafers. The phosphorus atoms doped in the silicon wafers can shield electromagnetic fields. Alternatively, ion implantation can be used to inject elements such as phosphorus and boron into the silicon wafer surface to improve the electromagnetic shielding effect. Insulating films 13 are provided on both the upper and lower silicon wafers 1 and 2. The main components of insulating films 13 are polyimide and RF shielding coating. Polyimide can isolate electric fields and block electrostatic high voltage at the bottom of the wafer during use (the voltage range of the electrostatic chuck adsorbing the wafer is generally within DC 1-3KV). The upper silicon wafer 1 and lower silicon wafer 2 are bonded together with adhesive 12, with a thickness within 0.05mm. The bonding surfaces of the upper and lower silicon wafers 1 and 2 are not on the same plane as the circuit board, preventing RF interference from entering the circuit from the wafer side. After testing, the sensor test wafer still maintained normal operation in RF environments of 2MHz, 13.56MHz, and 60MHz.

[0035] Example 1

[0036] In this embodiment, the circuit board 3 is a polyimide FPC circuit board, which integrates a battery 4, a charging coil 5, a charging device 6, a communication chip 7 (Bluetooth chip), a data storage module 8 (NAND flash memory chip), a main control chip 9 (STM32F103 microcontroller), and an array sensor module 10 (digital temperature and pressure composite sensor). All electronic components are surface mount type, and the circuit board 3 is adapted to be embedded in the receiving slot, making full use of the installation space provided by the upper silicon wafer.

[0037] After the upper and lower silicon wafers are processed, they are heat-treated using a wafer rapid thermal processing equipment: after vacuuming, argon gas is introduced to create a positive pressure environment, and the temperature is kept constant at 1000℃ for 30 minutes to eliminate internal stress. A yttrium oxide etching-resistant coating 11 with a thickness of 5μm is deposited on the outer surface of the upper silicon wafer 1 using PVD technology.

[0038] An insulating film 13 is laid between the upper and lower silicon wafers and the circuit board 3. The insulating film 13 is made of polyimide and radio frequency shielding coating and has a thickness of 0.02mm. The upper and lower silicon wafers are bonded together with epoxy resin adhesive 12. The adhesive 12 has a thickness of 0.04mm, and the bonding surface of the upper and lower silicon wafers is misaligned with the mounting surface of the circuit board 3 by 0.1mm to form a misaligned structure.

[0039] The overall thickness of the sensor test wafer prepared in this embodiment is 1.15mm, which is perfectly compatible with the actual mass production wafer thickness of semiconductor production lines. It can be directly connected to existing production line equipment without debugging. The silicon wafer achieves non-attenuated RF signal penetration, and the Bluetooth wireless communication signal reception rate is 100%. The mechanical strength of the wafer meets the requirements of automated production line operation. It has undergone 1000 automated loading and transmission tests without cracking or deformation. Temperature and pressure parameters are monitored in conventional semiconductor processes with a data error of ≤±0.5%. It can work continuously for 72 hours in a 13.56MHz RF environment without circuit failure and without data transmission distortion.

[0040] Example 2

[0041] This embodiment is a dedicated embedded wireless sensing test wafer for 3D integrated circuit stacking. Based on the basic structure of Embodiment 1, the following optimizations are made:

[0042] The thickness of the upper silicon wafer 1 is reduced to 0.3 mm, and the thickness of the lower silicon wafer 2 is reduced to 0.15 mm. A gradient transition accommodating groove is prepared by laser engraving, with the groove depth gradually increasing from 0.05 mm to 0.2 mm from the edge to the center. A 0.05 mm thick polyimide flexible buffer layer is added between the upper and lower silicon wafers and the circuit board 3. A 1 μm thick silicon nitride film is deposited on the surface of the silicon wafer using PECVD technology to improve the bending resistance. Plasma activated bonding technology is used to complete the bonding of the upper and lower silicon wafers at 350 °C. The heat treatment process is changed to multi-step annealing: annealing at 600 °C for 1 h → slowly heating to 900 °C and holding for 30 min → natural cooling to room temperature.

[0043] The overall thickness of the sensing test wafer prepared in this embodiment is 0.48 mm, which can be directly inserted into the interlayer of 3D integrated circuit stacked wafers. In a stacking environment of 200℃ and 5MPa, there is no cracking or deformation. The monitoring data error of temperature and stress between stacked layers is ≤±0.8%, which meets the intercalation monitoring requirements of 3D integrated circuit stacking process.

[0044] Example 3

[0045] In this embodiment, based on the basic structure of Embodiment 1, the following optimizations are made: the etch-resistant coating 11 is replaced with a yttrium oxide-hafnium oxide composite coating (mass ratio 7:3), with a coating thickness of 8μm and a density ≥99.5%; a multi-layer composite shielding structure is adopted: from the outside to the inside, it consists of a composite etch-resistant layer, a titanium alloy micron-level mesh layer (mesh aperture 5μm), an aluminum nitride dielectric layer (thickness 0.03mm), and a copper-aluminum alloy thin film layer (thickness 0.02mm); a 2nm thick nano-graphene layer is introduced on the silicon wafer surface to enhance electromagnetic shielding; a high dielectric constant polymer material is used to fill the gap between the circuit board 3 and the receiving groove; a DSP chip (TMS320F28335) is integrated on the circuit board 3, equipped with an adaptive interference cancellation algorithm and a machine learning interference model. The sensor test wafer prepared in this embodiment can work continuously for 168 hours in a plasma etching process (RF power 1000W, etching gas CF4+O2), with no obvious etching marks on the surface, an electromagnetic interference signal attenuation rate ≥99%, and a monitoring data error ≤±0.3%. It can realize accurate real-time monitoring of the plasma etching process, and the wafer thickness is compatible with the production line and can be directly connected to the etching equipment.

[0046] Compared with the prior art, the present invention,

[0047] 1. Scientifically optimized thickness parameters achieve a precise balance of multiple technical effects: The parameter combination of 0.7-0.9mm for the upper silicon wafer, 0.3-0.4mm for the lower silicon wafer, and a total thickness of ≤1.2mm has been verified through hundreds of experiments. It precisely matches the four core requirements of embedded installation of wireless sensor circuit boards, wireless signal penetration and transmission, mechanical structural strength of wafers, and size adaptation with actual wafers in semiconductor production lines. The thin design of the lower silicon wafer ensures that the radio frequency signal penetrates without attenuation, the thickness design of the upper silicon wafer takes into account the installation space and mechanical strength, and the total thickness design achieves full compatibility with existing production lines without the need for equipment debugging, solving industry pain points.

[0048] 2. Thickness and shape are highly matched, and the monitoring data is accurate and highly adaptable: Through laser / mechanical precision carving and the selection of ultra-thin components and FPC circuit boards, the design requirement of a total thickness of ≤1.2mm is accurately achieved, which is completely consistent with the actual production wafer thickness. The overall shape matches the production wafer, which can truly reproduce the environment of the wafer in the actual process. This completely solves the problem of data distortion in existing products, greatly improves the authenticity and accuracy of the measurement, and can be directly connected to existing production lines, improving ease of use.

[0049] 3. Multiple anti-interference structures to adapt to complex electromagnetic environments: Combining the electromagnetic shielding of phosphorus-doped silicon wafers (or ion implantation), the electrostatic / radio frequency isolation of polyimide + RF shielding coating insulating film, and the misalignment structure of the upper and lower silicon wafer bonding surfaces and the circuit board, a multiple anti-interference system is constructed from both material and structural aspects. It can effectively resist electromagnetic and electrostatic interference from RF plasma and electrostatic chucks, and can still work normally in the 2MHz-60MHz RF environment, greatly improving circuit stability and monitoring accuracy.

[0050] 4. Specialized etching-resistant coating, extending service life and preventing contamination: A yttrium oxide-based etching-resistant coating is prepared on the surface of the silicon wafer and deposited using PVD / ALD technology. This effectively resists the erosion of etching gases and prevents internal components from being exposed. This not only extends the service life of the wafer but also prevents components from contaminating the process chamber, reducing process maintenance costs.

[0051] 5. Scientific processing technology reduces the risk of breakage and improves reliability: Symmetrical trenching on both the upper and lower silicon wafers avoids stress concentration and reduced mechanical strength caused by deep trenching on a single silicon wafer; high-temperature heat treatment under argon protection after processing effectively eliminates internal stress; the 3D integrated optimized version also adopts gradient transition trenching and multi-step annealing processes to further disperse stress, significantly reducing the risk of breakage during wafer processing and use, and improving product reliability.

[0052] 6. High integration of functional modules and high monitoring efficiency: The circuit board integrates the battery, charging module, wireless communication module, data storage module, main control module and array sensor module to realize real-time acquisition, processing, storage and wireless transmission of multiple physical field parameters. No external equipment is required, and in-situ detection of the entire semiconductor process can be completed, which greatly improves the efficiency and convenience of process monitoring.

[0053] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several modifications and improvements without departing from the inventive concept of the present invention, and these all fall within the protection scope of the present invention.

Claims

1. An embedded wireless sensing test wafer, characterized in that, It includes an upper silicon wafer, a lower silicon wafer, and a circuit board. The upper and lower silicon wafers are clamped on both sides of the circuit board. The surfaces of the upper and lower silicon wafers facing the circuit board are laser-engraved or mechanically precision-engraved to form receiving grooves, and the circuit board is embedded in the receiving grooves. The thickness of the upper silicon wafer is 0.7-0.9mm, the thickness of the lower silicon wafer is 0.3-0.4mm, and the total thickness of the upper and lower silicon wafers clamping the circuit board is ≤1.2mm.

2. The embedded wireless sensing test wafer according to claim 1, characterized in that, The circuit board is a polyimide FPC flexible circuit board, and the electronic components on the circuit board are surface mount type or unpackaged type.

3. The embedded wireless sensing test wafer according to claim 1, characterized in that, The upper and lower silicon wafers are engraved and then subjected to a heat treatment process. The heat treatment process uses a wafer rapid heat treatment equipment and is carried out at a constant temperature of 1000℃ for 30 minutes under argon positive pressure protection.

4. The embedded wireless sensing test wafer according to claim 1, characterized in that, The surface of the upper silicon wafer away from the circuit board is provided with an etch-resistant coating, which is formed by PVD physical vapor deposition. The main component of the etch-resistant coating is yttrium oxide.

5. The embedded wireless sensing test wafer according to claim 1, characterized in that, The upper and lower silicon wafers are phosphorus-doped silicon wafers; or the surfaces of the upper and lower silicon wafers are subjected to ion implantation treatment, with the implanted element being one or both of phosphorus and boron.

6. The embedded wireless sensing test wafer according to claim 1, characterized in that, An insulating film is laid between the upper silicon wafer, the lower silicon wafer, and the circuit board. The main components of the insulating film are polyimide and radio frequency shielding coating.

7. The embedded wireless sensing test wafer according to claim 1, characterized in that, The upper silicon wafer and the lower silicon wafer are bonded and fixed by an adhesive with a thickness of ≤0.05mm, and the bonding surfaces of the upper and lower silicon wafers are not in the same plane as the mounting surface of the circuit board.

8. The embedded wireless sensing test wafer according to claim 1, characterized in that, The circuit board integrates a battery, a charging coil, a charging device, a communication chip, a data storage module, a main control chip, and an array sensor module. The battery is a solid-state or semi-solid-state battery. The charging coil and the charging device are both located at the center of the wafer. The array sensor module is a digital sensor chip or an analog sensor chip with an analog-to-digital conversion circuit.

9. The embedded wireless sensing test wafer according to claim 1, characterized in that: The upper silicon wafer has a thickness of 0.3 mm, the lower silicon wafer has a thickness of 0.15 mm, and the overall thickness is ≤0.5 mm. A 0.05 mm thick polyimide flexible buffer layer is provided between the upper and lower silicon wafers and the circuit board. The receiving groove has a gradient transition structure, gradually deepening from the edge of the wafer to the center. A silicon nitride thin film is deposited on the surface of the silicon wafer, and the upper and lower silicon wafers are bonded by a low-temperature bonding technology below 400°C.

10. The embedded wireless sensing test wafer according to claim 1, characterized in that, The etching-resistant coating is a composite coating of yttrium oxide and hafnium oxide. The wafer has a multi-layer composite shielding structure, consisting of an anti-etching layer, a titanium alloy micron-scale mesh layer, an aluminum nitride dielectric layer, and a copper-aluminum alloy thin film layer from the outside to the inside. The silicon wafer surface has a nano-scale graphene layer. The gap between the circuit board and the receiving groove is filled with a polymer material with a high dielectric constant. The circuit board integrates a digital signal processing chip, equipped with an adaptive interference cancellation algorithm and a machine learning interference model.

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