Low-loss IGBT (Insulated Gate Bipolar Translator) chip with compensation type floating P region and preparation method of low-loss IGBT chip

By introducing a compensated floating P-region structure and an N-CS layer into the IGBT chip, the electric field distribution is optimized, solving the problem of balancing high voltage withstand, low loss, and process feasibility in IGBT chips, and achieving the effects of high voltage withstand, low loss, and simplified process.

CN121968613APending Publication Date: 2026-05-01ZHEJIANG XINMENG SEMICON TECH CO LTD +1
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Patent Information

Application Number
CN202610127869.5
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-01-29
Publication Date
2026-05-01

AI Technical Summary

Technical Problem

Existing IGBT chips struggle to balance high voltage withstand capability, low loss, and process feasibility, resulting in low blocking voltage, high switching losses, and complex manufacturing processes.

Method used

A compensated floating P-region structure is adopted. The cell structure includes an emitter structure, a drift region structure, a trench gate structure, and a collector structure. An N-CS layer is embedded inside the floating P-region to form a three-layer structure. The electric field distribution under the conduction and blocking states is optimized by decreasing doping concentration and positional symmetry design.

Benefits of technology

It effectively reduces on-state voltage drop and switching losses, improves device blocking voltage and switching speed, simplifies manufacturing processes, and achieves a balance between high withstand voltage and low loss.

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Abstract

The invention belongs to the field of power semiconductor devices, and particularly discloses a low-loss IGBT chip with a compensation type floating P region and a preparation method of the low-loss IGBT chip. According to the invention, the N-CS layer is formed in the floating P region, the N-CS layer forms a hole barrier when the device is conducted, the hole concentration of the emitter side is increased by the floating P region, electron injection of the emitter side is enhanced in order to maintain electric neutrality, and the on-state voltage drop can be effectively reduced. In the switching process, the N-CS layer and the floating P region are mutually depleted, the expansion time of a depletion layer is shortened, and the switching time of the device is shortened. The switching loss can be reduced while the low on-state voltage drop of the device is maintained, and the on-state voltage drop and the switching loss are effectively balanced. An N-type layer is introduced into a floating P region, and the original maximum electric field is reduced due to positive charges provided by N-CS, so that the reduction of the electric flux of the traditional floating P region, the reduction of a concentrated high electric field near a groove, the protection of a gate oxide layer at the bottom of the groove and the improvement of the blocking voltage of the device are facilitated.
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