Double-spin torque tunnel junction device and preparation method thereof

Abstract

The invention provides a double-spin torque tunnel junction device and a preparation method thereof. The device comprises a double-spin torque tunnel junction. The double-spin torque tunnel junction sequentially comprises a bottom reference layer, a barrier layer, a free layer, a metal isolation layer and a top reference layer from bottom to top. The bottom reference layer, the barrier layer and the free layer form a tunneling structure; the free layer, the metal isolation layer and the top reference layer form a spin valve structure. According to the device, weak antiferromagnetic RKKY interaction is formed between the free layer and the top reference layer through the metal isolation layer, and the free layer and the top reference layer are reasonably designed, so that critical write-in currents of the free layer and the top reference layer meet specific conditions, and the device can be adaptively evolved into a magnetic structure with the minimum read error rate in the data write-in process; compared with a conventional external means, initialization configuration is independently carried out on the top reference layer before reading and writing operation, the complexity of an external circuit can be greatly reduced, and the power consumption of a complete operation period is reduced.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a dual-spin-torque tunnel junction device and its fabrication method. Background Technology

[0002] With the advent of the digital and intelligent era, strategic emerging technologies such as artificial intelligence, the Internet of Things, and autonomous driving are developing rapidly. Computing and storage have become two core issues in the development of micro-nano electronics technology. As Moore's Law gradually becomes obsolete, "storage-based computing" and "storage-based replacement of computing" have emerged as disruptive technologies that promise to overcome the bottlenecks in computing power and the limitations of storage. Embedded non-volatile memory (eNVM) technology is an indispensable part of modern electronic devices, providing powerful data storage and management capabilities for various application scenarios. With the development of emerging eNVM technologies, it will play a crucial role in the future trend of intelligent and networked development. Traditional CMOS-eNVM (eFlash) below 28nm is no longer sustainable due to cost, performance, and process compatibility issues, leading to the emergence of new eNVM technologies such as eMRAM, eRRAM, and ePCM. Compared to other emerging eNVMs, eMRAM combines high speed, high reliability, and sustainable shrinkage, making it the preferred solution to replace eFlash and a priority embedded IP for major foundries. Currently, TSMC, Samsung, and Global Foundries have achieved mature mass production of eMRAM at the 22 / 28nm node, and 16nm node eMRAM has entered customer verification. Among them, TSMC has launched its first design company in Europe and is conducting research on 5nm eMRAM technology.

[0003] One of the key challenges of eMRAM technology is the impedance matching design between magnetic tunnel junction devices and transistor devices. eMRAM memory cells consist of transistors and tunnel junctions connected in series. With continuous advancements in process nodes, the operating voltage and saturation current of transistors gradually decrease, weakening their load-carrying capacity. Designing and manufacturing tunnel junction devices compatible with advanced logic processes is a crucial issue that urgently needs to be addressed. Reducing the write current (energy consumption) of the tunnel junction device without altering its thermal stability and resistance (RA) is the ultimate goal of eMRAM. Miniaturizing the tunnel junction device to reduce the write current was an early mainstream approach. However, as the device size decreases, its thermal stability coefficient decreases. Further attempts to compensate for this thermal stability degradation include increasing the number of CoFeB / MgO interfaces in the tunnel junction device; however, this increases the RA of the device. This trade-off cannot be eliminated through traditional methods.

[0004] In 2017, IBM pioneered the concept of a "dual spin-torque tunnel junction," inserting an additional reference layer on top of the free layer. When the magnetic moments of the top and bottom reference layers are antiparallel, the spin transfer torque effect of both layers can theoretically reduce the critical write current of the device by a factor of 10. However, a core problem with this structure is that when reading the resistance of the tunnel junction device, the read current path is the same as the write current path. Since the write current is very small, there is a high probability of false writes during the readout process. This can only be avoided by strictly controlling the amplitude of the read current, which is not conducive to chip integration because it is difficult to achieve high-precision low-current generation within a chip.

[0005] As mentioned above, when the magnetic moments of the top and bottom reference layers of a dual spin-orbit tunnel junction are antiparallel, the critical current of the device decreases due to the enhanced spin-orbit torque effect. Conversely, when the magnetic moments of the top and bottom reference layers are parallel, the critical current increases due to the cancellation of the spin-orbit torque effect, thus increasing the readout window. Therefore, the internationally proposed solution is to introduce other external stimuli (such as magnetic field effects, spin-orbit torque effects, or voltage modulation effects) to independently control the magnetic moment direction of the top reference layer. When data writing is required, the top reference layer is initialized to an antiparallel state; when data reading is required, the top reference layer is initialized to a parallel state. This method is also not suitable for chip integration because it adds extra initialization operations, resulting in additional energy overhead and circuit design complexity.

[0006] In view of this, the present invention is proposed. Summary of the Invention

[0007] The purpose of this invention is to provide a dual spin torque tunnel junction device with reduced bit error rate and its fabrication method, which utilizes the adaptive characteristics during data writing to keep the device in the optimal magnetic structure state for different operations.

[0008] In a first aspect, the present invention provides a dual-spin-moment tunnel junction device, comprising a dual-spin-moment tunnel junction; The dual-spin moment tunnel junction comprises, from bottom to top: a bottom reference layer, a barrier layer, a free layer, a metal isolation layer, and a top reference layer; The bottom reference layer, barrier layer, and free layer constitute the tunneling structure; The free layer, the metal isolation layer, and the top reference layer constitute the spin valve structure.

[0009] Preferably, in the tunneling structure, when the magnetic moment directions of the bottom reference layer and the free layer are parallel, the device exhibits low resistance Rp, and vice versa. In a spin valve structure, when the magnetic moments of the free layer and the top reference layer are parallel, the device exhibits low resistance Rp1, and vice versa. The magnetic reluctance of the tunnel structure is much greater than that of the spin valve structure, and the resistance of the device can be approximated as having only two resistance states: Rp and Rap.

[0010] Preferably, the device meets the following conditions: I AP c,FL < I c , DRL < I P c,FL < c,RL ; Among them, I AP c,FL The critical write current when the magnetic moments of the top and bottom reference layers are antiparallel in the free layer; I P c,FL The critical write current for the free layer when the magnetic moments of the top and bottom reference layers are parallel; I c , DRL This is the critical write current for the top reference layer; I c,RL This is the critical write current for the bottom reference layer.

[0011] Preferably, an antiferromagnetic RKKY interaction is generated between the free layer and the top reference layer through a metal isolation layer.

[0012] Preferably, the free layer and the bottom reference layer are made of CoFeB material; The barrier layer material is MgO; The metal isolation layer is made of a heavy metal material with an outermost electron unsaturated layer; The top reference layer is made of a magnetic material with vertical magnetic anisotropy.

[0013] Preferably, the outermost electron-unsaturated heavy metal material is selected from any one of W, Ta, Ru, and Ir.

[0014] Preferably, the magnetic material with perpendicular magnetic anisotropy is selected from CoFeB / MgO and [Co / Pt]. n [Co / Pt] n / Ru / [Co / Pt] m Any one of them.

[0015] Preferably, the bottom reference layer further includes a pinning layer, the pinning layer being made of [Co / Pt] material.​m / Ru / [Co / Pt] n / W.

[0016] A second aspect of the present invention provides a method for fabricating a dual-spin-moment tunnel junction device, comprising the following steps: S1. Using a magnetron sputtering system, a bottom electrode layer, a bottom reference layer, a barrier layer, a free layer, a metal isolation layer, a top reference layer, and a capping protective layer are sequentially deposited on the substrate. S2. Using a deep ultraviolet exposure system, a photoresist pattern for forming a tunnel junction is formed by exposure. S3. Using an ion beam etching system, etching is performed according to the photoresist pattern. The etching stops at the bottom electrode layer, realizing pattern transfer and obtaining a tunnel junction.

[0017] Preferably, the following steps are also included: S4. Utilize the PECVD system to deposit a passivation layer to protect the tunnel junction; S5. Using a deep ultraviolet exposure system, the photoresist pattern of the bottom electrode is formed by exposure. S6. Using an ion beam etching system, etching is performed according to the photoresist pattern. The etching stops at the substrate to achieve pattern transfer and obtain the bottom electrode. S7. Deposit a media isolation layer using a PECVD system; S8. Using a CMP system, polish the surface to expose the protective cap layer; S9. Using a deep ultraviolet exposure system, the photoresist pattern of the bottom electrode contact hole is formed by exposure. S10. Using an ion beam etching system, etching is performed according to the photoresist pattern. The etching stops at the bottom electrode to achieve pattern transfer and obtain the bottom electrode contact hole. S11. Using a PVD system, deposit metal to fill interconnect base holes; S12. Using a deep ultraviolet exposure system and an ion beam etching system, after exposure and etching, the test electrode is obtained.

[0018] The present invention has at least the following beneficial effects: (1) The dual spin torque tunnel junction device of the present invention forms a weak antiferromagnetic RKKY interaction between the free layer and the top reference layer through a metal isolation layer, and rationally designs the free layer and the top reference layer so that the critical write current of both meets specific conditions, so that the device can adaptively evolve into a magnetic structure with the lowest read error rate during the data writing process. Compared with the conventional method of independently initializing the top reference layer before the read and write operations through external means, the complexity of the external circuit can be greatly reduced and the power consumption of the complete operation cycle can be reduced.

[0019] (2) Compared with conventional methods that rely on external means, the present invention independently initializes and configures the top reference layer before reading and writing operations, which can greatly reduce the complexity of external circuits and reduce the power consumption of the entire operation cycle. Attached Figure Description

[0020] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the structure of the double spin moment tunnel junction provided by the present invention.

[0022] Figure 2 This is a schematic diagram illustrating the principle of the formation of a stable state in a dual-spin moment tunnel junction provided by the present invention.

[0023] Figure 3 This invention provides a schematic diagram illustrating the principle of applying a top-down motion to a dual-spin-moment tunnel junction to change the electronic state.

[0024] Figure 4 This invention provides a schematic diagram illustrating the principle of applying an upward-moving electron state change to a dual-spin-moment tunnel junction.

[0025] Figure 5 This is a schematic diagram of a double spin moment tunnel junction with a top reference layer of CoFeB / MgO stack, as provided in this invention.

[0026] Figure 6 The top reference layer provided for this invention is [Co / Pt]. n A schematic diagram of a double-spin-moment tunnel junction in a stacked configuration.

[0027] Figure 7 The top reference layer provided for this invention is [Co / Pt]. n / Ru / [Co / Pt] m A schematic diagram of the structure of a double-spin moment tunnel junction.

[0028] Figure 8 This is a schematic diagram of the structure after step S1 of the present invention, in which a bottom electrode layer, a bottom reference layer, a barrier layer, a free layer, a metal isolation layer, a top reference layer and a capping protective layer are sequentially deposited on a silicon substrate.

[0029] Figure 9 This is a schematic diagram of the structure after the photoresist pattern for the tunnel junction is formed in step S2 of the present invention.

[0030] Figure 10 Step S3 of the present invention involves etching the photoresist pattern to achieve pattern transfer, resulting in a schematic diagram of the structure after the tunnel junction is obtained.

[0031] Figure 11 This is a schematic diagram of the structure after the passivation layer is deposited in step S4 of the present invention.

[0032] Figure 12 This is a schematic diagram of the structure after the photoresist pattern of the bottom electrode is formed by exposure in step S5 of the present invention.

[0033] Figure 13 The schematic diagram of the structure after obtaining the bottom electrode is provided in step S6 of the present invention, which involves etching according to the photoresist pattern to achieve pattern transfer.

[0034] Figure 14 This is a schematic diagram of the structure after the deposition of the medium isolation layer in step S7 of the present invention.

[0035] Figure 15 This is a schematic diagram of the structure after the protective cap layer is exposed on the polished surface in step S8 of the present invention.

[0036] Figure 16 This is a schematic diagram of the structure after the photoresist pattern for the bottom electrode contact hole is exposed in step S9 of the present invention.

[0037] Figure 17 The schematic diagram of the structure after obtaining the bottom electrode contact hole is provided in step S10 of the present invention, which involves etching according to the photoresist pattern to achieve pattern transfer.

[0038] Figure 18 This is a schematic diagram of the structure after metal deposition and filling of interconnect base holes in step S11 of the present invention.

[0039] Figure 19 This is a schematic diagram of the structure of the device after exposure and etching in step S12 of the present invention, resulting in the device test electrode.

[0040] Explanation of reference numerals in the attached figures: 1. Substrate; 2. Bottom electrode layer; 3. Bottom reference layer; 4. Barrier layer; 5. Free layer; 6. Metal isolation layer; 7. Top reference layer; 8. Cap protective layer; 9. Photoresist pattern of tunnel junction; 10. Passivation layer; 11. Photoresist pattern of bottom electrode; 12. Dielectric isolation layer; 13. Photoresist pattern of bottom electrode contact hole; 14. Bottom electrode contact hole; 15. Interconnect base hole; 16. Test electrode. Detailed Implementation

[0041] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0042] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form includes the plural form unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0043] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] Example This embodiment provides a dual-spin-torque tunnel junction device, including a dual-spin-torque tunnel junction; the dual-spin-torque tunnel junction, from bottom to top, includes: a bottom reference layer 3, a barrier layer 4, a free layer 5, a metal isolation layer 6, and a top reference layer 7; the bottom reference layer 3, barrier layer 4, and free layer 5 constitute a tunneling structure; the free layer 5, metal isolation layer 6, and top reference layer 7 constitute a spin valve structure, such as... Figure 1 As shown.

[0045] In the tunneling structure, when the magnetic moments of the bottom reference layer 3 and the free layer 5 are parallel, the device exhibits low resistance Rp, and vice versa. In the spin valve structure, when the magnetic moments of the free layer 5 and the top reference layer 7 are parallel, the device exhibits low resistance Rp1, and vice versa. The magnetic reluctance of the tunneling structure is much greater than that of the spin valve structure, and the resistance of the device can be approximated as having only two resistance states: Rp and Rap.

[0046] In this embodiment, the device satisfies the following two conditions: Condition 1: I AP c,FL < I c , DRL < I P c,FL < c,RL ; Among them, I AP c,FL The critical write current for free layer 5 when the magnetic moments of the top reference layer 7 and the bottom reference layer 3 are antiparallel;​ I P c,FL The critical write current for free layer 5 when the magnetic moments of the top reference layer 7 and the bottom reference layer 3 are parallel; I c , DRL The critical write current for the top reference layer 7; I c,RL This is the critical write current for the bottom reference layer 3.

[0047] Condition 2: The RKKY interaction between the free layer 5 and the top reference layer 7, generated by the metal isolation layer 6, forms a weak antiferromagnetic coupling.

[0048] In this embodiment, the free layer 5 and the bottom reference layer 3 are selected as CoFeB (the pinning layer at the bottom of the bottom reference layer 3 is ignored here; the complete structure of the bottom reference layer 3 is generally [Co / Pt]). m / Ru / [Co / Pt] n / W / CoFeB (for simplicity, the bottom reference layer 3 is denoted as CoFeB), with a thickness between 0.8nm and 1.5nm, ensuring that it has perpendicular magnetic anisotropy.

[0049] In this embodiment, the barrier layer 4 is selected as MgO, with a thickness of 0.8nm~1.2nm, to ensure that the device has a sufficiently large tunneling magnetoresistance ratio [TMR=(Rap-Rp) / Rp], while having a small resistance area product (RA).

[0050] In this embodiment, the metal isolation layer 6 is made of an outermost electron-unsaturated heavy metal material, such as W, Ta, Ru, Ir, etc., and its thickness varies depending on the material selected. Taking metal W as an example, its thickness is generally 1.0 nm to 1.8 nm. Factors to consider include the requirement for an antiferromagnetic RKKY interaction between the free layer 5 and the top reference layer 7. The strength of this interaction exhibits a Bessel function oscillation trend with the thickness of the metal layer, necessitating the selection of a thickness range with weaker antiferromagnetic interaction. Secondly, the spin diffusion length of the heavy metal material also needs to be considered. If the metal thickness is too large, exceeding the intrinsic spin diffusion length of the material, the double spin torque effect will disappear, thus failing to achieve the characteristics of a double spin torque tunnel junction application.

[0051] In this embodiment, the top reference layer 7 is selected from magnetic materials with perpendicular magnetic anisotropy, such as CoFeB / MgO stacks or [Co / Pt]. n Stacked, [Co / Pt] n / Ru / [Co / Pt] m Artificial antiferromagnetic layers, such as Figure 5-7 As shown. By optimizing parameters such as the thickness of the magnetic layer and the number of layers in the stack, I is adjusted.c,DRL .

[0052] The working principle of the dual-spin-moment tunnel junction device in this embodiment is as follows: The first step is initialization. A strong external magnetic field is applied to the device, magnetizing the magnetic moments of the top reference layer, free layer, and bottom reference layer all in the same direction. Then the external magnetic field is removed. At this point, the magnetic moments of the bottom reference layer and free layer are parallel, while those of the top reference layer and free layer are antiparallel (due to condition 2), forming a configuration as shown below. Figure 2 The stable state shown.

[0053] After initialization, current is applied to the device (here, current is represented by the movement of electrons; note that the direction of current is opposite to the direction of electron movement). For example... Figure 3 As shown in Figure A, electrons moving from top to bottom are introduced. According to condition 1, when the writing current I... w > I AP c,FL At that time, the magnetic moment of the free layer first reverses, becoming Figure 3 As shown in B in the diagram. If the current is maintained or the current intensity is increased, according to conditions 1 and 2, the magnetic moment of the top reference layer will reverse, evolving into... Figure 3 The state shown in C indicates that when the current is removed, the device can stabilize in this state, as shown in Figure C. Figure 3 As shown in D in the diagram. Note that, Figure 3 The initial state shown in Figure A has a device resistance of Rp. Figure 3 As shown in D, in stable state a, the device resistance is Rap, at which point the write operation from low resistance to high resistance is completed. More importantly, in stable state a, the magnetic moments of the top and bottom reference layers are parallel, and the critical flip current of the free layer is at its maximum. In this state, the read current margin of the device is extremely large.

[0054] Based on the stable state a, electrons moving from bottom to top are applied to the device, such as... Figure 4 As shown in A, according to conditions 1 and 2, when the write current Iw > I c,DRL At that time, the magnetic moment direction of the top reference layer will flip first, evolving into Figure 4 As shown in B. In this state, the free layer will flip, evolving into Figure 4 C represents the steady state b. When the current is removed, the device state remains unchanged, as shown in the example. Figure 4 As shown in D in the diagram. Note that, Figure 4 D and Figure 3 The A state is the same, meaning the write cycle from Rp to Rap to Rp is complete. On the other hand, for the stable state b, during the read operation, if the electrons move from top to bottom, there is a high probability of incorrect writing (Iread < ...). AP ​c,FL However, if the electrons move from bottom to top, the device state will not change. That is, the stability of steady state b depends on the direction of electron movement, while the stability of steady state a is minimally affected by the direction of electron movement. Therefore, during the read process, the direction of the read current is set from top to bottom, and Iread < 0. c,DRL Therefore, the data can be safely read out. As can be seen from condition 1, the readout window can be significantly improved compared to conventional dual-spin-moment devices using the solution proposed in this invention.

[0055] The key to improving the readout window in this invention lies in Iread< c,DRL According to condition 1, I c,DRL in I AP c,FL and I P c,FL Between, therefore as long as I AP c,FL and I P c,FL The difference is large enough, I c,DRL There is enough design window to meet the requirements of low write power consumption and low read error rate.

[0056] The fabrication method of the dual-spin-moment tunnel junction device is described in detail below with reference to the accompanying drawings. To illustrate this scheme more clearly, the process flow diagram only shows the layer layout relevant to the patent. The dimensions in the diagram (including lateral dimensions, layout dimensions, dielectric thickness, metal thickness, junction depth, etc.) do not represent actual dimensions, but are only used to illustrate the patent concept.

[0057] This embodiment provides a method for fabricating a dual-spin-moment tunnel junction device, comprising the following steps: S1. Using a magnetron sputtering system, sequentially deposit the following layers on a silicon substrate: a bottom electrode layer (typically 20nm Ru or Ta), a bottom reference layer 3 (RL), a barrier layer 4, a free layer 5 (FL), a metal isolation layer 6 (Spacer), a top reference layer 7 (DRL), and a capping protective layer 8 (Cap). Figure 8 As shown; S2. Using a deep ultraviolet exposure system, a photoresist pattern 9 is formed by exposure to create a tunnel junction, such as... Figure 9 As shown; S3. Using an ion beam etching system (IBE / RIE), etching is performed according to the photoresist pattern. The etching stops at the bottom electrode layer, achieving pattern transfer and obtaining a tunnel junction. Figure 10 As shown; S4. Using a PECVD system, a passivation layer of 10 (SiN) is deposited to protect the tunnel junction, such as... Figure 11 As shown; ​​S5. Using a deep ultraviolet exposure system, the photoresist pattern 11 of the bottom electrode is formed by exposure, such as... Figure 12 As shown; S6. Using an ion beam etching system, etching is performed according to the photoresist pattern. Etching stops at the substrate, achieving pattern transfer and obtaining the bottom electrode (BE). Figure 13 As shown; S7. Using a PECVD system, deposit dielectric isolation layer 12 (SiO2) as dielectric isolation between devices, such as... Figure 14 As shown; S8. Using a CMP system, polish the surface to expose the protective cap layer 8, such as... Figure 15 As shown; S9. Using a deep ultraviolet exposure system, the photoresist pattern 13 of the bottom electrode contact hole 14 is formed by exposure, such as... Figure 16 As shown; S10. Using an ion beam etching system, etching is performed according to the photoresist pattern. The etching stops at the bottom electrode, achieving pattern transfer and obtaining the bottom electrode contact hole 14. Figure 17 As shown; S11. Using a PVD system, deposit metal to fill the interconnect base holes 15, such as... Figure 18 As shown; S12. Using a deep ultraviolet exposure system and an ion beam etching system, after exposure and etching, the device test electrode 16 is obtained, such as... Figure 19 As shown.

[0058] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0059] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A dual-spin-moment tunnel junction device, characterized in that, Including double-spin-moment tunnel junctions; The dual-spin moment tunnel junction comprises, from bottom to top: a bottom reference layer, a barrier layer, a free layer, a metal isolation layer, and a top reference layer; The bottom reference layer, barrier layer, and free layer constitute the tunneling structure; The free layer, the metal isolation layer, and the top reference layer constitute the spin valve structure.

2. The dual-spin-moment tunnel junction device according to claim 1, characterized in that, In a tunneling structure, when the magnetic moments of the bottom reference layer and the free layer are parallel, the device exhibits low resistance Rp, and vice versa. In a spin valve structure, when the magnetic moments of the free layer and the top reference layer are parallel, the device exhibits low resistance Rp1, and vice versa. The magnetic reluctance of the tunnel structure is much greater than that of the spin valve structure, and the resistance of the device can be approximated as having only two resistance states: Rp and Rap.

3. The dual-spin-moment tunnel junction device according to claim 1, characterized in that, The device meets the following conditions: I AP c,FL < I c , DRL < I P c,FL << I c,RL ; Among them, I AP c,FL The critical write current when the magnetic moments of the top and bottom reference layers are antiparallel in the free layer; I P c,FL The critical write current for the free layer when the magnetic moments of the top and bottom reference layers are parallel; I c , DRL This is the critical write current for the top reference layer; I c,RL This is the critical write current for the bottom reference layer.

4. The dual-spin-moment tunnel junction device according to claim 1, characterized in that, An antiferromagnetic RKKY interaction is generated between the free layer and the top reference layer through a metal isolation layer.

5. The dual-spin-moment tunnel junction device according to claim 1, characterized in that, The free layer and the bottom reference layer are made of CoFeB. The barrier layer material is MgO; The metal isolation layer is made of a heavy metal material with an outermost electron unsaturated layer; The top reference layer is made of a magnetic material with vertical magnetic anisotropy.

6. The dual-spin-moment tunnel junction device according to claim 5, characterized in that, The outermost electron-unsaturated heavy metal material is selected from any one of W, Ta, Ru, and Ir.

7. The dual-spin moment tunnel junction device according to claim 5, characterized in that, The magnetic material with perpendicular magnetic anisotropy is selected from CoFeB / MgO and [Co / Pt]. n [Co / Pt] n / Ru / [Co / Pt] m Any one of them.

8. The dual-spin moment tunnel junction device according to claim 1, characterized in that, The bottom reference layer also includes a pinning layer, the pinning layer being made of [Co / Pt] material. m / Ru / [Co / Pt] n / W.

9. A method for fabricating a dual-spin-torque tunnel junction device, characterized in that, Includes the following steps: S1. Using a magnetron sputtering system, a bottom electrode layer, a bottom reference layer, a barrier layer, a free layer, a metal isolation layer, a top reference layer, and a capping protective layer are sequentially deposited on the substrate. S2. Using a deep ultraviolet exposure system, a photoresist pattern for forming a tunnel junction is formed by exposure. S3. Using an ion beam etching system, etching is performed according to the photoresist pattern. The etching stops at the bottom electrode layer, realizing pattern transfer and obtaining a tunnel junction.

10. The method for fabricating a dual-spin-moment tunnel junction device according to claim 9, characterized in that, It also includes the following steps: S4. Utilize the PECVD system to deposit a passivation layer to protect the tunnel junction; S5. Using a deep ultraviolet exposure system, the photoresist pattern of the bottom electrode is formed by exposure. S6. Using an ion beam etching system, etching is performed according to the photoresist pattern. The etching stops at the substrate to achieve pattern transfer and obtain the bottom electrode. S7. Deposit a media isolation layer using a PECVD system; S8. Using a CMP system, polish the surface to expose the protective cap layer; S9. Using a deep ultraviolet exposure system, the photoresist pattern of the bottom electrode contact hole is formed by exposure. S10. Using an ion beam etching system, etching is performed according to the photoresist pattern. The etching stops at the bottom electrode to achieve pattern transfer and obtain the bottom electrode contact hole. S11. Using a PVD system, deposit metal to fill interconnect base holes; S12. Using a deep ultraviolet exposure system and an ion beam etching system, after exposure and etching, the test electrode is obtained.

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