A distributed video stitching device
Through the integrated design of the distributed video splicing device, the problems of complex architecture and remote network streaming media processing in traditional video splicing systems have been solved, achieving low-cost, highly scalable, and low-latency multi-channel signal display.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- ZHONGLI INTELLIGENT TECH (SHENZHEN) CO LTD
- Filing Date
- 2025-05-14
- Publication Date
- 2026-06-02
Smart Images
Figure CN224319402U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of video splicing technology, specifically to a distributed video splicing device. Background Technology
[0002] In today's information society, multi-screen splicing technology has become an indispensable and important component in fields such as conference rooms, lecture halls, auditorium stages, and video surveillance. This technology achieves high-resolution and large-size display effects by dividing a complete image signal into multiple parts and distributing them to a corresponding number of video displays (i.e., splicing walls).
[0003] In traditional video splicing systems, the control unit typically lacks an integrated design. Multiple video inputs usually rely on independent decoders and splicing processors, resulting in a complex system architecture, high cost, and limited scalability. Furthermore, in existing technologies, most splicing controllers only support local HDMI or SDI inputs, failing to efficiently process remote network streaming media (such as RTSP and RTMP), requiring the deployment of additional streaming media servers or decoding equipment, thus increasing system latency and integration complexity. Therefore, a device is needed that enables remote streaming media data processing based on an integrated design. This invention addresses this technical problem. Utility Model Content
[0004] The purpose of this application is to provide a distributed video splicing device that aims to solve the technical problems of achieving integrated design and processing network streaming media data.
[0005] To achieve the above objectives, this application proposes a distributed video stitching device, which includes:
[0006] The system includes several local input modules connected to an external image device, a management module connected to the several local input modules, several output modules connected to the management module, and a network streaming media input module connected to the management module. The output modules are connected to an external display device.
[0007] Furthermore, the local input module includes an input interface connected to the external image device, an input conversion chip electrically connected to the input interface, and an input FPGA electrically connected to the input conversion chip. The input FPGA is electrically connected to the management module, and the input conversion chip is used to output RGB signals to the input FPGA.
[0008] Furthermore, the input FPGA is electrically connected to the management module via a high-speed serial differential interface.
[0009] Furthermore, the output module includes an output FPGA electrically connected to the management module, an output conversion chip electrically connected to the output FPGA, and an output interface electrically connected to the output conversion chip. The output interface is connected to the external display device, and the output conversion chip is used to convert the received YUV signal and output it to the output interface.
[0010] Furthermore, the output FPGA is electrically connected to the management module via a high-speed serial differential interface.
[0011] Furthermore, the management module includes a management FPGA electrically connected to the local input module and the output module, a control card electrically connected to the management FPGA, a memory and a CPU electrically connected to the control card, and the control card is electrically connected to the network streaming media input module.
[0012] Furthermore, the network streaming media input module adopts an RJ45 network interface.
[0013] The technical solution proposed in this application has at least the following technical effects:
[0014] (1) Several local input modules in this solution can convert the image signals of external image devices and transmit them to the management module, and the network streaming media input module can transmit the network streaming media data to the management module. The management module will mix the acquired data and distribute it to several output modules. The images output by several output modules will be displayed on external display devices to achieve video splicing.
[0015] (2) Through integrated design, this solution can simultaneously support local image devices and remote network media stream data. It also integrates several local input and output modules, and can control multiple modules through a single control card. Compared with the traditional method, this solution reduces the number of hardware, lowers complexity and cost, and improves practicality.
[0016] (3) The management module in this solution can connect to multiple local input modules and output modules. Users can add more local input modules and output modules according to actual needs, so that the device has good scalability. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.
[0018] Figure 1 This is a connection diagram of the present invention.
[0019] Figure 2 This is a schematic diagram of the integrated circuit framework in this utility model.
[0020] Figure 3 This is a circuit diagram of the input interface in this utility model.
[0021] Figure 4 This is a schematic diagram of the image editing and splicing process in this utility model.
[0022] Figure 5 This is a schematic diagram of the control card controlling the image signal in this utility model.
[0023] Figure 6 This is a schematic diagram of the clock frequency supply for the clock management subsystem in this utility model.
[0024] Figure 7 This is a schematic diagram of the front panel of the chassis in this utility model.
[0025] Figure 8 This is a schematic diagram of the rear panel of the chassis in this utility model.
[0026] Figure 9 This is a schematic diagram of the left side panel of the chassis in this utility model.
[0027] Figure 10 This is a schematic diagram of the right side panel of the chassis in this utility model.
[0028] The reference numerals in the attached diagram are as follows: 1. Input interface; 2. Input conversion chip; 3. Input FPGA; 4. Control card; 5. Management FPGA; 6. Memory; 7. CPU; 8. RJ45 network interface; 9. Output FPGA; 10. Output conversion chip; 11. Output interface.
[0029] The realization of the purpose, functional features and advantages of this utility model will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0030] The technical solution of this utility model will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this utility model, and not all of them. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.
[0031] It should be noted that if the embodiments of this utility model involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.
[0032] Furthermore, if the embodiments of this utility model involve descriptions of "input," "output," etc., such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "input" or "output" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this utility model.
[0033] See Figures 1-6 A distributed video splicing device includes several local input modules connected to an external image device, a management module connected to the several local input modules, several output modules connected to the management module, a network streaming media input module connected to the management module, and the output modules connected to an external display device.
[0034] Furthermore, the local input module includes an input interface 1 connected to an external image device, an input conversion chip 2 electrically connected to the input interface 1, and an input FPGA 3 electrically connected to the input conversion chip 2. The input FPGA is electrically connected to the management module, and the input conversion chip 2 is used to output RGB signals to the input FPGA 3.
[0035] In this embodiment, four local input modules are provided, and each local input module is provided with four input interfaces 1, namely HDMI input interfaces 1. Each HDMI input interface 1 corresponds to an HDMI input conversion chip 2. The input conversion chip 2 converts the received signal into an RGB signal. The input FPGA 3 is electrically connected to the four input conversion chips 2 and is used to encode and package the received RGB signal into image data.
[0036] Each input signal is decomposed into a 24-bit RGB-TTL signal (8 bits each for red, green, and blue) by the HDMI input conversion chip 2. FPGA (Field-Programmable Gate Array) is a hardware reconfigurable architecture. FPGA is a further development based on programmable devices such as PAL (Programmable Array Logic) and GAL (General Purpose Array Logic).
[0037] Furthermore, the input FPGA3 is electrically connected to the management module via a high-speed serial differential interface (SERDES).
[0038] Preferably, the high-speed serial differential interface (SERDES) in this embodiment can be connected to a data routing controller. The data routing controller in this embodiment includes a multi-level instruction distribution channel and a data stream arbitration module. The multi-level instruction distribution channel is used to transmit video processing commands, and the data stream arbitration module is used to coordinate memory access conflicts between network streams and local HDMI streams. The above content belongs to the prior art known to those skilled in the art, and will not be described in detail here.
[0039] Furthermore, the output module includes an output FPGA9 electrically connected to the management module, an output conversion chip 10 electrically connected to the output FPGA9, and an output interface 11 electrically connected to the output conversion chip 10. The output interface 11 is connected to an external display device. The output conversion chip 10 is used to convert the received YUV signal and output it to the output interface 11.
[0040] Furthermore, the output FPGA9 is electrically connected to the management module via a high-speed serial differential interface.
[0041] Furthermore, the management module includes a management FPGA 5 electrically connected to the local input module and output module, a control card 4 electrically connected to the management FPGA 5, a memory 6 electrically connected to the control card 4, and a CPU 7. The control card 4 is electrically connected to the network streaming media input module. In this embodiment, the memory 6 is DDR4 memory.
[0042] The control card 4 in this embodiment includes: a video decoding engine (HiSilicon chip), used for hardware decoding of network streaming media such as RTSP / RTMP / TS and generating layout instructions such as windowing / overlay / roaming / scaling / stretching and sending them to the corresponding FPGA; a memory mapping manager, which writes the decoded data to the specified memory area of the target FPGA through direct storage access; and DDR4 memory for image pre-storage.
[0043] See Figure 5In this embodiment, CPU7 uses the HI3536, which is the main control chip of control card 4. It is used to issue commands. FPGA5 is used to receive pre-processed image data from each input FPGA3 and synchronously receive network streaming media data transmitted through control card 4. All input data is stored uniformly in the DDR4 memory on control card 4. Then, management FPGA5 reads data from memory according to the routing table issued by control card 4 and dynamically allocates the read image data and network streaming media data to each output FPGA9. Control card 4 in this embodiment is configured with a routing policy register for issuing screen control commands, monitoring the output timing synchronization of each output FPGA9, and dynamically adjusting data stream priorities (e.g., network streams prioritize local HDMI streams). The 8MHz passive crystal oscillator in the figure is the system clock required for the HI3536 chip to run the Linux system.
[0044] In this embodiment, each input FPGA3 can receive 4 channels of RGB-TTL signals, package 1-16 channels of image signal data through a high-speed SERDES bus, and transmit the network streaming media data, which is decoded and cached by the HiSilicon chip, to the management FPGA5. The management FPGA5 stores all data in DDR4 memory, so the DDR4 memory of the management FPGA5 contains all HDMI input image signals and network streaming media signals from ports 1-16. The CPU7 of the control card 4 sends screen layout instructions and mixing parameters to each output FPGA9 through the bus. At the same time, the HI3536 configures the underlying hardware parameters of the output FPGA9 and the HDMI conversion chip registers through the IIC bus. The fifth FPGA selects the specified signal source from memory and performs dynamic splicing processing according to the received control instructions, and finally distributes the mixed video data to each output FPGA9. Each output FPGA9 outputs the YUV signal to the display device through the HDMI conversion chip according to the parameters configured by the HI3536, realizing the synchronous display of multi-source signals.
[0045] See Figure 6 In this embodiment, the control card 4 also includes a clock management subsystem, namely a clock management unit. The clock management subsystem is connected to each output FPGA9 and the DDR4 memory of each output FPGA9 through PCB pin layout wiring, providing a synchronous clock signal to ensure unified processing and stable output of video data. In the figure, 148MHz specifically refers to 148.5MHz. 148.5MHz is the image pixel clock, that is, in a display system with a resolution of 1920*1080 and a refresh rate of 60Hz, the pixel clock PCLK = 2200 (total number of horizontal pixels) * 1125 (total number of vertical lines) * 60Hz = 148.5MHz. The 100MHz differential clock is the basic clock required for DDR4 operation.
[0046] Furthermore, the network streaming media input module adopts an RJ45 network interface 8. In this embodiment, the network streaming media data is input through the RJ45 network interface 8, decoded by the CPU 7 (HI3536), transmitted via PCIe, and stored in the DDR4 memory. The control card 4 will send out the routing table in real time. Each input FPGA 3 will temporarily store the received data in its local DDR4 memory, and then respond to the splicing command issued by the CPU 7 (HI3536) of the control card 4 to complete the processing such as image scaling, overlay editing, and RGB to YUV format conversion. Finally, the image data is output through the connected HDMI output conversion chip 10.
[0047] See Figure 3 The diagram shows one of the 16 HDMI ports. Since all 16 ports have identical circuitry, only one is described here. J15 is HDMI input port 1, which can connect to a computer, webcam, and other external devices that output image / video signals. J15 has four sets of differential HDMI signal outputs to pins 26-34 of U46. Y3 provides a 27MHz clock. Network R0-R7 are 8-bit red primary color signal outputs, network G0-G7 are 8-bit green primary color signal outputs, and network B0-B7 are 8-bit blue primary color signal outputs, forming a total RGB-TTL 24-bit signal. RN41-RN46 are damping resistor arrays, each outputting four TTL signals to the FPGA. Pins 9 and 10 of the chip are horizontal and vertical scan signals. Pin 75 outputs the pixel clock signal PCLK, generated by the chip. The main purpose of HDMI to RGB-TTL conversion is to generate a level signal that the FPGA can recognize.
[0048] The working principle of this embodiment is as follows:
[0049] The signal from the external image device is transmitted to the input conversion chip 2 through the input interface 1. The input conversion chip 2 converts the input HDMI signal into an RGB signal. The input FPGA 3 encodes and packages the RGB signal into image data. In this embodiment, there are 16 input interfaces 1. Each input FPGA 3 receives four signals. After clock recovery and data alignment of the signal, each input FPGA 3 transmits the image data to the management FPGA 5 through the SerDes high-speed bus.
[0050] Meanwhile, control card 4 receives network streaming media data (RTSP / RTMP, etc.) through the RJ45 interface. After being decoded by the built-in Hisilicon chip (HI3536) of control card 4, the data is transmitted to DDR4 memory via the PCIe channel. CPU 7 of control card 4 sends screen layout instructions and mixing parameters to management FPGA 5 through the I2C bus. At the same time, HI3536 configures and outputs the underlying hardware parameters of FPGA 9 and HDMI conversion chip registers through the IIC bus. Management FPGA 5 selects a specified signal source from memory for dynamic splicing processing according to the received control instructions.
[0051] CPU7 (HI3536) establishes a connection and communication with management FPGA5 via the SPI bus and issues dynamic routes. Management FPGA5, based on the issued dynamic routing table, mixes local image data with network stream data and distributes it to each output FPGA9. Output FPGA9 is used to convert the received image data into YUV signals. After each output FPGA9 stores the data in its local DDR4 memory, CPU7 (HI3536) sends configuration commands to the output FPGA9 via the SPI bus. Upon receiving the configuration commands, management FPGA5 issues commands to the output FPGA9 via the IIC bus to execute multiple commands. In this solution, the management FPGA5 only forwards data, while each output FPGA9 has a buffering function that can cache image data into the corresponding DDR4 memory. After receiving the splicing command from FPGA5, each output FPGA9 will exchange and splice the image pixel data through the SERDES interface. After splicing, it will be transmitted to the output conversion chip 10 in YUV-TTL mode for YUV-TTL to HDMI image signal conversion. Finally, it will be output to the external display device through the output interface 11, thereby realizing the synchronous splicing display of 16 signals.
[0052] As can be seen from the above embodiments, this application can reduce network stream transmission latency, reduce synchronization errors of all input signals, and improve system scalability by centrally managing the scheduling of FPGA5.
[0053] See Figures 7-10 Preferably, the distributed splicing device in this embodiment can be installed inside a chassis. The chassis in the figure is only a schematic diagram. Without affecting the operation of this device, the chassis can be of any structure, which will not be described in detail here.
[0054] The above description is merely an exemplary embodiment of the present utility model and does not limit the patent scope of the present utility model. Any equivalent structural transformations made based on the technical concept of the present utility model and the contents of the present utility model specification and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present utility model.
Claims
1. A distributed video splicing device, characterized in that, It includes several local input modules connected to an external image device, a management module connected to the several local input modules, several output modules connected to the management module, and a network streaming media input module connected to the management module, wherein the output modules are connected to an external display device.
2. The distributed video splicing device according to claim 1, characterized in that, The local input module includes an input interface (1) connected to the external image device, an input conversion chip (2) electrically connected to the input interface (1), and an input FPGA (3) electrically connected to the input conversion chip (2). The input FPGA is electrically connected to the management module, and the input conversion chip (2) is used to output RGB signals to the input FPGA (3).
3. The distributed video splicing device according to claim 2, characterized in that, The input FPGA (3) is electrically connected to the management module through a high-speed serial differential interface.
4. The distributed video splicing device according to claim 1, characterized in that, The output module includes an output FPGA (9) electrically connected to the management module, an output conversion chip (10) electrically connected to the output FPGA (9), and an output interface (11) electrically connected to the output conversion chip (10). The output interface (11) is connected to the external display device. The output conversion chip (10) is used to convert the received YUV signal and output it to the output interface (11).
5. The distributed video splicing device according to claim 4, characterized in that, The output FPGA (9) is electrically connected to the management module via a high-speed serial differential interface.
6. The distributed video splicing device according to claim 1, characterized in that, The management module includes a management FPGA (5) electrically connected to the local input module and the output module, a control card (4) electrically connected to the management FPGA (5), a memory (6) and a CPU (7) electrically connected to the control card (4), and the control card (4) is electrically connected to the network streaming media input module.
7. The distributed video splicing device according to claim 1, characterized in that, The network streaming media input module uses an RJ45 network interface (8).