A wide-input micro-SIP packaged isolated regulated power supply module and its control circuit.

Abstract

This invention discloses a wide-input micro-SIP packaged isolated voltage regulator module and its control circuit, belonging to the technical field of voltage regulator modules. The voltage regulator module adopts a six-layer vertical stacked structure, including a metal heat sink, a chip layer integrating GaN power switches and a control ASIC, a multi-layer ceramic substrate with embedded capacitors, an embedded magnetic layer integrating a planar transformer, a three-dimensional creepage structure isolation barrier layer, and a bottom solder ball array. The control ASIC samples the input voltage and load current in real time, dynamically switching between PWM mode, frequency hopping mode, burst mode, or resonant mode according to the input voltage threshold and load conditions. In resonant mode, valley-level turn-on is achieved by detecting the drain voltage valley. In PWM mode, frequency conversion control inversely proportional to the input voltage is used. This invention achieves high-efficiency voltage regulation output under wide input voltage through SIP packaging and multi-mode adaptive control, significantly reducing module size and standby power consumption.

Description

Technical Field

[0001] This invention relates to the field of voltage regulator module technology, and more particularly to a voltage regulator module isolated in a wide-input micro SIP package and its control circuit. Background Technology

[0002] Currently, there is a growing demand for isolated voltage regulator modules with wide input voltage, high efficiency, and small size in fields such as industrial automation, communication equipment, automotive electronics, and high-performance computing. Existing isolated power supply modules mostly adopt traditional PWM control architectures and designs that combine discrete magnetic components and power devices. Common implementation schemes include hard-switching flyback or half-bridge topologies based on silicon-based MOSFETs, coupled with independent transformers and external control ICs. The overall structure is large and has low integration, making it difficult to meet the requirements of high power density and miniaturized packaging (such as SIP, System in Package).

[0003] In traditional fixed-frequency hard-switching topologies, the drain-source voltage and the current flowing through the power switch overlap significantly during each cycle of turn-on and turn-off. The resulting switching losses are proportional to the square of the voltage stress experienced by the switch instantaneously. As the input voltage increases from its nominal value to its maximum value, the losses for each switching action rise sharply with a quadratic curve.

[0004] Under high input voltage conditions, switching losses become the dominant component of total losses, leading to a significant decrease in the overall efficiency of the power module and the generation of a large amount of heat. To control temperature rise, it is often necessary to reduce the switching frequency or increase the size of the heat sink, directly sacrificing the power density and dynamic response speed of the power supply, and increasing the complexity and cost of system thermal management. This contradiction is particularly prominent in wide-voltage application scenarios that pursue high efficiency and miniaturization.

[0005] Existing control strategies are mostly simplistic and rigid, typically operating only in a fixed-frequency PWM mode. While this mode can provide good dynamic response under heavy loads, the switching losses at the fixed frequency increase under light loads or no loads, resulting in low efficiency under light loads and failing to meet modern stringent standby energy efficiency standards. Summary of the Invention

[0006] To overcome the shortcomings mentioned above, this invention aims to provide a wide-input micro SIP packaged isolated regulated power supply module and its control circuit, which can solve the above problems.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] A wide-input micro SIP packaged isolated voltage regulator module includes a six-layer vertical stacked structure, which from top to bottom consists of a metal heat sink, a chip layer, a multilayer ceramic substrate, an embedded magnetic layer, an isolation barrier layer, and a bottom solder ball array.

[0009] Its features are,

[0010] The chip layer integrates a primary-side GaN power switch, a secondary-side GaN synchronous rectifier, and a control ASIC.

[0011] The embedded magnetic layer integrates a planar transformer;

[0012] The control ASIC dynamically switches the operating mode according to the input voltage and load current to achieve efficient voltage regulation output under wide input voltage conditions.

[0013] Preferably, the multilayer ceramic substrate has an input filter capacitor and an output filter capacitor embedded inside, which are electrically and mechanically connected to the chip layer through copper pillar bumps.

[0014] Preferably, the isolation barrier layer includes a laser-etched microgroove structure filled with a high-insulation-strength polyimide gel to form a three-dimensional creepage isolation structure.

[0015] Preferably, the bottom solder ball array is a copper pillar bump array, which also serves as an electrical connection pin and a heat conduction path.

[0016] A control circuit for a wide-input micro-SIP packaged isolated voltage regulator module, the control circuit comprising:

[0017] The sampling unit is used to acquire input voltage, output voltage, and load current in real time.

[0018] An error calculation unit is used to generate an error signal between the output voltage and the reference voltage.

[0019] The mode switching unit is used to select and switch to PWM mode, frequency hopping mode, burst mode or resonant mode based on the comparison between the input voltage and a preset threshold.

[0020] A switching frequency adjustment unit is used to dynamically adjust the switching frequency in different modes;

[0021] The digital PWM module is used to generate drive signals based on error signals.

[0022] Preferably, the mode switching unit switches to resonant mode based on whether the input voltage is higher than the high voltage threshold; when the input voltage falls back to below the low voltage threshold, it switches back to PWM mode and introduces a hysteresis interval to prevent frequent mode switching.

[0023] Preferably, in resonant mode, the control ASIC detects the resonant valley of the drain voltage of the switching transistor and turns on the switching transistor at the lowest voltage point to achieve valley turn-on and reduce turn-on losses.

[0024] Preferably, in PWM mode, the switching frequency adjustment unit adjusts the switching frequency in an inversely proportional manner according to the change in input voltage, so as to reduce switching losses under high input voltage.

[0025] Preferably, in frequency hopping mode, the switching frequency adjustment unit linearly or segmentally reduces the switching frequency according to the load current to improve light-load efficiency; in burst mode, the control ASIC enters a sleep or wake-up state according to the comparison between the output voltage and the preset hysteresis window to realize intermittent switching control and reduce standby power consumption.

[0026] Preferably, the digital PWM module generates a drive signal according to the duty cycle formula in PWM mode and generates a drive signal according to the conduction time in resonant mode, thereby realizing adaptive output of the control quantity.

[0027] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0028] Using SIP packaging, GaN power devices, control ASICs, planar transformers, filter capacitors and other multi-layer structures are integrated into one, significantly reducing the size and adapting to high-density installation scenarios.

[0029] Utilizing GaN power devices reduces switching losses; the control ASIC supports multi-mode adaptive switching, optimizing efficiency under different input voltages and load conditions. Especially under high input voltages, valley switching is achieved through resonant mode, further reducing turn-on losses. The control circuit adjusts the switching frequency and operating mode in real time according to the input voltage, supporting a wide input range from low to high voltage while maintaining regulated output. In no-load burst mode, it enters an intermittent operating state with extremely low standby power consumption, meeting green energy-saving standards.

[0030] The structure employs a six-layer vertical stacking configuration: a metal heat sink, a chip layer, a ceramic substrate, an embedded magnetic layer, an isolation barrier layer, and a bottom solder ball array. This structure achieves tight integration of power devices, control chips, passive components, and heat dissipation paths in three-dimensional space. High-density electrical interconnections and mechanical connections are achieved through flip-chip and copper pillar bump technology, which is the physical basis for miniaturization and high power density.

[0031] The system dynamically switches operating modes based on input voltage and load current, including heavy-load fixed-frequency PWM mode, light-load frequency-hopping mode, no-load burst mode, and resonant mode under high-voltage input. This achieves efficiency optimization across all operating conditions from full load to no-load, and ensures fast dynamic response and accurate voltage regulation.

[0032] By detecting the resonant valley of the drain voltage of the switching transistor, zero-voltage turn-on is precisely achieved, virtually eliminating turn-on losses. In this mode, the conduction time is directly controlled, and the switching frequency is naturally determined by the resonant circuit, achieving a combination of high efficiency and soft switching. In PWM mode, a frequency conversion strategy inversely proportional to the input voltage is adopted to further smoothly reduce switching losses. Attached Figure Description

[0033] Figure 1 This is a structural block diagram of the voltage regulator module of the present invention;

[0034] Figure 2 This is a structural block diagram of the control circuit of the voltage regulator module of the present invention;

[0035] Figure 3 This is a circuit diagram of the control circuit for the voltage regulator module of the present invention;

[0036] Figure 4 This is a logic block diagram of the control circuit for the voltage regulator module of the present invention;

[0037] Figure 5 This is another logic block diagram of the control circuit for the regulated power supply module of the present invention.

[0038] The reference numerals and names in the figure are as follows: metal heat sink 10, chip layer 20, ceramic substrate 30, embedded magnetic layer 40, isolation barrier layer 50, and bottom solder ball array 60. Detailed Implementation

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] Example 1

[0041] Reference Figures 1 to 2 As shown, this embodiment discloses a wide-voltage input micro SIP packaged isolated voltage regulator module, which consists of a metal heat sink 10, a chip layer 20, a multilayer ceramic substrate 30, an embedded magnetic layer 40, an isolation barrier layer 50, and a bottom solder ball array 60, from top to bottom.

[0042] The metal heat sink 10 is located on the top layer and is made of copper alloy. Its inner surface is flat, and its outer surface has laser-etched micro-grooves to increase the heat dissipation area.

[0043] Chip layer 20 includes two primary-side GaN power MOSFETs for main switching and active clamping, respectively; two secondary-side GaN synchronous rectification MOSFETs for synchronous rectification; and a control ASIC that integrates a RISC-V core, ADC, DPWM, etc.

[0044] A capacitor array is embedded inside the ceramic substrate 30 for input and output filtering.

[0045] The chip layer 20 is electrically and mechanically connected to the ceramic substrate 30 via copper pillar bumps. The ceramic substrate 30 contains multiple layers of wiring to achieve electrical interconnection. On the upper layer of the ceramic substrate 30, near the chip layer 20, there are pads for connecting the chip bumps.

[0046] The intermediate layer of the ceramic substrate 30 is designed with isolation grooves (three-dimensional creepage structure).

[0047] The embedded magnetic layer 40 is a planar transformer manufactured using LTCC technology. The primary and secondary windings of the transformer are arranged alternately, and there is an insulating layer between the layers. The ratio of the primary winding to the secondary winding of the transformer is 4:1.

[0048] Preferably, the transformer core material is a low-temperature co-fired ferrite slurry.

[0049] In the region between the primary and secondary edges of the substrate, the isolation barrier layer 50 is filled with high-insulation-strength polyimide gel through laser-etched microgrooves to form a three-dimensional creepage structure.

[0050] The bottom solder ball array 60 uses a copper pillar bump array as the module's input, output, and control pins. The bump array also serves to conduct heat to the system PCB.

[0051] Furthermore, the metal heat sink 10, chip layer 20, multilayer ceramic substrate 30, embedded magnetic layer 40, isolation barrier layer 50 and bottom solder ball array 60 all adopt flip-chip technology to bond the following chips to the substrate.

[0052] The working principle is as follows: a wide-input micro SIP packaged isolated voltage regulator module. It has six layers from top to bottom. The top layer is a metal heat sink 10, made of copper alloy. Its inner surface is very smooth, while its outer surface has laser-etched micro-grooves. These grooves increase the heat dissipation area, helping the module dissipate heat.

[0053] Below the metal heat sink 10 is the chip layer 20. Chip layer 20 has two primary-side GaN power MOSFETs, one for main switching and the other for active clamping. There are also two secondary-side GaN synchronous rectifier MOSFETs for synchronous rectification. The control ASIC integrates a RISC-V core, ADC, and DPWM. The control ASIC manages the switching process of the entire module.

[0054] Below chip layer 20 is a multilayer ceramic substrate 30. Capacitors and resistors are embedded within the ceramic substrate 30 for input and output filtering and bypassing. Chip layer 20 is connected to the ceramic substrate 30 via copper pillar bumps. The ceramic substrate 30 contains multiple layers of wiring. These wirings enable electrical interconnection. The upper layer of the ceramic substrate 30 has pads. These pads are used to connect the chip bumps. The middle layer of the ceramic substrate 30 is designed with isolation trenches. These isolation trenches form a three-dimensional creepage structure, enhancing electrical isolation performance.

[0055] Below the ceramic substrate 30 is an embedded magnetic layer 40. The embedded magnetic layer 40 is fabricated using LTCC technology and contains a planar transformer and a filter inductor. The primary and secondary windings of the transformer are staggered. Insulating layers separate the winding layers. The transformer core material is low-temperature co-fired ferrite paste. The transformer achieves voltage conversion and isolation.

[0056] In the substrate, the region located between the primary and secondary edges is the isolation barrier layer 50. The isolation barrier layer 50 contains laser-etched microgrooves. These microgrooves are filled with a high-insulation-strength polyimide gel. This forms a three-dimensional creepage structure, further ensuring the safety of electrical isolation.

[0057] The bottom layer of the module is the bottom solder ball array 60. The bottom solder ball array 60 uses a copper pillar bump array. It serves as the module's input, output, and control pins. In summary, the module operates as follows: Input voltage enters through the bottom solder ball array 60. Capacitors and resistors within the ceramic substrate 30 filter the voltage. The control ASIC 20 controls the switching of the primary-side GaN MOSFETs. Switching energy is transferred through a transformer in the embedded magnetic layer 40. The transformer provides necessary electrical isolation. The secondary-side GaN MOSFETs perform synchronous rectification, and a stable output voltage is output after filtering. The generated heat is dissipated through the metal heat sink 10 and the bottom solder ball array 60. The isolation barrier layer 50 and the three-dimensional structure in the ceramic substrate 30 provide reliable insulation. Ultimately, this achieves the conversion of a wide range of input voltages into a stable, isolated output voltage.

[0058] In traditional fixed-frequency hard-switching power supplies, the switching losses of the power switching transistors are proportional to the square of the input voltage. When the input voltage rises from its nominal value to its maximum value, the switching losses increase dramatically.

[0059] Example 2

[0060] This embodiment includes all the contents of one or more of the above embodiments, and refers to... Figures 3 to 5 As shown in the figure, this embodiment also discloses a control circuit for a wide-voltage input micro SIP packaged isolated voltage regulator module, including the following: a sampling unit, an error calculation unit, a mode switching unit, a power conversion unit, a filtering unit, and a switching frequency adjustment unit.

[0061] The sampling unit is an ADC module that periodically samples the input voltage, output voltage, and load current; the error calculation unit compares the collected output voltage with the reference voltage to generate an error signal.

[0062] Furthermore, the control ASIC continuously samples the input voltage. and load current Dynamically adjust the switching frequency It also allows for seamless switching between different operating modes. This is achieved using real-time sampled input voltage. Based on this, the ASIC is controlled to compare it with a set threshold, and the mode switching unit selects to switch to the corresponding working mode.

[0063] When the input voltage Above the high voltage threshold When the input voltage is high, it enters resonant mode; when the input voltage is low, it enters resonant mode. Below When that happens, it returns to PWM mode. Among these, This indicates a hysteresis voltage, which prevents frequent and repeated switching of the operating mode when the input voltage fluctuates slightly near the threshold point.

[0064] Furthermore, the power conversion unit consists of two primary-side GaN power MOSFET switches M1 and M2, two secondary-side GaN synchronous rectifier MOSFET switches SR1 and SR2, and a planar transformer. Voltage conversion is achieved through the planar transformer.

[0065] The filtering unit consists of a capacitor array embedded inside the ceramic substrate 30. The input filter Cin filters out the input voltage ripple; the output filter Cout smooths the output voltage and reduces ripple.

[0066] In PWM mode, the control ASIC adjusts the current input voltage. The value sets the frequency of this switching cycle. The switching frequency is mentioned above. Approximately the same as the input voltage They are inversely proportional. For example, when the input voltage is low, the switching frequency is increased by the switching frequency adjustment unit; when the input voltage increases, the switching frequency is decreased, which can directly reduce the number of times the switching transistor switches in each cycle, thereby suppressing the switching losses that increase sharply due to the increase in voltage.

[0067] Voltage regulation is achieved by adjusting the on-time D of the power switch within a fixed frequency cycle. (Based on error...) Calculate the required duty cycle Then, the DPWM module switches at the currently set switching frequency. Based on this, generate a pulse width of The control signal drives the power switching transistor, which adapts to changes in input voltage while precisely regulating the output energy.

[0068] Specifically, the control ASIC adaptively switches between different operating modes through real-time sampling and algorithm calculation to cope with different operating conditions from full load to no load. Under any load, the first priority is to ensure that the output voltage is stable at the set value, and the second priority is to maximize system energy efficiency. The control basis for all different operating modes begins with the monitoring and error calculation of the output voltage.

[0069] The output voltage is periodically sampled by the built-in ADC module. and with high-precision internal reference voltage Compare and generate an error signal:

[0070]

[0071] in, This represents the error at time n, the deviation between the expected voltage and the actual voltage. A positive value indicates that the actual voltage is too low, requiring an increase in energy input; a negative value indicates that the voltage is too high, requiring a decrease in energy input. This represents the reference voltage, which is generated by a high-precision, low-temperature drift bandgap reference source inside the chip and is a fixed voltage value. This represents the output voltage sample value at time n, which is obtained by real-time sampling of the output terminal through the ADC module.

[0072] PWM modes include: heavy-load fixed-frequency PWM mode, light-load frequency-hopping mode, and no-load burst mode.

[0073] Specific examples are provided:

[0074] 1. In heavy-load fixed-frequency PWM mode, when the load current... When the threshold is exceeded, it is activated to prioritize dynamic response speed and low output ripple, meeting the high performance requirements under heavy load.

[0075] In this operating mode, the control ASIC operates at a fixed high-frequency switching frequency. Below, based on the error signal Calculate and output the PWM duty cycle for the next cycle in real time. The calculation formula is expressed as follows:

[0076]

[0077] in, This represents the duty cycle at time n, which determines the proportion of the power switch's on-time within a switching cycle. Its value is typically between 0% and 100%, directly controlling the energy delivered to the load. This represents the historical cumulative sum of errors, which is the algebraic sum of all errors e from the initial time to the current time n. This represents the rate of change of the error, the difference between the error at the current moment and the error at the previous moment. A positive value indicates that the error is increasing and the voltage is deviating from the target, while a negative value indicates that the error is decreasing and the voltage is returning to the target.

[0078] Based on the calculation A fixed-frequency, variable-duty-cycle drive signal is generated to control the GaN power switch. Through high-frequency, continuous closed-loop regulation, the output voltage is ensured even in the face of input voltage fluctuations or load step changes. Closely track the reference voltage This enables rapid recovery and precise voltage regulation.

[0079] 2. In light-load frequency hopping mode, when the load current... It is activated when the load drops to the light load threshold. While maintaining stable output voltage, it significantly reduces switching losses by lowering the switching frequency, thereby improving light load efficiency.

[0080] In this operating mode, the switching frequency It is no longer fixed; it is adjusted in real time according to the load current. The frequency decreases linearly or piecewise as the load decreases, as shown below:

[0081]

[0082] Where k is the frequency-load ratio coefficient, which determines the switching frequency. With load current The slope of the change; This indicates the minimum permissible switching frequency, the lowest allowed frequency limit in continuous conduction mode, used to avoid audio noise and maintain control loop stability.

[0083] In this operating mode, the switching cycle becomes longer, but within each effective switching cycle, the real-time error sampled for that cycle is... Calculate and update the duty cycle D. Maintain the output voltage while conserving power. Closely track the reference voltage .

[0084] 3. No-load burst mode, under load current It is activated when the load is extremely low or close to no load, minimizing standby power consumption and meeting the highest energy efficiency standards. In no-load burst mode, it enters an intermittent working state, automatically switching between sleep and wake-up periods, forming a hysteresis control.

[0085] During sleep mode, when the output voltage The power consumption increases slowly due to the microampere level at the back end, eventually reaching its upper limit. At this time, all power switches are turned off, and only the monitoring circuit operates at extremely low power, at which point the switching loss is almost zero.

[0086] During the wake-up period, when the output voltage Gradually decreasing to the lower limit due to load consumption. Upon rapid awakening, the power transistor is driven to emit a series of high-frequency PWM pulses, quickly replenishing energy to the output capacitor. The output voltage... Strictly limited to Centered on, with a width of Within the hysteresis window. In this operating mode, although a lower frequency voltage ripple is introduced, its average value remains stable, and standby power consumption is reduced to an extremely low level.

[0087] Furthermore, when switching to resonant mode, after the switching transistor is turned off, the primary inductance Lp of the transformer and the parasitic capacitance Coss of the switching transistor will resonate, causing the drain voltage of the switching transistor to exhibit an oscillating waveform that first decreases and then increases. The control ASIC detects this voltage through a dedicated pin.

[0088] At this point, the turn-on command is actively delayed, waiting for the voltage to oscillate to the first lowest point. Upon detecting the valley, the control ASIC immediately turns on the switching transistor, ensuring that the voltage across the transistor has dropped to its minimum when it is turned on, thus essentially eliminating turn-on losses.

[0089] In resonant mode, the switching period It consists of two parts: conduction time and variable resonance waiting time Variable resonant waiting time The resonant period is determined by the primary inductance Lp of the transformer and the parasitic capacitance Coss of the switching transistor.

[0090] In resonant mode, the control output of the controller no longer determines the duty cycle, but directly determines the on-time of each cycle. The given conduction time varies with the heavier the load or the lower the input voltage. The longer the switching frequency, the shorter the switching frequency. Represented as: It changes naturally with variations in input voltage and load.

[0091] It is important to note that the output is interpreted as different quantities depending on the current operating mode: in PWM mode, it is interpreted as the duty cycle D, and in resonant mode, it is interpreted as the on-time. .

[0092] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

Claims

1. A wide-input micro SIP packaged isolated voltage regulator module, comprising a six-layer vertical stacked structure, from top to bottom being a metal heat sink (10), a chip layer (20), a multilayer ceramic substrate (30), an embedded magnetic layer (40), an isolation barrier layer (50), and a bottom solder ball array (60). Its features are, The chip layer (20) integrates a primary GaN power switch, a secondary GaN synchronous rectifier, and a control ASIC. The embedded magnetic layer (40) integrates a planar transformer; The control ASIC dynamically switches the operating mode according to the input voltage and load current to achieve efficient voltage regulation output under wide input voltage conditions.

2. The voltage regulator module according to claim 1, characterized in that, The multilayer ceramic substrate (30) has an input filter capacitor and an output filter capacitor embedded inside, which are electrically and mechanically connected to the chip layer through copper pillar bumps.

3. The voltage regulator module according to claim 1, characterized in that, The isolation barrier layer (50) includes a laser-etched microgroove structure filled with a high-insulation-strength polyimide gel to form a three-dimensional creepage isolation structure.

4. The voltage regulator module according to claim 1, characterized in that, The bottom solder ball array (60) uses a copper pillar bump array, which also serves as an electrical connection pin and a heat conduction path.

5. A control circuit for a wide-input micro-SIP packaged isolated regulated power supply module, comprising the regulated power supply module of claim 1, characterized in that, The control circuit of the regulated power supply module includes: The sampling unit is used to acquire input voltage, output voltage, and load current in real time. An error calculation unit is used to generate an error signal between the output voltage and the reference voltage. The mode switching unit is used to select and switch to PWM mode, frequency hopping mode, burst mode or resonant mode based on the comparison between the input voltage and a preset threshold. A switching frequency adjustment unit is used to dynamically adjust the switching frequency in different modes; The digital PWM module is used to generate drive signals based on error signals.

6. The control circuit for the regulated power supply module according to claim 5, characterized in that, The mode switching unit switches to resonant mode based on whether the input voltage is higher than the high voltage threshold; when the input voltage falls back to the low voltage threshold, it switches back to PWM mode and introduces a hysteresis interval to prevent frequent mode switching.

7. The control circuit for the regulated power supply module according to claim 5, characterized in that, In resonant mode, the control ASIC detects the resonant valley of the drain voltage of the switching transistor and turns on the switching transistor at the lowest voltage point to achieve valley turn-on and reduce turn-on losses.

8. The control circuit for the regulated power supply module according to claim 5, characterized in that, In PWM mode, the switching frequency adjustment unit adjusts the switching frequency in an inversely proportional manner according to the change in input voltage, so as to reduce switching losses under high input voltage.

9. The control circuit for the regulated power supply module according to claim 5, characterized in that, In frequency hopping mode, the switching frequency adjustment unit linearly or segmentally reduces the switching frequency according to the load current to improve light load efficiency; in burst mode, the control ASIC enters a sleep or wake-up state according to the comparison between the output voltage and the preset hysteresis window to realize intermittent switching control and reduce standby power consumption.

10. The control circuit for the regulated power supply module according to claim 5, characterized in that, The digital PWM module generates a drive signal according to the duty cycle formula in PWM mode and generates a drive signal according to the conduction time in resonant mode, thereby realizing adaptive output of control quantity.

Images