Circuit board and method of manufacturing the same

Abstract

The application provides a circuit board and a manufacturing method thereof. A medium layer source, i.e., a resin source, is divided into multiple parts, i.e., a top medium layer above a buried device and an intermediate medium layer between core boards. In a pressing process, the top medium layer above the buried device fills a gap between an upper frame (a second core board) and the buried device, and the intermediate medium layer between the core boards quickly fills a gap between a lower frame (a first core board) and the buried device. The vertical distance of resin flow is greatly reduced, the resin flowability is greatly improved, the problem of insufficient filling caused by insufficient resin flowability or mismatched curing speed can be effectively avoided, the problem of insufficient glue filling capacity of a traditional single-frame design when processing a large-thickness component is solved, and the reliability and stability of the buried device are improved.

Description

Technical Field

[0001] This application relates to the field of circuit board technology, and in particular to a circuit board and a method for manufacturing the same. Background Technology

[0002] As electronic products trend towards miniaturization, thinner designs, and higher performance, embedded PCB technology has become a hot research topic in the industry due to its ability to significantly improve system integration density, optimize electrothermal performance, and shorten interconnection paths. This technology achieves three-dimensional integration by pre-embedding active components (such as chips), passive components, or metal substrates inside the PCB.

[0003] Currently, a single-layer frame structure is commonly used for embedding components. This involves milling a single-layer cavity into the core board or dielectric layer, placing the component inside, and then filling and laminating it using the dielectric layer (specifically, the resin formed by the melting of prepreg (PP) under heat, i.e., the filler resin) through a vacuum lamination process. However, this traditional single-layer frame design suffers from insufficient filler capacity when handling thicker components (such as high-power chips, thick-film resistors, and metal heat sinks). During lamination, the amount of dielectric layer requiring filling is enormous, and the dielectric layer flows along a long path in a single direction, making it highly susceptible to incomplete filling due to insufficient resin flowability or mismatched curing speeds. Summary of the Invention

[0004] This application provides a circuit board and its manufacturing method, which can solve the problems caused by embedding thick components and improve product yield and reliability.

[0005] This application provides a circuit board, including:

[0006] The first core board, the middle dielectric layer, the second core board, the top dielectric layer and the copper foil layer are stacked in sequence, with the second core board located above the first core board;

[0007] The first core board, the intermediate dielectric layer, and the second core board all have slots that extend through the thickness direction. The slots of the first core board, the intermediate dielectric layer, and the second core board together form a cavity. The opening size at the top of the cavity is larger than the opening size at the bottom of the cavity. An embedded device is disposed in the cavity, and the size of the embedded device is smaller than the opening size at the bottom of the cavity.

[0008] The top dielectric layer partially fills the gap between the embedded device and the second core board, and the middle dielectric layer partially fills the gap between the embedded device and the first core board.

[0009] In some embodiments, the slot width of the second core board is greater than the slot width of the first core board;

[0010] The slot width of the intermediate medium layer is less than or equal to the slot width of the second core board, and greater than or equal to the slot width of the first core board.

[0011] In some embodiments, the circuit board further includes a third core board, which is disposed between the second core board and the first core board;

[0012] The intermediate dielectric layer includes a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is disposed between the first core board and the third core board, and the second dielectric layer is disposed between the third core board and the second core board;

[0013] The third core board, the first dielectric layer, and the second dielectric layer each have a through slot along the thickness direction, and the slots of the first core board, the first dielectric layer, the third core board, the second dielectric layer, and the second core board together form the cavity.

[0014] In some embodiments, the slot widths of the second core board, the third core board, and the first core board decrease sequentially.

[0015] The slot width of the second dielectric layer is less than or equal to the slot width of the second core board, and greater than or equal to the slot width of the third core board;

[0016] The slot width of the first dielectric layer is less than or equal to the slot width of the third core board, and greater than or equal to the slot width of the first core board.

[0017] In some embodiments, the top dielectric layer also partially fills the gap between the top of the embedded device and the top dielectric layer.

[0018] In some embodiments, the embedded device includes one or more of a chip, resistor, capacitor, inductor, and metal substrate.

[0019] This application embodiment also provides a method for manufacturing a circuit board, including: processing a first core board, a second core board and an intermediate dielectric layer, wherein the first core board, the second core board and the intermediate dielectric layer each have a slot that runs through the thickness direction;

[0020] Embedded devices are placed in the slots of the first core board;

[0021] The first core plate, the intermediate dielectric layer, and the second core plate, which are equipped with the embedded device, are stacked sequentially along the thickness direction. The second core plate is located above the first core plate. The slots of the first core plate, the intermediate dielectric layer, and the second core plate together form a cavity. The opening size at the top of the cavity is larger than the opening size at the bottom of the cavity, and the size of the embedded device is smaller than the opening size at the bottom of the cavity.

[0022] A top dielectric layer and a copper foil layer are sequentially disposed above the second core board;

[0023] The layers are bonded together, wherein the top dielectric layer partially fills the gap between the embedded device and the second core board, and the middle dielectric layer partially fills the gap between the embedded device and the first core board.

[0024] In some embodiments, the top dielectric layer also partially fills the gap between the top of the embedded device and the top dielectric layer.

[0025] In some embodiments, during the pressing process:

[0026] After the top dielectric layer melts, it flows from top to bottom, sequentially filling the gap between the top of the embedded device and the top dielectric layer, and the gap between the embedded device and the second core board;

[0027] After the intermediate dielectric layer melts, it flows from top to bottom and fills the gap between the embedded device and the first core board.

[0028] In some embodiments, the step of setting the embedded device within the slot of the first core board includes:

[0029] An adhesive layer is provided at the bottom of the first core board;

[0030] An embedded device is disposed in the groove of the first core board, and the embedded device is attached to the adhesive layer;

[0031] After the pressing process is performed to bond the layers together, the method further includes removing the adhesive layer.

[0032] The circuit board provided in this application embodiment decomposes the dielectric layer source, i.e., the resin source, into multiple parts, namely the top dielectric layer above the embedded device and the intermediate dielectric layer between the core board. During the lamination process, the top dielectric layer above the device (embedded device) fills the gap between the upper frame (second core board) and the embedded device, and the intermediate dielectric layer between the core boards quickly fills the gap between the lower frame (first core board) and the embedded device. This greatly reduces the vertical distance of resin flow, significantly improves resin fluidity, and effectively avoids the problem of insufficient filling caused by insufficient resin fluidity or mismatched curing speed. It solves the problem of insufficient glue filling capacity when the traditional single-layer frame design is used to handle thicker components, and improves the reliability and stability of the embedded device.

[0033] Furthermore, the first and second core boards form a double-layer frame structure. This double-layer frame structure creates cavities for embedding components. Compared to a single-layer frame structure, it allows for more efficient component placement within a limited space, fully utilizing the thickness of the PCB and achieving a higher degree of system integration. This enables electronic products to integrate more functions in a smaller volume, meeting the demands for miniaturization and thinner designs. The thickness and slot dimensions of the double-layer frame structure can be flexibly adjusted, better accommodating components of varying thicknesses and sizes, enhancing the technology's versatility and application range. The more thorough dielectric layer filling better encapsulates the embedded components, reducing air gaps between the components and the surrounding dielectric, lowering contact thermal resistance, and improving heat dissipation efficiency. Simultaneously, good filling also helps improve the electrical performance of the circuit, reducing interference and loss during signal transmission, and enhancing the overall system's electrothermal performance. This is particularly suitable for embedding high-power chips and other components with high requirements for heat dissipation and electrical performance. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a first structural schematic diagram of a circuit board according to an embodiment of this application.

[0036] Figure 2 This is a schematic diagram of the second structure of the circuit board according to an embodiment of this application.

[0037] Figure 3 This is a schematic diagram of the third structure of the circuit board according to an embodiment of this application.

[0038] Figure 4This is a schematic diagram of the fourth structure of the circuit board according to an embodiment of this application.

[0039] Figure 5 This is a schematic flowchart illustrating a method for manufacturing a circuit board according to an embodiment of this application.

[0040] Among them, 100 is the circuit board; 10 is the first core board; 20 is the intermediate dielectric layer; 21 is the first dielectric layer; 22 is the second dielectric layer; 23 is the third dielectric layer; 30 is the second core board; 40 is the top dielectric layer; 50 is the copper foil layer; 60 is the embedded device; 70 is the third core board; 80 is the adhesive layer; and 90 is the fourth core board. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0042] This application provides a circuit board 100. The circuit board 100 can be applied to high-end communication equipment, such as 5G / 6G base station RF front-end modules; automotive electronics, including motor controllers and battery management systems (BMS) for new energy vehicles; and servers and switches for high-performance computing and data centers.

[0043] refer to Figures 1 to 2 , Figure 1 This is a first structural schematic diagram of the circuit board 100 according to an embodiment of this application. Figure 2 This is a second structural schematic diagram of the circuit board 100 according to an embodiment of this application. The circuit board 100 includes a first core board 10, an intermediate dielectric layer 20, a second core board 30, a top dielectric layer 40, and a copper foil layer 50 stacked sequentially. The second core board 30 is located above the first core board 10. The first core board 10, the intermediate dielectric layer 20, and the second core board 30 all have slots that extend through the thickness direction. The slots of the first core board 10, the intermediate dielectric layer 20, and the second core board 30 together form a cavity. The opening size at the top of the cavity is larger than the opening size at the bottom of the cavity. An embedded device 60 is disposed in the cavity. The size of the embedded device 60 is smaller than the opening size at the bottom of the cavity. The top dielectric layer 40 partially fills the gap between the embedded device 60 and the second core board 30, and the intermediate dielectric layer 20 partially fills the gap between the embedded device 60 and the first core board 10.

[0044] The first core board 10 and the second core board 30 are made of board material with good insulation and processing properties. The intermediate dielectric layer 20 and the top dielectric layer 40 are made of prepreg (PP). (During vacuum pressing, the prepreg (PP) melts under heat to form resin; after being held under high temperature and pressure for a sufficient time, the resin undergoes a cross-linking reaction, completely solidifying from the molten state to form a hard insulator. This process firmly bonds the layers of the multilayer board together, forming a stable multilayer structure.) The copper foil layer 50 is selected according to the appropriate thickness and specifications based on the circuit design requirements. The embedded device 60 includes one or more of the following: chip, resistor, capacitor, inductor, and metal substrate. A high-power chip with a larger thickness can be selected, which has high heat generation and specific electrical performance requirements.

[0045] As an example, firstly, a high-precision milling machine is used to perform grooving on the first core board 10, the intermediate dielectric layer 20, and the second core board 30. The grooving extends along the thickness direction of each board, and the shape and size of the grooving are designed according to the shape of the embedded device 60 to ensure that the embedded device 60 can be accurately placed in the cavity formed by the grooving. Subsequently, the prepared embedded device 60 is placed in the slot of the first core board 10. Then, the first core board 10, the intermediate dielectric layer 20, and the second core board 30, in which the embedded device 60 is located, are assembled in a stacked order to form a double-layer frame (the first core board 10 is the lower frame, and the second core board 30 is the upper frame, thus forming a double-layer frame structure). Their slots are aligned to form a complete cavity. The size of the embedded device 60 is smaller than the opening size at the bottom of the cavity to ensure a good fit between the embedded device 60 and the cavity, with a certain gap between the embedded device 60 and the bottom of the cavity. The pins or other connections of the embedded device 60 are compatible with the subsequent circuit design. Finally, the top dielectric layer 40 is placed over the second core board 30, and the assembled structure is placed in a vacuum press and vacuum-pressed according to the set process parameters. During the lamination process, the top dielectric layer 40 above the embedded device 60 serves as the source of the dielectric layer above the device, i.e., the resin source (the dielectric layer is specifically resin formed by the melting of prepreg (PP) under heat). Part of the top dielectric layer 40 flows into and fills the gap between the second core plate 30 (i.e., the upper frame) and the embedded device 60. Simultaneously, the intermediate dielectric layer 20 between the first core plate 10 and the second core plate 30 serves as the source of the dielectric layer between the core plates, i.e., the resin source. Part of the intermediate dielectric layer 20 fills the gap between the embedded device 60 and the first core plate 10. This configuration decomposes the source of the dielectric layer, i.e., the source of the resin, into multiple parts: the top dielectric layer 40 above the embedded device 60 and the intermediate dielectric layer 20 between the core board. During the lamination process, the top dielectric layer 40 above the device fills the gap between the upper frame (second core board 30) and the embedded device 60, while the intermediate dielectric layer 20 between the core boards quickly fills the gap between the lower frame (first core board 10) and the embedded device 60. This greatly reduces the vertical distance of resin flow, significantly improves resin fluidity, and effectively avoids the problem of insufficient filling caused by insufficient resin fluidity or mismatched curing speed. It solves the problem of insufficient glue filling capacity when the traditional single-layer frame design is used to handle thicker components, and improves the reliability and stability of the embedded device 60.

[0046] Furthermore, the first core board 10 and the second core board 30 form a double-layer frame structure. This double-layer frame structure creates cavities for embedding components. Compared to a single-layer frame structure, it allows for more efficient component placement within a limited space, fully utilizing the thickness of the PCB and achieving a higher degree of system integration. This enables electronic products to integrate more functions in a smaller volume, meeting the demands for miniaturization and thinner designs. The thickness and slot dimensions of the double-layer frame structure can be flexibly adjusted, better adapting to components of various thicknesses and sizes, enhancing the versatility and application range of this technology. The more thorough resin filling better encapsulates the embedded device 60, reducing air gaps between the device and the surrounding medium, lowering contact thermal resistance, and improving heat dissipation efficiency. Simultaneously, good filling also helps improve the electrical performance of the circuit, reducing interference and loss during signal transmission, and enhancing the overall system's electrothermal performance. This is particularly suitable for embedding high-power chips and other components with high requirements for heat dissipation and electrical performance.

[0047] In some embodiments, reference Figures 1 to 2 The groove width of the second core board 30 is greater than the groove width of the first core board 10; the groove width of the intermediate medium layer 20 is less than or equal to the groove width of the second core board 30, and greater than or equal to the groove width of the first core board 10.

[0048] As an example, in the design, the groove width of the second core board 30 is greater than the groove width of the first core board 10; the groove width of the intermediate medium layer 20 is less than or equal to the groove width of the second core board 30, and greater than or equal to the groove width of the first core board 10. That is, the groove of the upper frame is greater than the groove of the lower frame. Thus, the cavity formed by the grooves of the first core board 10, the intermediate medium layer 20, and the second core board 30 is a stepped cavity, making the opening size at the top of the cavity larger than the opening size at the bottom. During vacuum pressing, the medium layer, i.e., the prepreg (PP), is heated and melts to form resin, which flows into the cavity from all directions. Traditional vertical cavities have the same inlet and outlet size, and the width of the resin inflow "gate" is fixed. However, the stepped cavity design expands the inflow channel area at the top of the cavity (i.e., the large upper opening), essentially opening a "wide gate" for resin inflow, which has a guiding effect. Based on fluid dynamics principles, this allows more resin to simultaneously and quickly flow into the top area of ​​the cavity, significantly reducing initial flow resistance. Furthermore, in traditional vertical cavities, the bottom corner of the embedded device 60 is a typical "air trapping zone," where air is easily trapped. However, the stepped cavity has a guiding effect, allowing the resin to more effectively "wash" the bottom corner of the embedded device 60, greatly reducing the possibility of air trapping.

[0049] The stepped cavity in this example has an overwhelming advantage in guiding fluid and orderly venting compared to a vertical cavity with uniform openings at both ends. Although a vertical cavity can also fill resin, the competition between resin inflow and air outflow paths still exists, and there is still a risk of void formation. The stepped cavity, by changing the inlet shape, actively manages the fluid behavior, transforming the "competitive" relationship into a "sequential cooperative" one, achieving a superior filling effect. This application, through a "divide and conquer" strategy, transforms the difficult unidirectional deep cavity filling into the easy multidirectional shallow filling, greatly improving resin flowability and filling capacity, fundamentally avoiding air retention, and achieving near 100% void-free filling. The void-free, dense structure ensures uniform stress distribution at the embedding interface, significantly improving resistance to thermal shock, mechanical shock, and delamination, resulting in a qualitative leap in product life and reliability. It reduces the stringent requirements for the ultimate vacuum level of the laminating equipment and resin flowability, broadens the process window, improves production yield, and thus reduces overall manufacturing costs.

[0050] In some embodiments, reference Figure 3 , Figure 3 This is a schematic diagram of the third structure of the circuit board 100 according to an embodiment of this application. The circuit board 100 further includes a third core board 70, which is disposed between the second core board 30 and the first core board 10; the intermediate dielectric layer 20 includes a first dielectric layer 21 and a second dielectric layer 22, the first dielectric layer 21 being disposed between the first core board 10 and the third core board 70, and the second dielectric layer 22 being disposed between the third core board 70 and the second core board 30; wherein, the third core board 70, the first dielectric layer 21, and the second dielectric layer 22 all have slots that extend along the thickness direction, and the slots of the first core board 10, the first dielectric layer 21, the third core board 70, the second dielectric layer 22, and the second core board 30 together form a cavity.

[0051] The third core board 70 is made of a board material with good insulation and processing performance, and the third core board 70 is grooved using a high-precision milling machine.

[0052] As an example, the prepared embedded device 60 is placed in the slot of the first core board 10. Then, the first core board 10, the first dielectric layer 21, the third core board 70, the second dielectric layer 22, and the second core board 30, in which the embedded device 60 is located, are assembled in a stacked order to form a three-layer frame (the first core board 10 is the lower frame, the third core board 70 is the middle frame, and the second core board 30 is the upper frame, thus forming a three-layer frame structure). Their slots are aligned to form a complete cavity, ensuring a good fit between the embedded device 60 and the cavity, and that the pins or other connections of the embedded device 60 match the subsequent circuit design. Finally, the top dielectric layer 40 is placed over the second core board 30, and the assembled structure is placed in a vacuum press and vacuum-pressed according to the set process parameters. During the lamination process, the top dielectric layer 40 above the embedded device 60 serves as the source of the dielectric layer above the device, i.e., the resin source. Part of the top dielectric layer 40 flows into and fills the gap between the second core plate 30 (i.e., the upper frame) and the embedded device 60. Simultaneously, the first dielectric layer 21 between the first core plate 10 and the third core plate 70, and the second dielectric layer 22 between the third core plate 70 and the second core plate 30, serve as the source of the dielectric layer between the core plates, i.e., the resin source. The first dielectric layer 21 partially fills the gap between the embedded device 60 and the first core plate 10, and the second dielectric layer 22 partially fills the gap between the embedded device 60 and the third core plate 70. This configuration decomposes the source of the dielectric layer, i.e., the source of the resin, into multiple parts: the top dielectric layer 40 above the embedded device 60 and the intermediate dielectric layer 20 (first dielectric layer 21 and second dielectric layer 22) between the core board and the top dielectric layer 40 above the device. During the lamination process, the top dielectric layer 40 fills the gap between the upper frame (second core board 30) and the embedded device 60, the first dielectric layer 21 between the core boards quickly fills the gap between the lower frame (first core board 10) and the embedded device 60, and the second dielectric layer 22 between the core boards quickly fills the gap between the middle frame (third core board 70) and the embedded device 60. This greatly reduces the vertical distance of resin flow, significantly improves resin fluidity, and effectively avoids the problem of insufficient filling caused by insufficient resin fluidity or mismatched curing speed. It solves the problem of insufficient glue filling capacity when the traditional single-layer frame design is used to handle thicker components, and improves the reliability and stability of the embedded device 60. Furthermore, the first core board 10, the third core board 70, and the second core board 30 form a three-layer frame structure. This three-layer frame structure creates cavities for embedding components. Compared to a single-layer frame structure, this allows for more efficient component placement within a limited space, fully utilizing the thickness of the PCB and achieving a higher degree of system integration. This enables electronic products to integrate more functions in a smaller volume, meeting the demands for miniaturization and thinner designs in electronic products.

[0053] In some embodiments, reference Figure 3, Figure 3 This is a schematic diagram of the third structure of the circuit board 100 according to an embodiment of this application. The slot widths of the second core board 30, the third core board 70, and the first core board 10 decrease sequentially; the slot width of the second dielectric layer 22 is less than or equal to the slot width of the second core board 30, and greater than or equal to the slot width of the third core board 70; the slot width of the first dielectric layer 21 is less than or equal to the slot width of the third core board 70, and greater than or equal to the slot width of the first core board 10.

[0054] As an example, in the design, the slot widths of the second core board 30, the third core board 70, and the first core board 10 decrease sequentially; the slot width of the second dielectric layer 22 is less than or equal to the slot width of the second core board 30, and greater than or equal to the slot width of the third core board 70; the slot width of the first dielectric layer 21 is less than or equal to the slot width of the third core board 70, and greater than or equal to the slot width of the first core board 10. That is, the slots of the upper frame are larger than the slots of the middle frame, and the slots of the middle frame are larger than the slots of the lower frame. Thus, the cavity formed by the slots of the first core board 10, the first dielectric layer 21, the third core board 70, the second dielectric layer 22, and the second core board 30 together forms a stepped cavity. During vacuum pressing, the dielectric layer, i.e., the prepreg (PP), is heated and melts to form resin, which flows into the cavity from all directions. Traditional vertical cavities have a fixed inlet and outlet size, resulting in a fixed "gate" width for resin inflow. In contrast, the stepped cavity design expands the inflow channel area at the top of the cavity (i.e., a large upper opening), effectively opening a "wide gate" for resin inflow. This guides the flow, allowing more resin to simultaneously and rapidly flow into the top region of the cavity based on fluid mechanics principles, significantly reducing initial flow resistance. Furthermore, in traditional vertical cavities, the bottom corner of the embedded device 60 is a typical "air trapping zone," where air is easily trapped. The stepped cavity's guiding effect allows the resin to more effectively "flush" the bottom corner of the embedded device 60, greatly reducing the possibility of air trapping.

[0055] In some embodiments, reference Figure 4 , Figure 4This is a schematic diagram of the fourth structure of the circuit board 100 according to an embodiment of this application. The circuit board 100 further includes a fourth core board 90, which is disposed between the third core board 70 and the second core board 30; the intermediate dielectric layer 20 further includes a third dielectric layer 23, a first dielectric layer 21 is disposed between the first core board 10 and the third core board 70, a second dielectric layer 22 is disposed between the third core board 70 and the fourth core board 90, and a third dielectric layer 23 is disposed between the fourth core board 90 and the second core board 30; wherein, the fourth core board 90 and the third dielectric layer 23 both have slots that extend through the thickness direction, and the slots of the first core board 10, the first dielectric layer 21, the third core board 70, the second dielectric layer 22, the fourth core board 90, the third dielectric layer 23 and the second core board 30 together form a cavity.

[0056] The fourth core board 90 is made of a board material with good insulation and processing performance, and the fourth core board 90 is grooved using a high-precision milling machine.

[0057] The prepared embedded device 60 is placed in the slot of the first core board 10. Then, the first core board 10, first dielectric layer 21, third core board 70, second dielectric layer 22, fourth core board 90, third dielectric layer 23, and second core board 30, in which the embedded device 60 is located, are assembled in a stacked order to form a four-layer frame (first core board 10 is the lower frame, third core board 70 and fourth core board 90 are the middle frame, and second core board 30 is the upper frame, thus forming a multi-layer frame structure). Their slots are aligned to form a complete cavity, ensuring a good fit between the embedded device 60 and the cavity, and that the pins or other connections of the embedded device 60 match the subsequent circuit design. Finally, the top dielectric layer 40 is placed over the second core board 30, and the assembled structure is placed in a vacuum press and vacuum-pressed according to the set process parameters. During the lamination process, the top dielectric layer 40 above the embedded device 60 serves as the source of the dielectric layer above the device, i.e., the resin source. Part of the top dielectric layer 40 flows into and fills the gap between the second core plate 30 (i.e., the upper frame) and the embedded device 60. Simultaneously, the first dielectric layer 21 between the first core plate 10 and the third core plate 70, the second dielectric layer 22 between the third core plate 70 and the fourth core plate 90, and the third dielectric layer 23 between the fourth core plate 90 and the second core plate 30 serve as the source of the dielectric layer between the core plates, i.e., the resin source. The first dielectric layer 21 partially fills the gap between the embedded device 60 and the first core plate 10, the second dielectric layer 22 partially fills the gap between the embedded device 60 and the third core plate 70, and the third dielectric layer 23 partially fills the gap between the embedded device 60 and the fourth core plate 90. This configuration decomposes the source of the dielectric layer, i.e., the source of the resin, into multiple parts: the top dielectric layer 40 above the embedded device 60 and the intermediate dielectric layer 20 (first dielectric layer 21, second dielectric layer 22, and third dielectric layer 23) between the core board and the top dielectric layer 40 above the device. During the lamination process, the top dielectric layer 40 fills the gap between the upper frame (second core board 30) and the embedded device 60, the first dielectric layer 21 between the core boards quickly fills the gap between the lower frame (first core board 10) and the embedded device 60, and the second dielectric layer 22 between the core boards quickly fills the gap between the lower frame (first core board 10) and the embedded device 60. The third dielectric layer 23 between the core boards quickly fills the gap between the middle frame (third core board 70) and the embedded device 60, greatly reducing the vertical distance of resin flow and significantly improving resin flowability. This effectively avoids the problem of insufficient filling caused by insufficient resin flowability or mismatched curing speed, solves the problem of insufficient glue filling capacity when the traditional single-layer frame design is used to handle thicker components, and improves the reliability and stability of the embedded device 60.Furthermore, the first core board 10, the third core board 70, the fourth core board 90, and the second core board 30 form a four-layer frame structure. This four-layer frame structure creates cavities to embed components. Compared to a single-layer frame structure, this allows for more efficient component placement within a limited space, fully utilizing the thickness of the PCB and achieving a higher degree of system integration. This enables electronic products to integrate more functions in a smaller volume, meeting the demands for miniaturization and thinner designs in electronic products.

[0058] In some embodiments, the circuit board 100 further includes a fifth core board, and the intermediate dielectric layer 20 further includes a fourth dielectric layer, with a specific design similar to the above embodiments. Similarly, the circuit board 100 may also include a sixth core board, and the intermediate dielectric layer 20 may further include a fifth dielectric layer; the circuit board 100 may also include a seventh core board, and the intermediate dielectric layer 20 may further include a sixth dielectric layer.

[0059] In some embodiments, reference Figure 2 , Figure 2 This is a schematic diagram of the second structure of the circuit board 100 according to an embodiment of this application. The slot widths of the second core board 30, the fourth core board 90, the third core board 70, and the first core board 10 decrease sequentially; the slot width of the third dielectric layer 23 is less than or equal to the slot width of the second core board 30, and greater than or equal to the slot width of the fourth core board 90; the slot width of the second dielectric layer 22 is less than or equal to the slot width of the fourth core board 90, and greater than or equal to the slot width of the third core board 70; the slot width of the first dielectric layer 21 is less than or equal to the slot width of the third core board 70, and greater than or equal to the slot width of the first core board 10. That is, the slots of the upper frame are larger than the slots of the middle frame, and the slots of the middle frame are larger than the slots of the lower frame. Thus, the cavity formed by the slots of the first core board 10, the first dielectric layer 21, the third core board 70, the second dielectric layer 22, the fourth core board 90, the third dielectric layer 23, and the second core board 30 forms a stepped cavity. During vacuum lamination, the prepreg (PP) melts upon heating to form resin, which flows into the cavity from all directions. In traditional vertical cavities, the inlet and outlet are the same size, resulting in a fixed "gateway" width for resin inflow. However, the stepped cavity design expands the inflow channel area at the top of the cavity (i.e., a large upper opening), effectively opening a "wide gate" for resin inflow. This guides the flow, allowing more resin to simultaneously and rapidly enter the top region of the cavity based on fluid mechanics principles, significantly reducing initial flow resistance. Furthermore, in traditional vertical cavities, the bottom corner of the embedded device 60 is a typical "air trapping zone," where air is easily trapped. The stepped cavity's guiding effect allows the resin to more effectively "flush" the bottom corner of the embedded device 60, greatly reducing the possibility of air trapping.

[0060] In some embodiments, reference Figure 2The top dielectric layer 40 also partially fills the gap between the top of the embedded device 60 and the top dielectric layer 40.

[0061] As an example, during vacuum pressing, the resin, through a wide upper opening, first rapidly fills the gap between the top of the embedded device 60 and the top dielectric layer 40 (i.e., the flat area between the top of the device and the lower surface of the upper frame). This area is very thin, and the resin can fill it instantly, expelling the air in the area to the outside, greatly reducing the possibility of air being trapped. This facilitates void-free filling. The void-free, dense structure ensures a uniform stress distribution at the embedding interface, significantly improving resistance to thermal shock, mechanical shock, and delamination, resulting in a qualitative leap in product lifespan and reliability.

[0062] This application also provides a method for manufacturing a circuit board 100 to form the circuit board 100 described above. (See reference...) Figure 5 , Figure 5 This is a schematic flowchart illustrating a method for manufacturing a circuit board 100 according to an embodiment of this application. The manufacturing method includes the following steps:

[0063] S501, the first core board 10, the second core board 30 and the intermediate dielectric layer 20 are processed. The first core board 10, the second core board 30 and the intermediate dielectric layer 20 all have slots that run through the thickness direction.

[0064] S502, an embedded device 60 is set in the slot of the first core board 10;

[0065] S503, the first core plate 10, the intermediate dielectric layer 20, and the second core plate 30, which are provided with the embedded device 60, are stacked sequentially along the thickness direction. The second core plate 30 is located above the first core plate 10. The slots of the first core plate 10, the intermediate dielectric layer 20, and the second core plate 30 together form a cavity. The opening size at the top of the cavity is larger than the opening size at the bottom of the cavity, and the size of the embedded device 60 is smaller than the opening size at the bottom of the cavity.

[0066] S504, a top dielectric layer 40 and a copper foil layer 50 are sequentially disposed above the second core board 30;

[0067] S505, pressing is performed to bond the layers together, wherein the top dielectric layer 40 partially fills the gap between the embedded device 60 and the second core board 30, and the middle dielectric layer 20 partially fills the gap between the embedded device 60 and the first core board 10.

[0068] Please refer to the above. Figures 1 to 4 , Figure 1 This is a first structural schematic diagram of the circuit board 100 according to an embodiment of this application. Figure 2 This is a schematic diagram of the second structure of the circuit board 100 according to an embodiment of this application. Figure 3This is a schematic diagram of the third structure of the circuit board 100 according to an embodiment of this application. Figure 4 This is a schematic diagram of the fourth structure of the circuit board 100 according to an embodiment of this application.

[0069] As an example, firstly, the frame core board and prepreg are prepared. In step S501, the first core board 10, the second core board 30, and the intermediate dielectric layer 20 are first processed. Then, a high-precision milling machine is used to perform grooving processing on the first core board 10, the intermediate dielectric layer 20, and the second core board 30, respectively. That is, according to the size and thickness of the target component (embedded device 60), multiple frame core boards (first core board 10 and second core board 30) and dielectric layers (intermediate dielectric layer 20 and top dielectric layer 40) with specific grooves of different sizes are designed and processed. The frame core board can be a traditional FR-4 core board or other rigid dielectric materials.

[0070] Subsequently, the frame core board and the prepreg are stacked and pre-fixed in layers. In step S502, the prepared embedded device 60 is placed in the slot of the first core board 10. In step S503, the first core board 10, the intermediate dielectric layer 20, and the second core board 30, which contain the embedded device 60, are stacked sequentially along the thickness direction to form a double-layer frame (the first core board 10 is the lower frame, and the second core board 30 is the upper frame, thus forming a double-layer frame structure). Their slots are aligned to form a complete cavity. The opening size at the top of the cavity is larger than the opening size at the bottom, and the size of the embedded device 60 is smaller than the opening size at the bottom, ensuring a good fit between the embedded device 60 and the cavity, and creating a certain gap between the embedded device 60 and the bottom of the cavity. The pins or other connections of the embedded device 60 are matched with the subsequent circuit design. In other words, the core board with pre-attached devices, the pre-slotted core board, and the pre-slotted prepreg are aligned and stacked according to the design sequence, and pre-fixed by pre-riveting to form a "prefabricated body" with a multi-layered embedded cavity. The thickness of the frame core board can be adjusted according to the actual design, and can consist of two or more sheets.

[0071] Subsequently, the outer layer board assembly process is carried out. In step S504, a top dielectric layer 40 and a copper foil layer 50 are sequentially arranged above the second core board 30, that is, the outer layer prepreg (PP) and the outer layer copper foil are covered according to the design. The PP can be a single sheet or multiple sheets according to the design.

[0072] Finally, the lamination and adhesive filling processes are performed. In step S505, lamination is performed to bond the layers together. The top dielectric layer 40 above the embedded device 60 serves as the source of the dielectric layer above the device, i.e., the resin source. Part of the top dielectric layer 40 flows into and fills the gap between the second core board 30 (i.e., the upper frame) and the embedded device 60. Simultaneously, the intermediate dielectric layer 20 between the first core board 10 and the second core board 30 serves as the source of the dielectric layer between the core boards, i.e., the resin source. Part of the intermediate dielectric layer 20 fills the gap between the embedded device 60 and the first core board 10. That is, lamination and adhesive filling are performed through vacuum lamination. The gap between the frame core board and the device is filled by the PP from the upper PP and the PP between the core boards, completing the fabrication of the device embedded in the inner layer of the PCB. This configuration decomposes the source of the dielectric layer, i.e., the source of the resin, into multiple parts: the top dielectric layer 40 above the embedded device 60 and the intermediate dielectric layer 20 between the core board. During the lamination process, the top dielectric layer 40 above the device fills the gap between the upper frame (second core board 30) and the embedded device 60, while the intermediate dielectric layer 20 between the core boards quickly fills the gap between the lower frame (first core board 10) and the embedded device 60. This greatly reduces the vertical distance of resin flow, significantly improves resin fluidity, and effectively avoids the problem of insufficient filling caused by insufficient resin fluidity or mismatched curing speed. It solves the problem of insufficient glue filling capacity when the traditional single-layer frame design is used to handle thicker components, and improves the reliability and stability of the embedded device 60.

[0073] In some embodiments, reference Figures 1 to 2 , Figure 1 This is a first structural schematic diagram of the circuit board 100 according to an embodiment of this application. Figure 2 This is a schematic diagram of the second structure of the circuit board 100 according to an embodiment of this application. During the lamination process: the top dielectric layer 40 melts and flows from top to bottom, sequentially filling the gap between the top of the embedded device 60 and the top dielectric layer 40, and the gap between the embedded device 60 and the second core board 30; the middle dielectric layer 20 melts and flows from top to bottom, filling the gap between the embedded device 60 and the first core board 10.

[0074] As an example, during the pressing process, the top dielectric layer 40 and the middle dielectric layer 20 are filled sequentially, which can efficiently expel air and eliminate voids. Specifically, the resin flow behavior prioritizes filling the path of least resistance, and the filling process can be divided into three sequential stages: First, the top is filled laterally. A large amount of molten resin, through a wide upper opening, quickly fills the flat area between the top (or top surface) of the embedded device 60 and the lower surface of the second core plate 30. This area is thin, allowing the resin to fill it instantly and expel air from the area to the outside. Second, the resin is guided longitudinally along the sidewalls of the embedded device 60. After the aforementioned flat area is filled, the resin begins to flow downwards from all sides. At this time, because the groove width of the second core plate 30 is greater than that of the first core plate 10, a suspended "eaves" structure is formed. This "eaves" guides the resin flow, causing it to flow more concentratedly and smoothly downwards along the gap between the sidewalls of the embedded device 60 and the inner wall of the cavity, rather than splashing randomly. The third stage: bottom lateral convergence and venting. After the downward-flowing resin reaches the bottom of the cavity, it begins to laterally fill the area between the bottom surface of the embedded device 60 and the core plate from the periphery to the center. Since air is lighter than resin, it is continuously driven by the resin from top to bottom and from the center to the edges throughout the process. Finally, the air is smoothly discharged into the dielectric layer through the gaps at the edge of the cavity and then removed by the vacuum system, thus avoiding the formation of voids in the corners and bottom. This achieves void-free filling. The void-free, dense structure ensures a uniform stress distribution at the embedding interface, significantly improving resistance to thermal shock, mechanical shock, and delamination, resulting in a qualitative leap in product life and reliability.

[0075] In some embodiments, reference Figures 1 to 4 , Figure 1 This is a first structural schematic diagram of the circuit board 100 according to an embodiment of this application. Figure 2 This is a schematic diagram of the second structure of the circuit board 100 according to an embodiment of this application. Figure 3 This is a schematic diagram of the third structure of the circuit board 100 according to an embodiment of this application. Figure 4 This is a fourth structural schematic diagram of the circuit board 100 according to an embodiment of this application. The method of setting an embedded device 60 within a slot in the first core board 10 includes: setting an adhesive layer 80 at the bottom of the first core board 10; setting the embedded device 60 within the slot in the first core board 10, such that the embedded device 60 is adhered to the adhesive layer 80; and after pressing to bond the layers together, the method further includes: removing the adhesive layer 80.

[0076] As an example, firstly, an adhesive layer 80 (e.g., a micro-adhesive film) is placed on the bottom of the first core board 10. Then, an embedded device 60 is placed in a slot in the first core board 10, allowing the embedded device 60 to adhere to the adhesive layer 80. This adhesive layer 80 facilitates the installation of the embedded device 60, ensuring the stability and reliability of its installation. Finally, after lamination to bond the layers together, the adhesive layer 80 is removed, eliminating potential electrical interference, reducing signal attenuation and distortion, improving signal integrity and transmission quality, and completing the fabrication of the circuit board 100.

[0077] In the description of this application, it should be understood that terms such as “first” and “second” are used only to distinguish similar objects and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0078] The circuit board and its manufacturing method provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A circuit board, characterized in that, include: The first core board, the middle dielectric layer, the second core board, the top dielectric layer and the copper foil layer are stacked in sequence, with the second core board located above the first core board; The first core board, the intermediate dielectric layer, and the second core board all have slots that extend through the thickness direction. The slots of the first core board, the intermediate dielectric layer, and the second core board together form a cavity. The opening size at the top of the cavity is larger than the opening size at the bottom of the cavity. An embedded device is disposed in the cavity, and the size of the embedded device is smaller than the opening size at the bottom of the cavity. The top dielectric layer partially fills the gap between the embedded device and the second core board, and the middle dielectric layer partially fills the gap between the embedded device and the first core board.

2. The circuit board according to claim 1, characterized in that: The slot width of the second core board is greater than the slot width of the first core board; The slot width of the intermediate medium layer is less than or equal to the slot width of the second core board, and greater than or equal to the slot width of the first core board.

3. The circuit board according to claim 1, characterized in that, The circuit board further includes a third core board, which is disposed between the second core board and the first core board; The intermediate dielectric layer includes a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is disposed between the first core board and the third core board, and the second dielectric layer is disposed between the third core board and the second core board; The third core board, the first dielectric layer, and the second dielectric layer each have a through slot along the thickness direction, and the slots of the first core board, the first dielectric layer, the third core board, the second dielectric layer, and the second core board together form the cavity.

4. The circuit board according to claim 3, characterized in that: The slot widths of the second core board, the third core board, and the first core board decrease sequentially. The slot width of the second dielectric layer is less than or equal to the slot width of the second core board, and greater than or equal to the slot width of the third core board; The slot width of the first dielectric layer is less than or equal to the slot width of the third core board, and greater than or equal to the slot width of the first core board.

5. The circuit board according to any one of claims 1 to 4, characterized in that, The top dielectric layer also partially fills the gap between the top of the embedded device and the top dielectric layer.

6. The circuit board according to any one of claims 1 to 4, characterized in that, The embedded device includes one or more of the following: chip, resistor, capacitor, inductor, and metal substrate.

7. A method for manufacturing a circuit board, characterized in that, include: A first core board, a second core board, and an intermediate dielectric layer are processed, and the first core board, the second core board, and the intermediate dielectric layer all have slots that extend through the thickness direction; Embedded devices are placed in the slots of the first core board; The first core plate, the intermediate dielectric layer, and the second core plate, which are equipped with the embedded device, are stacked sequentially along the thickness direction. The second core plate is located above the first core plate. The slots of the first core plate, the intermediate dielectric layer, and the second core plate together form a cavity. The opening size at the top of the cavity is larger than the opening size at the bottom of the cavity, and the size of the embedded device is smaller than the opening size at the bottom of the cavity. A top dielectric layer and a copper foil layer are sequentially disposed above the second core board; The layers are bonded together, wherein the top dielectric layer partially fills the gap between the embedded device and the second core board, and the middle dielectric layer partially fills the gap between the embedded device and the first core board.

8. The manufacturing method according to claim 7, characterized in that, The top dielectric layer also partially fills the gap between the top of the embedded device and the top dielectric layer.

9. The manufacturing method according to claim 8, characterized in that, During the pressing process: After the top dielectric layer melts, it flows from top to bottom, sequentially filling the gap between the top of the embedded device and the top dielectric layer, and the gap between the embedded device and the second core board; After the intermediate dielectric layer melts, it flows from top to bottom and fills the gap between the embedded device and the first core board.

10. The manufacturing method according to any one of claims 7 to 9, characterized in that, The step of setting an embedded device within a slot in the first core board includes: An adhesive layer is provided at the bottom of the first core board; An embedded device is disposed in the groove of the first core board, and the embedded device is attached to the adhesive layer; After the pressing process is performed to bond the layers together, the method further includes removing the adhesive layer.

Images