Integrated circuit with power device and dsoi device and method of manufacturing the same

Abstract

The application relates to an integrated circuit with a power device and a DSOI device and a manufacturing method thereof, which comprises a substrate including a first active region; a first oxide layer located on the substrate and including a field oxide region and a first insulating buried layer region; a first gate located on the substrate and extending to the field oxide region; a first semiconductor layer including a field plate region located on the field oxide region and a first SOI region located on the first insulating buried layer region; a second insulating buried layer located on the first SOI region; a second semiconductor layer located on the second insulating buried layer and including a second active region; and a second gate located on the second semiconductor layer. The field oxide region and the field plate region of the application utilize a part of the DSOI structure, so that the power device can be integrated on the DSOI structure by a simpler process and at a lower cost. Compared with the circuit design in which the power device and the DSOI device are not in one die, the application has the advantages of small size, low cost and high reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to an integrated circuit having a power device and a DSOI device, and also to a method for manufacturing an integrated circuit having a power device and a DSOI device. Background Technology

[0002] Double Silicon On Insulator (DSOI) devices are formed by adding a silicon dioxide layer (SiO2) and a single-crystal silicon layer (Si) to the Silicon On Insulator (SOI) structure. They inherit the excellent resistance to single-event effects of SOI and show significant improvements over bulk silicon and SOI processes in terms of back-gate effect, total radiation dose effect, and electrode crosstalk effect. Therefore, DSOI structures have broad application prospects in some specialized fields and are currently receiving increasing research and application attention.

[0003] Figure 1 This is a schematic diagram of an exemplary DSOI device, including a substrate 110, a second buried oxide layer 124, a second semiconductor layer 134, a first buried oxide layer 122, a first semiconductor layer 132, a gate 152, a gate contact 162, a source contact 164, and a drain contact 166. The thickness of the top silicon layer (i.e., the first semiconductor layer 132) in a DSOI structure is typically quite thin, for example, only 400 Å. Laterally diffused metal-oxide-semiconductor field-effect transistors (LDMOS) generally require a certain depth of drift region to handle current and voltage, and the thickness of the top silicon layer in a DSOI structure cannot meet the depth requirements of the drift region. Therefore, the drift region (and active region) of an LDMOS is difficult to integrate into the top silicon layer of a DSOI structure.

[0004] For situations where power devices such as LDMOS need to be used in the same circuit as DSOI devices, an exemplary solution is to co-package the DSOI devices and power devices, or even connect them directly on the PCB (printed circuit board). However, this will lead to a significant increase in cost and a larger circuit size. Summary of the Invention

[0005] Therefore, it is necessary to provide an integrated circuit with power devices and DSOI devices and a method for manufacturing the same.

[0006] An integrated circuit having a power device and a DSOI device includes: a substrate including a first active region; a first oxide layer located on the substrate, including a field oxide region and a first buried insulating layer region, the field oxide region and the first buried insulating layer region being separately disposed; a first gate located on the substrate and extending from a position adjacent to the field oxide region to the field oxide region; a first semiconductor layer including a field plate region and a first SOI region, the field plate region and the first SOI region being separately disposed, the field plate region being located on the field oxide region, and the first SOI region being located on the first buried insulating layer region; a second buried insulating layer located on the first SOI region; a second semiconductor layer located on the second buried insulating layer, the second semiconductor layer including a second active region; and a second gate disposed on the second semiconductor layer; wherein the first active region, the field oxide region, the first gate and the field plate region constitute the structure of a power device, and the first buried insulating layer region, the first SOI region, the second buried insulating layer, the second active region and the second gate constitute the structure of a DSOI device.

[0007] In the aforementioned integrated circuit with power devices and DSOI devices, the field oxide region and the first buried insulating layer region are both part of the first oxide layer, and the field plate region and the first SOI region are both part of the first semiconductor layer. Therefore, the field oxide region and the field plate region utilize a portion of the DSOI structure, enabling the integration of power devices on the DSOI structure with simpler processes and lower costs. Furthermore, compared to circuit designs where the power devices and DSOI devices are not housed in a single die (DIE), this design offers advantages such as smaller size, lower cost, and higher reliability.

[0008] In one embodiment, the power device is an LDMOS, the first active region includes an LDMOS source region and an LDMOS drain region, the integrated circuit further includes a drift region located in the substrate, the drift region being at least partially located between the LDMOS source region and the LDMOS drain region, the field oxide region being located on the drift region, the first gate being located above the region between the LDMOS source region and the LDMOS drain region and extending from the edge of the LDMOS source region to the field oxide region, the LDMOS source region, the LDMOS drain region and the drift region having the same conductivity type.

[0009] In one embodiment, the integrated circuit has a field plate contact hole, an LDMOS source contact hole, and an LDMOS drain contact hole. The conductive material filled in the field plate contact hole is electrically connected to the field plate region, the conductive material filled in the LDMOS source contact hole is electrically connected to the LDMOS source region, and the conductive material filled in the LDMOS drain contact hole is electrically connected to the LDMOS drain region.

[0010] In one embodiment, the field oxide region and the first insulating buried layer region are formed in the same step, and the field plate region and the first SOI region are formed in the same step.

[0011] In one embodiment, the field oxygen region and the first insulating buried layer region have the same thickness, and the field plate region and the first SOI region have the same thickness.

[0012] In one embodiment, the double silicon-on-insulator device includes a metal-oxide-semiconductor field-effect transistor (MOSFET), and the second active region includes a MOS source region and a MOS drain region; the second gate, the MOS source region, and the MOS drain region constitute the structure of the MOSFET; the integrated circuit has a gate contact hole, a MOS source contact hole, and a MOS drain contact hole, wherein the conductive material filled in the gate contact hole is electrically connected to the second gate, the conductive material filled in the MOS source contact hole is electrically connected to the MOS source region, and the conductive material filled in the MOS drain contact hole is electrically connected to the MOS drain region.

[0013] In one embodiment, the thickness of the substrate is greater than 700 micrometers.

[0014] In one embodiment, the thickness of the first oxide layer is 1000~2000 Å.

[0015] In one embodiment, the thickness of the first oxide layer is approximately 1500 Å.

[0016] In one embodiment, the thickness of the first semiconductor layer is 1000~2000 Å.

[0017] In one embodiment, the thickness of the first semiconductor layer is approximately 1500 Å.

[0018] A method for manufacturing an integrated circuit having a power device and a DSOI device as described in any of the foregoing embodiments, wherein the field oxide region and the first insulating buried layer region are formed in the same step, and the field plate region and the first SOI region are formed in the same step.

[0019] In the aforementioned method for manufacturing integrated circuits with power devices and DSOI devices, the field oxide region and the first buried insulating layer region are formed in the same step, and the field plate region and the first SOI region are formed in the same step. Therefore, the field oxide region and the field plate region utilize a portion of the DSOI structure, enabling the integration of power devices on the DSOI structure with simpler processes and lower costs. Furthermore, compared to circuit designs where the power devices and DSOI devices are not housed in a single die (DIE), this method offers advantages such as smaller size, lower cost, and higher reliability. Attached Figure Description

[0020] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0021] Figure 1 This is a schematic diagram of an exemplary DSOI device.

[0022] Figure 2 This is a schematic diagram of an integrated circuit having a power device and a DSOI device in one embodiment of this application. Detailed Implementation

[0023] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0025] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0026] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0028] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0029] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0030] This application proposes an integrated circuit with power devices and DSOI devices, wherein the power devices are integrated on a DSOI structure. Figure 2 This is a schematic diagram of an integrated circuit with power devices and DSOI devices according to an embodiment of this application, including a substrate 210, a first oxide layer 222, a first gate 242, a first semiconductor layer 232, a second buried insulating layer 224, a second semiconductor layer 234, and a second gate 246. A first active region ( Figure 2 (Not shown). In one embodiment of this application, the substrate 210 is further provided with a drift region ( Figure 2 (Not shown in the image). The first oxide layer 222 is located on the substrate 210 and includes a field oxide region 222a and a first insulating buried layer region 222b, which are separated from each other. The first gate 242 is located on the substrate 210 and extends from a region adjacent to the field oxide region 222a to the field oxide region 222a. The portion of the first gate 242 extending to the field oxide region 222a serves as a field plate. The first semiconductor layer 232 includes a field plate region 232a and a first SOI region 232b, which are separated from each other. The field plate region 232a is located on the field oxide region 222a, and the first SOI region 232b is located on the first insulating buried layer region 222b. The field plate region 232a also serves as a field plate, generating a vertical electric field applied to the drift region. This field, combined with the horizontal electric field, forces the electric field distribution in the drift region to become more uniform, thereby reducing the surface electric field strength and increasing the device breakdown voltage. A second buried insulating layer 224 is located on the first SOI region 232b. A second semiconductor layer 234 is located on the second buried insulating layer 224, and a second active region is provided within the second semiconductor layer 234. A second gate 246 is located on the second semiconductor layer 234.

[0031] exist Figure 2 In the illustrated embodiment, the first active region, field oxide region 222a, first gate 242, and field plate region 232a constitute the structure of a power device; the first buried insulating layer region 222b, first SOI region 232b, second buried insulating layer 224, second active region, and second gate 246 constitute the structure of a double insulator-on-silicon device.

[0032] In the aforementioned integrated circuit with power devices and DSOI devices, the field oxide region 222a and the first buried insulating layer region 222b are both part of the first oxide layer 222, and the field plate region 232a and the first SOI region 232b are both part of the first semiconductor layer 232. Therefore, the field oxide region 222a and the field plate region 232a utilize a portion of the DSOI structure, thus enabling the integration of power devices on the DSOI structure with simpler processes and lower costs. Furthermore, compared to circuit designs where power devices and DSOI devices are not housed in a single die (DIE), this design offers advantages such as smaller size, lower cost, and higher reliability.

[0033] Since both the field oxide region 222a and the first insulating buried layer region 222b are part of the first oxide layer 222, they are formed in the same step. Similarly, the field plate region 232a and the first SOI region 232b are also formed in the same step. The photolithography of the field oxide region 222a and the field plate region 232a can share a single photomask with the corresponding structures of the DSOI structure (i.e., the first insulating buried layer region 222b and the first SOI region 232b), eliminating the need for additional deposition, photolithography, and etching processes. In one embodiment of this application, the field oxide region 222a and the first insulating buried layer region 222b have the same thickness. In another embodiment of this application, the field plate region 232a and the first SOI region 232b have the same thickness.

[0034] In one embodiment of this application, the substrate 210 is a semiconductor substrate. Figure 2 In the embodiment shown, the substrate 210 is made of monocrystalline silicon.

[0035] In the aforementioned integrated circuit comprising a power device and a DSOI device, the active region (i.e., the first active region) of the power device is located within the substrate 210, and therefore the channel region of the device is also located within the substrate 210. The thickness of the substrate 210 is much greater than the thickness of the top silicon layer in the DSOI structure, providing sufficient depth for the drift region and deep well. Therefore, the power device of this application can achieve the same performance as conventional bulk silicon power devices. In one embodiment of this application, the thickness of the substrate is greater than 700 micrometers.

[0036] In one embodiment of this application, the thickness of the first oxide layer 222 is 1000~2000 Å; further, it can be about 1500 Å.

[0037] In one embodiment of this application, the thickness of the first semiconductor layer 232 is 1000~2000 Å; further, it can be about 1500 Å.

[0038] In one embodiment of this application, an interlayer dielectric (ILD) layer 260 is further provided on the substrate 210. The power device also includes a field plate contact hole 265 disposed on the field plate region 232a, the field plate contact hole 265 penetrating the interlayer dielectric layer 260, and the bottom of the conductive material filled in the field plate contact hole 265 being electrically connected to the field plate region 232a.

[0039] In one embodiment of this application, the interlayer medium may be a silicon oxide layer, such as a doped or undoped silicon oxide material layer formed using a thermal chemical vapor deposition (TCVD) process or a high-density plasma chemical vapor deposition (HDPCVD) process. Specifically, it may be an undoped silicon glass (USG), phosphosilicate glass (PSG), or borosilicate phosphosilicate glass (BPSG). Alternatively, the interlayer medium may also be a boron-doped or phosphorus-doped spin-on-glass (SOG), a phosphorus-doped tetraethoxysilane (PTEOS), or a boron-doped tetraethoxysilane (BTEOS), etc.

[0040] In one embodiment of this application, the power device is an LDMOS (Laterally Diffused Metal-Oxide-Semiconductor Field-Effect Transistor), and the first active region includes an LDMOS source region and an LDMOS drain region. A drift region in the substrate 210 is at least partially located between the LDMOS source region and the LDMOS drain region. A field oxide region 222a is located on the drift region, and a first gate 242 is located above the region between the LDMOS source region and the LDMOS drain region, extending from the edge of the LDMOS source region onto the field oxide region 222a. The LDMOS source region, the LDMOS drain region, and the drift region have the same conductivity type.

[0041] In one embodiment of this application, the power device further includes an LDMOS source contact hole 261 disposed on the LDMOS source region. The LDMOS source contact hole 261 penetrates the interlayer dielectric layer 260, and the bottom of the conductive material filled in the LDMOS source contact hole 261 is electrically connected to the LDMOS source region.

[0042] In one embodiment of this application, the power device further includes an LDMOS drain contact hole 263 disposed on the LDMOS drain region. The LDMOS drain contact hole 263 penetrates the interlayer dielectric layer 260, and the bottom of the conductive material filled in the LDMOS drain contact hole 263 is electrically connected to the LDMOS drain region.

[0043] In one embodiment of this application, the LDMOS source region, LDMOS drain region, and drift region are N-type regions, and the LDMOS source region and LDMOS drain region are heavily doped, with a doping concentration greater than that of the drift region. The substrate 210 is a P-type substrate.

[0044] The exemplary LDMOS with its conductive channel disposed in the substrate 210 requires separate processes to fabricate its stepped oxide layer (corresponding to the field oxide region 222a) and drift region field plate (corresponding to the field plate region 232a). For example, the stepped oxide layer is deposited using TEOS (tetraethoxysilane) or HTO (high temperature oxidation) processes, and then the pattern is defined by additional photolithography and etching processes. The drift region field plate is fabricated using a separate polysilicon layer or titanium nitride metal process, and the pattern is also defined by photolithography and etching processes. However, in the integrated circuit manufacturing method of the power device and DSOI device of the embodiments of this application, the fabrication of the LDMOS's field oxide region 222a and field plate region 232a shares the same process steps as the DSOI structure, thus requiring fewer steps and lower manufacturing costs.

[0045] In one embodiment of this application, the DSOI device includes a metal-oxide-semiconductor field-effect transistor (MOSFET), and the second active region includes the source region and the drain region of the MOSFET. The DSOI device also includes a MOSFET source contact hole 277 disposed on the source region of the MOSFET, the MOSFET source contact hole 277 penetrating the interlayer dielectric layer 260, and the bottom of the conductive material filled in the MOSFET source contact hole 277 being electrically connected to the source region of the MOSFET. In another embodiment of this application, the DSOI device also includes a MOSFET drain contact hole 275 disposed on the drain region of the MOSFET, the MOSFET drain contact hole 275 penetrating the interlayer dielectric layer 260, and the bottom of the conductive material filled in the MOSFET drain contact hole 275 being electrically connected to the drain region of the MOSFET.

[0046] In one embodiment of this application, the DSOI device further includes a gate contact hole 279 disposed on the second gate 246, the gate contact hole 279 penetrating the interlayer dielectric layer 260, and the bottom of the conductive material filled in the gate contact hole 279 being electrically connected to the second gate 246.

[0047] In one embodiment of this application, the first gate 242 and the second gate 246 are made of polycrystalline silicon.

[0048] exist Figure 2 In the illustrated embodiment, a gate dielectric layer 244 is further provided at the bottom of the second gate 246. In one embodiment of this application, the gate dielectric layer 244 may comprise conventional dielectric materials such as silicon oxides, nitrides, and oxides of nitride having a dielectric constant from about 4 to about 20 (measured in vacuum), or the gate dielectric layer 244 may comprise a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).

[0049] exist Figure 2 In the embodiment shown, a first sidewall 243 is provided on the side of the first gate 242, and a second sidewall 245 is provided on the side of the second gate 246.

[0050] exist Figure 2 In the illustrated embodiment, the DSOI device further includes a shallow trench isolation structure 250.

[0051] In one embodiment of this application, the DSOI device further includes a first back gate terminal leading out the first SOI region 232b through a contact hole. By applying different back bias voltages to the first SOI region 232b through the first back gate terminal, the threshold voltage of the DSOI device can be modulated, allowing the device to freely switch between high speed / high power consumption and low speed / low power consumption. The back bias voltage can also compensate for changes caused by external factors such as radiation and crosstalk.

[0052] This application provides a method for manufacturing integrated circuits of power devices and DSOI devices, used to manufacture integrated circuits of power devices and DSOI devices as described in any of the above embodiments. The field oxide region 222a and the first buried insulating layer region 222b are formed in the same step, as are the field plate region 232a and the first SOI region 232b. This integrated circuit is fully compatible with conventional DSOI CMOS processes and will not affect the fabrication of other ordinary transistors and back-biased voltage modulated transistors in the same chip.

[0053] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0054] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0055] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An integrated circuit having a power device and a DSOI device, characterized in that, include: The substrate includes the first active region; The first oxide layer is located on the substrate and includes a field oxide region and a first insulating buried layer region, wherein the field oxide region and the first insulating buried layer region are separated from each other; A first gate is located on the substrate and extends from a position adjacent to the field oxide region to the field oxide region; The first semiconductor layer includes a field plate region and a first SOI region, wherein the field plate region and the first SOI region are disposed separately from each other, the field plate region is located on the field oxide region, and the first SOI region is located on the first insulating buried layer region. The second insulating buried layer is located on the first SOI region; A second semiconductor layer is located on the second insulating buried layer, and the second semiconductor layer includes a second active region; The second gate is located on the second semiconductor layer; The first active region, field oxide region, first gate and field plate region constitute the composition structure of the power device, while the first buried insulating layer region, first SOI region, second buried insulating layer, second active region and second gate constitute the composition structure of the DSOI device.

2. The integrated circuit having a power device and a DSOI device according to claim 1, characterized in that, The power device is an LDMOS, the first active region includes an LDMOS source region and an LDMOS drain region, the integrated circuit also includes a drift region located in the substrate, the drift region being at least partially located between the LDMOS source region and the LDMOS drain region, the field oxide region being located on the drift region, the first gate being located above the region between the LDMOS source region and the LDMOS drain region, and extending from the edge of the LDMOS source region to the field oxide region, the LDMOS source region, the LDMOS drain region and the drift region having the same conductivity type.

3. The integrated circuit having a power device and a DSOI device according to claim 2, characterized in that, The integrated circuit has a field plate contact hole, an LDMOS source contact hole, and an LDMOS drain contact hole. The conductive material filled in the field plate contact hole is electrically connected to the field plate region. The conductive material filled in the LDMOS source contact hole is electrically connected to the LDMOS source region. The conductive material filled in the LDMOS drain contact hole is electrically connected to the LDMOS drain region.

4. The integrated circuit having a power device and a DSOI device according to claim 1, characterized in that, The field oxygen region and the first insulating buried layer region are manufactured in the same step, and the field plate region and the first SOI region are manufactured in the same step.

5. The integrated circuit having a power device and a DSOI device according to claim 1, characterized in that, The thickness of the field oxygen region and the first insulating buried layer region is the same, and the thickness of the field plate region and the first SOI region is the same.

6. The integrated circuit having a power device and a DSOI device according to claim 1, characterized in that, The double insulator-on-silicon device includes a metal-oxide-semiconductor field-effect transistor, and the second active region includes a MOS transistor source region and a MOS transistor drain region; the second gate, the MOS transistor source region, and the MOS transistor drain region constitute the structure of the metal-oxide-semiconductor field-effect transistor. The integrated circuit has a gate contact hole, a MOS source contact hole, and a MOS drain contact hole. The conductive material filled in the gate contact hole is electrically connected to the second gate. The conductive material filled in the MOS source contact hole is electrically connected to the MOS source region. The conductive material filled in the MOS drain contact hole is electrically connected to the MOS drain region.

7. The integrated circuit having a power device and a DSOI device according to claim 1, characterized in that, The thickness of the substrate is greater than 700 micrometers.

8. The integrated circuit having a power device and a DSOI device according to claim 1, characterized in that, The thickness of the first oxide layer is 1000~2000 Å.

9. The integrated circuit having a power device and a DSOI device according to claim 1, characterized in that, The thickness of the first semiconductor layer is 1000~2000 Å.

10. A method for manufacturing an integrated circuit having a power device and a DSOI device as described in claim 1, characterized in that, The field oxygen region and the first insulating buried layer region are manufactured in the same step, and the field plate region and the first SOI region are manufactured in the same step.

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