Method for manufacturing tgv interposer-copper paste interconnect-high thermal conductivity insulation material of three-dimensional integrated circuit package

Abstract

The application discloses a TGV interlayer-copper paste interconnection-high thermal conductivity and low loss insulation material collaborative packaging structure for three-dimensional integrated circuit packaging and a preparation method thereof, and belongs to the technical field of advanced electronic packaging materials. The structure comprises a TGV glass interlayer with low dielectric and adjustable thermal expansion coefficient, a high-uniformity metal interconnection structure formed by filling and sintering of functional copper paste, and a high-thermal-conductivity and low-loss insulation packaging layer. Through collaborative design of the interlayer material, the copper paste interconnection material and the insulation packaging material, excellent high-frequency electrical performance, thermal management performance and structural reliability can be realized. The application has simplified process and controllable cost, and is suitable for three-dimensional packaging application scenarios such as AI accelerators, high-performance computing, radio frequency front ends and heterogeneous integration.

Description

Technical Field

[0001] This invention belongs to the field of advanced packaging technology for integrated circuits and electronic packaging materials, specifically relating to a synergistic material system suitable for three-dimensional integrated circuit packaging and its preparation method. Background Technology

[0002] As integrated circuits in the Moore's Law era have evolved towards higher computing power, higher bandwidth, lower latency, and miniaturization, 3D integrated packaging technology has gradually become an important way to overcome chip performance bottlenecks. Through chip stacking, vertical interconnection, and high-density wiring, interconnection paths can be significantly shortened, signal transmission efficiency can be improved, and system power consumption can be reduced. Therefore, it shows broad application prospects in AI chips, high-performance computing, memory integration, and radio frequency communication.

[0003] However, current 3D integrated circuit packaging still faces the following key material challenges:

[0004] Inadequate performance of interposer materials: Existing silicon interposers are costly and have large parasitic capacitances, easily causing signal loss in high-frequency applications; organic interposers suffer from thermal expansion mismatch, insufficient dimensional stability, and limited high-frequency adaptability. Insufficient uniformity and formability of metal interconnects: In high aspect ratio vias or micro-interconnect structures, traditional electroplating copper processes are complex, costly, and difficult to control voids, while conventional copper pastes are prone to uneven sintering shrinkage, high porosity, and discontinuous conductive networks, affecting interconnect resistance and long-term reliability. Insulating encapsulation materials struggle to balance high thermal conductivity and low dielectric loss. Existing encapsulation insulating materials often suffer from low thermal conductivity, high interfacial thermal resistance, or high high-frequency loss, making it difficult to simultaneously meet the requirements of 3D packaging systems in terms of thermal management and high-speed electrical signal transmission.

[0005] Therefore, it is necessary to develop a collaborative material system for three-dimensional integrated circuit packaging, which can achieve integrated design in three key dimensions: interposer, metal interconnect and insulating packaging material, thereby improving the electrical, thermal and mechanical coupling performance and service reliability of the package. Summary of the Invention

[0006] The purpose of this invention is to provide a TGV interposer-copper paste interconnect-high thermal conductivity and low loss insulating material co-packaging structure and its preparation method for three-dimensional integrated circuit packaging, so as to solve the problems in the prior art that it is difficult to balance the dielectric properties and thermal matching of the interposer, the poor uniformity of the metal interconnect, and the difficulty in unifying the thermal conductivity and low loss of the packaging insulating material.

[0007] TGV interposer substrate; copper paste sintered metal interconnect structure disposed inside and on the surface of the TGV interposer substrate; high thermal conductivity and low loss insulating encapsulation layer covering the surface of the interposer and the periphery of the interconnect area. Wherein: the TGV interposer substrate is a low dielectric glass substrate material, and its coefficient of thermal expansion is matched to that of the chip / redistribution layer through component design or composite filler control;

[0008] The copper paste sintered metal interconnect structure is formed by filling glass vias with functional copper paste containing micron-nano-scale composite copper powder, low-temperature sintering aids, and a rheology modifier system, followed by segmented degreasing and densification sintering. The high thermal conductivity and low loss insulating encapsulation layer is a polymer / inorganic filler composite system, possessing both high thermal conductivity, low dielectric constant, and low dielectric loss. The TGV interposer substrate is selected from one or more of borosilicate glass, quartz glass, or their composite modified materials.

[0009] The present invention has the following advantages: the dielectric constant of the TGV interlayer is 3.5~6.0 (at 10 GHz), the dielectric loss tangent is less than 0.01, the coefficient of thermal expansion is 3~10 ppm / ℃, the diameter of the glass through-hole is 10~200 μm, and the depth-to-diameter ratio is 1:1~20:1.

[0010] The copper paste of this invention comprises the following components by mass percentage: 70%~92% copper powder; 0.1%~8% low-temperature sintering aid; 5%~20% organic carrier; and 0.1%~5% dispersant, wetting agent, and rheology modifier. In this invention, it is composed of micron-sized spherical copper powder and nano-sized copper powder in a mass ratio of (3~20):1 to achieve high filling density and low sintering temperature. The low-temperature sintering aid includes one or more of formate, organic amine complexes, trace silver sintering aids, copper precursors, or reducing organic acids. The copper paste is sintered in nitrogen, formic acid atmosphere, or inert / reducing composite atmosphere at a sintering temperature of 180~350℃.

[0011] The high thermal conductivity, low loss insulating encapsulation layer comprises a resin matrix and an inorganic thermally conductive filler; the resin matrix is ​​one or more selected from epoxy resin, benzocyclobutene, polyimide, cyanate ester resin, and siloxane-modified resin; the inorganic thermally conductive filler is one or more selected from boron nitride, aluminum nitride, spherical alumina, silicon nitride, or magnesium oxide. The insulating encapsulation layer has a thermal conductivity of 1~8 W / (m·K), a dielectric constant of 2.5~4.5, and a dielectric loss tangent of less than 0.008 (1~10 GHz).

[0012] This invention also provides a method for preparing the above-mentioned co-encapsulation structure, comprising the following steps:

[0013] 1) TGV Intermediate Layer Preparation: Select a low-dielectric glass substrate and form a through-hole array through laser drilling, wet etching, sandblasting, ultrasonic-assisted processing or photosensitive forming process; then clean, roughen and activate the inner wall of the through-hole, and deposit a barrier / seed layer on the hole wall.

[0014] 2) Copper paste preparation: Micron copper powder, nano copper powder, sintering aid, organic carrier, dispersant and rheology modifier are mixed in proportion, and ball milled, vacuum degassing and homogenized to obtain a low-temperature sintering copper paste suitable for TGV filling.

[0015] 3) TGV via filling and preforming: The copper paste is filled into the TGV vias and surface interconnect areas using vacuum-assisted screen printing, scraping filling, pressure injection, jet deposition or stencil transfer processes; then, graded pre-baking is performed to allow the organic components to partially volatilize and form an initial conductive framework.

[0016] 4) Sintering densification: The intermediate layer filled with copper paste is placed in a protective atmosphere for segmented heating degreasing and sintering treatment, which causes the copper particles to neck together, densify, and build a continuous conductive network, forming a metal interconnect structure with low porosity and high uniformity.

[0017] 5) Surface planarization and redistribution adaptation: The sintered copper interconnect surface is ground, polished or chemically and mechanically planarized to reduce surface roughness and form a surface structure that is compatible with subsequent redistribution layers and chip bonding.

[0018] 6) Construction of high thermal conductivity and low loss insulating encapsulation layer: Coating, molding, laminating or potting high thermal conductivity and low loss insulating material on the periphery of the interconnect or in the interlayer gap area, and curing it to form a stable interface bond with the interlayer and metal interconnect.

[0019] 7) Subsequent packaging integration: Integrate the chip, redistribution layer, solder joints or other functional layers with the above co-packaging structure to form a high-frequency, high-density, and high-reliability packaged device suitable for three-dimensional integrated circuits.

[0020] Compared with existing technologies, this invention has at least the following advantages: The use of a low-dielectric TGV glass interlayer significantly reduces parasitic losses and crosstalk during high-frequency signal transmission, improving high-speed interconnect performance and making it suitable for high-frequency applications such as AI accelerators and RF front-ends; by controlling the composition of the glass substrate and introducing composite fillers, the thermal expansion coefficient of the interlayer can be adjusted within a wide range, thereby reducing thermal stress mismatch between the interlayer and the chip, metal interconnects, and packaging layers, and improving thermal cycling reliability; the use of functionalized copper paste instead of complex electroplating processes for TGV filling reduces process steps and manufacturing costs, and achieves better filling density and sintering uniformity through micron / nano composite particle size design; this invention can be widely applied in fields such as three-dimensional stacked chips, heterogeneous integration, high-bandwidth storage, high-performance computing packaging, millimeter-wave / RF modules, and high-power-density electronic devices. Attached Figure Description

[0021] It should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention. The technical solutions in the embodiments of the present invention are clearly and completely described. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0022] Example 1

[0023] 1) Weigh the glass powder precisely according to the formula, and dry the raw materials in a 120℃ oven for 2 hours to remove moisture.

[0024] 2) After drying, the raw materials are put into a mixer and grinding balls are added. The mixture is then mixed for 3 hours to obtain a uniform batch. The batch is then placed in a platinum crucible and placed in a silicon molybdenum rod high-temperature furnace. The temperature is raised to 1000℃ and held for 1 hour to decompose the borosilicate.

[0025] 3) After melting, let it stand for 1.5 hours to clarify, allowing the bubbles to rise and escape, resulting in a clear and transparent glass melt. Quickly pour the glass melt into a preheated 400℃ cast iron mold to form the shape, then immediately transfer it to a muffle furnace and anneal at 620℃ for 3 hours, before cooling to room temperature.

[0026] 4) The annealed glass block was cut, ground, and polished to prepare a 50 mm × 50 mm × 0.5 mm substrate with a surface roughness Ra < 1 nm. A picosecond laser (wavelength 1030 nm, pulse energy 8 μJ, repetition frequency 200 kHz) was used to scan and modify the substrate according to a preset pattern. The substrate was then ultrasonically etched in 10% hydrofluoric acid at 30°C for 30 minutes, followed by cleaning and drying to obtain through-holes.

[0027] 5) A copper paste suitable for TGV filling was obtained by mixing 82% spherical micron copper powder, 6% nano copper powder, 2% formate sintering aid, 8% organic carrier, and 2% dispersant and thixotropic agent, followed by ball milling for 4 h and vacuum degassing for 30 min. The copper paste was injected into the TGV holes obtained in Example 1 under vacuum-assisted conditions, and the slurry was fully filled into the through holes with the aid of a scraper. Subsequently, it was pre-dried at 80°C for 20 min and then pre-dried again at 150°C for 30 min to remove some organic components and fix the morphology of the slurry.

[0028] 6) Using epoxy-cyanate composite resin as the matrix and lamellar boron nitride and spherical alumina as composite fillers, with a total filler content of 65 wt%, the resin was dispersed at high speed and degassed before being coated onto the surface and surrounding voids of a TGV substrate containing copper interconnect structures. It was pre-cured at 120℃ for 30 min and then cured at 180℃ for 2 h to obtain a dense insulating encapsulation layer. Tests showed that the encapsulation layer had a thermal conductivity of 3.2 W / (m·K), a dielectric constant of 3.4, and a dielectric loss tangent of less than 0.006.

[0029] Example 2

[0030] 1) Weigh the glass powder precisely according to the formula, and dry the raw materials in a 120℃ oven for 2 hours to remove moisture.

[0031] 2) After drying, the raw materials are put into a mixer and grinding balls are added. The mixture is then mixed for 3 hours to obtain a uniform batch. The batch is then placed in a platinum crucible and placed in a silicon molybdenum rod high-temperature furnace. The temperature is raised to 1000℃ and held for 1 hour to decompose the borosilicate.

[0032] 3) After melting, let it stand for 1.5 hours to clarify, allowing the bubbles to rise and escape, resulting in a clear and transparent glass melt. Quickly pour the glass melt into a preheated 400℃ cast iron mold to form the shape, then immediately transfer it to a muffle furnace and anneal at 620℃ for 3 hours, before cooling to room temperature.

[0033] 4) A 500 μm thick low-dielectric borosilicate glass substrate was selected, and a TGV array with a hole diameter of 50 μm and a hole spacing of 120 μm was formed using ultraviolet laser drilling. After the substrate was cleaned sequentially with deionized water, ethanol, and a weak alkaline solution, the hole walls were roughened and activated. A Ti / Cu barrier-seed layer was then deposited on the hole wall surface to improve the subsequent copper paste adhesion and interfacial bonding strength.

[0034] 5) A copper paste suitable for TGV filling was obtained by mixing 82% spherical micron copper powder, 6% nano copper powder, 2% formate sintering aid, 8% organic carrier, and 2% dispersant and thixotropic agent, followed by ball milling for 4 h and vacuum degassing for 30 min. The copper paste was injected into the TGV holes obtained in Example 1 under vacuum-assisted conditions, and the slurry was fully filled into the through holes with the aid of a scraper. Subsequently, it was pre-dried at 80°C for 20 min and then pre-dried again at 150°C for 30 min to remove some organic components and fix the morphology of the slurry.

[0035] 6) Using epoxy-cyanate composite resin as the matrix and lamellar boron nitride and spherical alumina as composite fillers, with a total filler content of 65 wt%, the resin was dispersed at high speed and degassed before being coated onto the surface and surrounding voids of a TGV substrate containing copper interconnect structures. It was pre-cured at 120℃ for 30 min and then cured at 180℃ for 2 h to obtain a dense insulating encapsulation layer. The resulting glass interposer has a dielectric constant of approximately 4.6 at 10 GHz and a dielectric loss tangent of less than 0.008, exhibiting good high-frequency transmission capability.

Claims

1. A collaborative packaging structure for three-dimensional integrated circuit packaging, characterized in that: It includes a TGV interposer substrate, a copper paste sintered metal interconnect structure disposed inside and on the surface of the TGV interposer substrate, and a high thermal conductivity, low loss insulating encapsulation layer disposed on the surface of the TGV interposer substrate and / or around the interconnect structure.

2. The collaborative packaging structure according to claim 1, characterized in that... The dielectric constant of the TGV interposer substrate of this invention is 3.5~6.0, the dielectric loss tangent is less than 0.01, and the coefficient of thermal expansion is 3~10 ppm / ℃.

3. A TGV interposer-copper paste interconnect-high thermal conductivity low loss insulating material for three-dimensional integrated circuit packaging, wherein the glass material is selected from one or more of borosilicate glass, aluminosilicate glass, quartz glass and their composite modified materials.

4. The collaborative packaging structure according to claim 1, characterized in that: The copper paste contains 70% to 92% copper powder, 0.1% to 8% sintering aid, 5% to 20% organic carrier, and 0.1% to 5% dispersant and rheology modifier.

5. The collaborative packaging structure according to claim 1, characterized in that... The resin matrix of the high thermal conductivity and low loss insulating encapsulation layer is selected from one or more of epoxy resin, polyimide, benzocyclobutene, cyanate ester resin, and siloxane modified resin.

6. A method for preparing the co-encapsulation structure according to claim 1, comprising the following steps: 1) Prepare a low-dielectric glass interlayer with a through-hole array, and clean, roughen, activate and deposit a barrier / seed layer on the hole walls; 2) Prepare functional copper paste containing micron / nano composite copper powder; 3) Copper paste is filled into the TGV vias and interconnect areas using a vacuum-assisted filling method and pre-baked to form the structure; then, in a protective or reducing atmosphere, it is degreased and sintered in stages to densify the copper paste and form a metal interconnect structure. 4) Planarize the interconnect surfaces; 5) Construct a high thermal conductivity, low loss insulating encapsulation layer on the surface of the interposer and / or the periphery of the interconnect and cure it; use the resulting structure for three-dimensional integrated circuit packaging and assembly.