Dwa algorithm implementation circuit and analog-to-digital converter

Abstract

This application provides a DWA algorithm implementation circuit and an analog-to-digital converter. The DWA algorithm implementation circuit includes a shifter and a combinational logic circuit. The shifter's data input terminal receives thermometer codes output by a quantizer based on a first clock control signal; the shifter's data output terminal is connected to the input terminal of the combinational logic circuit and serves as the output terminal of the DWA algorithm implementation circuit; the combinational logic circuit concatenates the thermometer codes output by the shifter and performs combinational logic operations on the concatenated thermometer codes to generate a shift indication signal for the shifter; the shifter performs shift operations based on the shift indication signal. This application significantly simplifies the circuit structure, saves circuit area, and reduces circuit cost; simultaneously, it improves circuit speed and increases its flexibility.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a DWA algorithm implementation circuit and an analog-to-digital converter. Background Technology

[0002] In mixed-signal integrated circuits, the analog-to-digital converter (ADC) plays a crucial role as the bridge connecting the analog and digital worlds. Among the many types of ADCs, the Sigma-Delta ADC (Σ-Δ ADC) significantly improves resolution due to its high oversampling rate and noise shaping technology, and is widely used in high-precision fields such as digital audio and instrumentation. However, to achieve a high signal-to-noise ratio (SNR), it is necessary to increase the order of the modulator or the bit depth of the quantizer. While a high-order 1-bit quantizer avoids nonlinearity, its stability issues can severely affect system stability and the range of the input signal, thus limiting its effectiveness. To overcome the drawbacks of high-order structures, a multi-stage noise-shaping (MASH) structure can be used. This structure achieves the effect of a higher-order quantizer through the cascading of lower-order shaping modulators, avoiding stability problems. However, it also introduces matching issues between stages, easily leading to noise leakage between interconnected stages and affecting the overall SNR, thus still presenting drawbacks. Compared to higher-order systems, modulators employing multi-bit quantizers avoid the aforementioned problems, effectively improving the signal-to-noise ratio (SNR) and providing a wider input signal range. In multi-bit quantizer structures, mismatch in the multi-bit DAC (Digital-to-Analog Converter) often introduces nonlinearity, causing harmonic distortion and reducing the overall linearity of the modulator. To reduce the nonlinearity caused by multi-bit DAC mismatch, various Dynamic Element Matching (DEM) algorithms are typically used to dynamically distribute the mismatch. Shaping converts the distortion caused by nonlinearity into white noise, pushing it to higher frequencies to maintain the SNR of the multi-bit quantizer. Common DEM methods include Data Weighted Averaging (DWA), Randomization, Clocked Averaging (CLA), and Individual Level Averaging (ILA). Among these, DWA is the most popular and convenient algorithm. This algorithm processes thermometer codes and cyclically draws from the capacitors in the DAC capacitor array to average the error, achieving dynamic component matching. Thermometer codes are composed of 0s and 1s, encoded in a manner such as 1s first and 0s last, where the numerical value of the thermometer code equals the number of 1s in the thermometer code.

[0003] Specifically, taking a three-bit quantizer as an example, the five outputs of the quantizer are {6, 5, 3, 0, 2}. For example, output 6 represents the first 6 bits of the eight-bit thermometer code being 1, which sequentially drives the capacitors in the DAC capacitor array to realize the feedback of the output signal in the modulator. Figure 1 This paper reveals the schematic diagram of a traditional DWA algorithm module for capacitor selection. (For example...) Figure 1 As shown, the darker areas represent the selected DAC capacitors. Assuming the DWA algorithm module has just been reset, the first input selects capacitors starting from the first capacitor in the DAC capacitor array. Therefore, the first input value 6 selects DAC capacitors {1, 2, 3, 4, 5, 6}. The second input value selects capacitors starting from the end of the first input, so the second input value 5 selects capacitors {7, 8, 1, 2, 3}. Similarly, the third input value 3 selects DAC capacitors {4, 5, 6}. The DWA algorithm module selects capacitors in the DAC capacitor array sequentially according to the input values ​​to ensure that each DAC capacitor is selected approximately the same number of times, thus summing the errors and bringing the overall error close to zero.

[0004] However, the traditional DWA algorithm is relatively complex to implement and occupies a large circuit area. Summary of the Invention

[0005] The purpose of this application is to provide a DWA algorithm implementation circuit and an analog-to-digital converter that can solve at least one of the technical problems mentioned in the prior art.

[0006] One aspect of this application provides a DWA algorithm implementation circuit. The DWA algorithm implementation circuit includes a shifter and a combinational logic circuit. The data input terminal of the shifter is used to receive thermometer codes output by a quantizer based on a first clock control signal; the data output terminal of the shifter is connected to the input terminal of the combinational logic circuit and serves as the output terminal of the DWA algorithm implementation circuit; the combinational logic circuit is used to concatenate the thermometer codes output by the shifter end-to-end and perform combinational logic operations on the concatenated thermometer codes to generate a shift indication signal for the shifter; the shifter is used to perform a shift operation based on the shift indication signal.

[0007] Furthermore, the combinational logic circuit is used to identify the adjacent positions of the 1 code and the 0 code by performing combinational logic operations on two adjacent bits in the thermometer code when the thermometer code is not all 1 codes or not all 0 codes, so as to obtain the position where the 1 code ends; the position where the 1 code ends is used as the number of bits to be shifted in the thermometer code output by the quantizer next time, and the shift indication signal is output to the shifter.

[0008] Furthermore, the thermometer code has M bits, and the combinational logic circuit includes M first logic circuits. The i-th first logic circuit is used to perform a logical AND operation on the i-th bit of the thermometer code connected end to end with the inversion of the next bit, and output the i-th bit shift indicator signal, where i ranges from 1 to M. The combinational logic circuit is used to determine the end position of the 1-bit code based on the M-bit shift indicator signals output by the M first logic circuits when the thermometer code is not all 1s or not all 0s.

[0009] Furthermore, the combinational logic circuit is used to identify the adjacent positions of 1 code and 0 code based on whether the M shift indication signals output by the M first logic circuits are 0 or 1, and to take the number of bits corresponding to the shift indication signal of 1 in the adjacent positions as the end position of 1 code.

[0010] Furthermore, the combinational logic circuit is also used to directly set the Mth shift indication signal output by the Mth first logic circuit to 1 when the thermometer code is all 1s or all 0s.

[0011] Furthermore, the combinational logic circuit also includes a second logic circuit, wherein the second logic circuit is used to perform logical processing on the output of the Mth first logic circuit and the M-bit code of the thermometer code, so as to update the Mth shift indication signal corresponding to the output of the Mth first logic circuit according to the state of the M-bit code of the thermometer code, and the combinational logic circuit is used to take the Mth shift indication signal updated by the second logic circuit as the final Mth shift indication signal.

[0012] Furthermore, the second logic circuit includes an AND gate, a NOR gate, and an OR gate, wherein the AND gate is used to perform a logical AND on the M-bit code of the thermometer code; the NOR gate is used to perform a logical OR on the M-bit code of the thermometer code; the three input terminals of the OR gate are respectively connected to the output terminal of the M-th first logic circuit, the output terminal of the AND gate, and the output terminal of the NOR gate, and the output terminal of the OR gate serves as the output terminal of the second logic circuit, used to output the updated M-th bit shift indication signal.

[0013] Furthermore, the DWA algorithm implementation circuit also includes a flip-flop, wherein the data terminal of the flip-flop is connected to the output terminal of the combinational logic circuit, the clock control terminal of the flip-flop is used to receive a second clock control signal, and the output terminal of the flip-flop is connected to the control terminal of the shifter; the flip-flop is used to control whether to transmit the signal from the data terminal of the flip-flop to the output terminal of the flip-flop according to the second clock control signal.

[0014] Furthermore, the second clock control signal lags behind the first clock control signal by a predetermined phase difference.

[0015] Furthermore, the thermometer code has M bits, the shift indication signal includes M bits, and the flip-flop is also used to receive a reset signal. The reset signal is used to reset the output of the flip-flop to a shift indication signal where only the Mth bit is 1 after the DWA algorithm implementation circuit is powered on and before the rising edge of the second clock control signal arrives.

[0016] Furthermore, the shifter includes M×M controllable switches, and the shifter has M data input terminals and M data output terminals. The controllable switches in the i-th row of each column are controlled by the i-th shift indication signal output by the combinational logic circuit, where i ranges from 1 to M. The input terminals of the controllable switches in the j-th column of each row are connected to the j-th data input terminal of the shifter, where j ranges from 1 to M. The output terminals of the controllable switches in the j-th column of the i-th row are connected to the k-th data output terminal of the shifter, where k = j + i when j + i ≤ M, and k = j + iM when j + i > M.

[0017] Furthermore, when the shift indicator signal of the i-th row is 1, the controllable switch of the i-th row is closed.

[0018] Another aspect of this application provides an analog-to-digital converter (ADC). The ADC includes a modulator, a quantizer, a DWA algorithm implementation circuit as described above, and a capacitor array. The input terminal of the modulator is used to receive an analog input signal; the output terminal of the modulator is connected to the input terminal of the quantizer; the output terminal of the quantizer is connected to the input terminal of the DWA algorithm implementation circuit; the output terminal of the DWA algorithm implementation circuit is connected to one end of the capacitor array; and the other end of the capacitor array is connected to the feedback terminal of the modulator.

[0019] The DWA algorithm implementation circuit and analog-to-digital converter having the DWA algorithm implementation circuit in one or more embodiments of this application, by adding combinational logic circuit, allows the shifter to output the thermometer code to the combinational logic circuit. The combinational logic circuit can directly perform combinational logic operations based on the thermometer code output by the shifter to obtain the shift indication signal of the next thermometer code to be shifted from the quantizer, and output the shift indication signal to the shifter for shifting operation, without the need for decoders, adders, and pointer registers, thereby greatly simplifying the circuit structure, saving circuit area, reducing design complexity, and significantly reducing circuit cost; at the same time, it can improve the speed of the circuit and increase its flexibility. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of selecting capacitors for a traditional DWA algorithm module.

[0021] Figure 2 This is a schematic diagram of the circuit structure for implementing a DWA algorithm in related technologies.

[0022] Figure 3 This is a schematic diagram of the structure of a DWA algorithm implementation circuit according to an embodiment of this application.

[0023] Figure 4 This is a schematic diagram of the structure of the first logic circuit in the combinational logic circuit of this application.

[0024] Figure 5 This is a schematic diagram of the structure of the second logic circuit in the combinational logic circuit of this application.

[0025] Figure 6 This is a timing diagram of the reset signal, the first clock control signal, and the second clock control signal according to an embodiment of this application.

[0026] Figure 7 This is a schematic diagram of the structure of a shifter according to an embodiment of this application.

[0027] Figure 8 This is a schematic diagram of the structure of an analog-to-digital converter according to an embodiment of this application. Detailed Implementation

[0028] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses consistent with some aspects of this application as detailed in the appended claims.

[0029] The general implementation of the DWA algorithm is similar to a barrel shifter. It needs to determine the next pointer position, i.e. the starting position for the next selection of the DAC capacitor, based on the current starting position of the selected DAC capacitor (i.e., the pointer position) and the magnitude of the current input value.

[0030] Figure 2 A schematic diagram of a DWA algorithm implementation circuit 200 in related technologies is shown. For example... Figure 2 As shown, the DWA algorithm implementation circuit 200 consists of a thermometer code-binary code decoder 220, an adder 230, a pointer register 240, and a shifter 210.

[0031] The decoder 220 converts the thermometer code output by the quantizer into binary code so that the adder 230 can perform calculations to obtain the position of the next pointer.

[0032] Adder 230 is a binary adder used to add the current pointer value to the output (binary) of the quantizer to calculate the starting position of the capacitor in the DAC capacitor array 100 for the next selection.

[0033] The pointer register 240 is used to pass the calculated pointer value and output the pointer value to the shifter 210 for shifting.

[0034] However, the DWA algorithm implementation circuit 200 in the aforementioned related technologies has some drawbacks:

[0035] First, the DWA algorithm implementation circuit 200 uses modules such as decoder 220, adder 230, and pointer register 240, which requires certain resources, has a large circuit area, and has many circuit modules, making it relatively complex.

[0036] Second, the transmission between modules involves adder 230 and pointer register 240, resulting in a certain delay in the signal path, which is not conducive to high-speed applications.

[0037] Third, when shifting the quantizer output, it is necessary to first decode it, convert it into binary, and then shift the thermometer code according to a binary value after the addition is completed. This causes redundancy and complexity in the design, resulting in an increase in circuit area.

[0038] In view of this, this application provides an improved DWA algorithm implementation circuit, which can solve at least one of the technical problems mentioned in the above-mentioned related technologies.

[0039] The DWA algorithm implementation circuit and the analog-to-digital converter having the DWA algorithm implementation circuit of this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementations can be combined with each other.

[0040] Figure 3 A schematic diagram of the structure of a DWA algorithm implementation circuit 300 according to an embodiment of this application is shown. Figure 3 As shown, a DWA algorithm implementation circuit 300 of one embodiment of this application includes a shifter 310 and a combinational logic circuit 320.

[0041] The data input terminal of shifter 310 can be used to receive the thermometer code output by quantizer 400 based on the first clock control signal; the data output terminal of shifter 310 is connected to the input terminal of combinational logic circuit 320 and serves as the output terminal of DWA algorithm implementation circuit 300.

[0042] The combinational logic circuit 320 can be used to connect the thermometer codes output by the shifter 310 end to end, and perform combinational logic operations on the connected thermometer codes to generate a shift indication signal Index to the shifter 310.

[0043] The shifter 310 can perform corresponding shift operations based on the shift indication signal Index output by the combinational logic circuit 320.

[0044] In this application, the thermometer code is represented using a 1-first, 0-last encoding method, and the shifting of shifter 310 is illustrated by a cyclic right shift. However, this application is not limited to this. The DWA algorithm implementation circuit 300 of this application is also applicable to the implementation of a cyclic left shift of a thermometer code encoded with 0-first, 1-last encoding. These equivalent transformations do not change the inventive essence of this application and are all covered within the protection scope of this application.

[0045] The quantizer 400 outputs a thermometer code of M bits. When the quantizer 400 has N bits, the number of bits in the output thermometer code is M = 2. N In the embodiments illustrated in this application, a 3-bit quantizer will be used as an example, with the quantizer 400 outputting an 8-bit thermometer code. However, this application does not limit the scope of the application.

[0046] When the thermometer code is not entirely composed of 1s or 0s, based on the characteristic that 1s and 0s tend to occur in clusters within the thermometer code (also known as unary code), the adjacent positions of 1s and 0s can be quickly obtained by performing combinational logic operations on adjacent bits. In the circuit implementing the DWA algorithm to select capacitors in the subsequent DAC capacitor array 100, the thermometer code is connected end-to-end, treated as a barrel shape, and shifted, as shown above. Figure 1 As shown, each capacitor in the DAC capacitor array 100 can be selected sequentially. Combining the characteristics of the thermometer code and barrel shift, the combinational logic circuit 320 of this application can identify the adjacent positions of the 1 code and the 0 code by performing combinational logic operations on the two adjacent bits in the thermometer code when the thermometer code is not all 1 codes or not all 0 codes, thus obtaining the position of the end of the 1 code; the position of the end of the 1 code is used as the number of bits to be shifted in the next output of the thermometer code by the quantizer 400, and the shift indication signal Index is output to the shifter 310.

[0047] The temperature code output by the quantizer 400 is M bits. Correspondingly, the shifter 310 is also an M-bit shifter, and the shift indication signal Index output by the combinational logic circuit 320 is also M bits. The shifter 310 can perform corresponding shift operations according to the M-bit shift indication signal Index.

[0048] In each output of the combinational logic circuit 320, only one shift indicator signal Index is 1, while the rest are 0. The number of bits where the shift indicator signal Index is 1 indicates the number of bits that the quantizer 400 needs to shift in the next output of the thermometer code. For example, when M=8, if the second shift indicator signal is 1 (i.e., Index2=1) and the rest are 0, it means that the quantizer 400 needs to shift the thermometer code to the right by 2 bits in the next output.

[0049] Figure 4 A schematic diagram of the structure of the first logic circuit 321 in the combinational logic circuit 320 of this application is shown. For example... Figure 4 As shown, in some embodiments, the combinational logic circuit 320 of this application includes M first logic circuits 321. The i-th first logic circuit 321 is used to perform a logical AND operation on the i-th bit Ci of the thermometer code connected end to end with the inverted bit of the next bit, and output the i-th bit shift indication signal Index i, where i ranges from 1 to M.

[0050] For example, taking M=8 as an example, the first logic circuit 3211 performs a logical AND operation on the inverted values ​​of the first bit code C1 and the second bit code C2 in the thermometer code, and outputs the first bit shift indicator signal Index1; the second logic circuit 3212 performs a logical AND operation on the inverted values ​​of the second bit code C2 and the third bit code C3 in the thermometer code, and outputs the second bit shift indicator signal Index2; ...; the seventh logic circuit 3217 performs a logical AND operation on the inverted values ​​of the seventh bit code C7 and the eighth bit code C8 in the thermometer code, and outputs the seventh bit shift indicator signal Index7; the eighth logic circuit 3218 performs a logical AND operation on the inverted values ​​of the eighth bit code C8 and the first bit code C1 in the thermometer code, and outputs the eighth bit shift indicator signal Index8.

[0051] When the thermometer code is not all 1s or not all 0s, the combinational logic circuit 320 can determine the end position of the 1 code based on the M shift indication signals Index output by the M first logic circuits 321.

[0052] In some embodiments, the combinational logic circuit 320 can identify the positions adjacent to the 1 code and the 0 code based on whether the M shift indication signals Index output by the M first logic circuits 321 are 0 or 1, and take the number of bits corresponding to the shift indication signal Index being 1 in the adjacent positions as the end position of the 1 code.

[0053] For example, the outputs of quantizer 400 are {6, 5, 3, 0, 2} in sequence. The first output is 6, and the corresponding thermometer code is {1, 1, 1, 1, 1, 1, 0, 0}. According to the combinational logic circuit 320 of this application, the combinational logic operation can be performed to obtain Index[1:8] = {0, 0, 0, 0, 0, 1, 0, 0}. Only the shift indicator signal Index6 of the 6th bit is 1, that is, Index6 = 1, indicating that the next output of quantizer 400 will be shifted 6 bits to the right.

[0054] Considering that when the quantizer 400 outputs at its maximum and minimum values, corresponding to all 1 codes and all 0 codes respectively, since there are no adjacent 1 codes and 0 codes, all shift indicator signals Index are all 0, which is not allowed. However, all 1 codes and all 0 codes do not require shifting. Therefore, when the thermometer code is all 1 codes or all 0 codes, the combinational logic circuit 320 of this application can directly set the Mth shift indicator signal Index corresponding to the Mth first logic circuit 321 to 1. For example, for an 8-bit system, Index8 = 1.

[0055] In order to enable the combinational logic circuit 320 to directly set the Mth shift indicator signal Index of the Mth first logic circuit 321 to 1 when the thermometer code is all 1s or all 0s, the combinational logic circuit 320 of this application may further include a second logic circuit 322.

[0056] Figure 5 A schematic diagram of the structure of the second logic circuit 322 in the combinational logic circuit 320 of this application is shown. For example... Figure 5 As shown, the second logic circuit 322 can further process the output of the Mth first logic circuit 321 and the M-bit code of the thermometer code, thereby updating the Mth shift indicator signal Index of the corresponding output of the Mth first logic circuit 321 according to the status of the M-bit code of the thermometer code. When the thermometer code is all 1s or all 0s, the second logic circuit 322 can be used to set the Mth shift indicator signal Index to 1.

[0057] The combinational logic circuit 320 can use the Mth shift indicator signal Index' updated by the second logic circuit 322 as the final Mth shift indicator signal Index, thereby avoiding the situation where the Mth shift indicator signal Index output by the combinational logic circuit 320 is all 0 when the thermometer code is all 1 or all 0.

[0058] In some embodiments, the second logic circuit 322 of this application includes an AND gate 3221, a NOR gate 3222, and an OR gate 3223.

[0059] AND gate 3221 can perform a logical AND operation on the M bits of the thermometer code. For example, when M=8, the eight inputs of AND gate 3221 respectively receive the first bit C1 to the eighth bit C8 in the thermometer code.

[0060] The NOR gate 3222 can perform a logical OR-NOT operation on the M bits of the thermometer code. For example, when M=8, the eight inputs of the NOR gate 3222 will receive the first bit C1 to the eighth bit C8 of the thermometer code respectively.

[0061] The three input terminals of OR gate 3223 are respectively connected to the output terminal of the Mth first logic circuit 321, the output terminal of AND gate 3221, and the output terminal of NOR gate 3222. The output terminal of OR gate 3223 serves as the output terminal of the second logic circuit 322, used to output the updated Mth shift indication signal Index'.

[0062] For example, taking an 8-bit system, when the thermometer code is all 1s, the output of the 8th logic circuit 3218 is 0, the output of AND gate 3221 is 1, and the output of NOR gate 3222 is 0. Therefore, the output of OR gate 3223 is 1, meaning the updated 8th bit shift indicator signal Index'8 output by OR gate 3223 is 1. When the thermometer code is all 0s, the output of the 8th logic circuit 3218 is 0, the output of AND gate 3221 is 0, and the output of NOR gate 3222 is 1. Therefore, the output of OR gate 3223 is 1, meaning the updated 8th bit shift indicator signal Index'8 output by OR gate 3223 is 1. Thus, the purpose of setting the Mth bit shift indicator signal Index of the combinational logic circuit 320 to 1 is achieved when the thermometer code is all 1s or all 0s.

[0063] When the thermometer code is neither all 1s nor all 0s, it can be determined that the output of AND gate 3221 is 0 and the output of NOR gate 3222 is 0. Therefore, the output of the second logic circuit 322 depends on the output of the Mth first logic circuit 321.

[0064] Therefore, when the thermometer code is neither all 1s nor all 0s, the presence of the second logic circuit 322 does not change the Mth shift indicator signal Index corresponding to the Mth first logic circuit 321; that is, the output of the second logic circuit 322 is consistent with the output of the Mth first logic circuit 321. It is understood that when the thermometer code is neither all 1s nor all 0s, the second logic circuit 322 in the combinational logic circuit 320 of this application can also coexist with the first logic circuit 321. When the combinational logic circuit 320 of this application includes both the first logic circuit 321 and the second logic circuit 322, then the combinational logic circuit 320 of this application can be applied to perform combinational logic operations on any thermometer code.

[0065] Since shifter 310 and combinational logic circuit 320 form a closed loop, shifter 310 will perform a corresponding shift operation whenever the M-shift indication signal Index output by combinational logic circuit 320 changes. Therefore, to prevent shifter 310 from shifting before quantizer 400 outputs the next thermometer code, [refer to reference]. Figure 3 In some embodiments, the DWA algorithm implementation circuit 300 of this application may further include a trigger 330.

[0066] The data terminal of flip-flop 330 is connected to the output terminal of combinational logic circuit 320 to receive the M-shift indication signal Index<1:M> output by combinational logic circuit 320. The clock control terminal of flip-flop 330 receives a second clock control signal, and the output terminal of flip-flop 330 is connected to the control terminal of shifter 310. Flip-flop 330 can control whether to transmit the signal from its data terminal to its output terminal based on the second clock control signal, i.e., whether to transmit the received M-shift indication signal Index<1:M> to its output terminal. When the rising edge of the second clock control signal arrives, flip-flop 330 will transmit the M-shift indication signal Index<1:M> from its input terminal to its output terminal, making the value of the flip-flop's output terminal equal to the value of its data terminal, i.e., E<1:M> = Index<1:M>. At this time, the output terminal of flip-flop 330 will then output the M-shift indication signal Index<1:M> to shifter 310 for shifting. The second clock control signal lags behind the first clock control signal by a predetermined phase difference to ensure that the rising edge of the second clock control signal is located between two adjacent rising edges of the first clock control signal.

[0067] The shifter 310 needs to shift the thermometer code output by the quantizer 400, actually starting from the second thermometer code output by the quantizer 400. When the quantizer 400 outputs the first thermometer code, the shifter 310 does not need to shift. Therefore, before the DWA algorithm implementation circuit 300 starts working, the output of the trigger 330 can be reset. Thus, in some embodiments, the trigger 330 of this application is also used to receive a reset signal. The reset signal can be used after the DWA algorithm implementation circuit 300 is powered on to reset the output of the trigger 330 to a shift indicator signal Index where only the most significant bit is 1, that is, setting the Mth shift indicator signal Index to 1 and setting the other shift indicator signals Index to 0. The shift indicator signal Index where only the most significant bit is 1 means that the next thermometer code output by the quantizer 400 will be shifted M bits to the right, which means that the shifter 310 does not need to perform a shift operation.

[0068] The following will combine Figure 6 This will illustrate the specific workflow of the DWA algorithm implementation circuit of this application.

[0069] Figure 6 A timing diagram illustrating the reset signal, first clock control signal, and second clock control signal according to an embodiment of this application is provided. (Refer to...) Figure 6Taking M=8 as an example, after the DWA algorithm implementation circuit is powered on, before the modulator in the preamplifier stage of quantizer 400 starts working, a reset operation will be performed on the circuit. The reset signal will reset the output of flip-flop 330 to the reset value [0000 0001], that is, only the 8th bit shift indicator signal Index8=1, and the rest Index<1:7>=0. At this time, the temperature code of the first output of quantizer 400 does not need to be shifted. Taking the thermometer codes output by quantizer 400 as {6, 5, 3, 0, 2} as an example, after reset, the modulator will operate according to the first clock control signal. First, the rising edge of the first clock control signal arrives first, and the value of the thermometer code D<1:8> will not be shifted. At this time, the thermometer code C1<1:8> = D1<1:8> = [1111 1100] output by shifter 310. The first thermometer code is not shifted. The combinational logic circuit 320 performs combinational logic operation based on the thermometer code C1<1:8> = [1111 1100] and the result is Index<1:8> = [00000100]. However, at this time, the output of flip-flop 330 still needs to maintain the reset value, that is, the output of flip-flop 330 at this time is E<1:8> =

[0000] .

[0001] , this state is maintained until the end of the first clock cycle of the first clock control signal; before the second rising edge of the first clock control signal arrives, the first rising edge of the second clock control signal arrives, and the shift indication signal Index<1:8> received by the input terminal of the flip-flop 330 from the combinational logic circuit 320 is transmitted to the output terminal of the flip-flop 330. That is, at this time, E<1:8>=Index<1:8>=[0000 0100], indicating that the second thermometer code output by the quantizer 400 is shifted 6 bits to the right; when the second rising edge of the first clock control signal arrives, the thermometer code output by the quantizer 400 is updated to the second thermometer code D[1:8]=[1111 1000]. Since E<1:8>=Index<1:8>=[0000 0100] at this time, the shifter 310 shifts the thermometer code D[1:8] 6 bits to the right to obtain C[1:8]=[1110 0011]. The combinational logic circuit 320 performs combinational logic operations based on C[1:8]=[1110 0011] to obtain Index<1:8>=[00100000], while the output of the flip-flop 330 retains the previous value E<1:8>=[0000 0100] until the second rising edge of the second clock control signal arrives. Only then will the value of the input of the flip-flop 330, Index<1:8>, be passed to the value of the output of the flip-flop 330, E<1:8>. Similarly, when the third rising edge of the subsequent first clock control signal arrives, the third thermometer code output by the quantizer 400 is updated, and so on.

[0070] The DWA algorithm implementation circuit 300 of this application, by adding a combinational logic circuit 320, can replace the decoder, adder, and pointer register in the DWA algorithm implementation circuit 300 of related technologies. The shifter 310 sends the output thermometer code to the combinational logic circuit 320, which can directly perform combinational logic operations based on the thermometer code output by the shifter 310 to obtain the shift indicator signal Index of the next thermometer code to be shifted output by the quantizer 400. The shift indicator signal Index is then output to the shifter 310 for the shift operation, thereby greatly simplifying the circuit structure, saving circuit area, reducing design complexity, and significantly reducing circuit cost; at the same time, it can improve the circuit speed and increase its flexibility.

[0071] Figure 7 A schematic diagram of the structure of a shifter 310 according to one embodiment of this application is shown. Figure 7 As shown, a shifter 310 according to one embodiment of this application includes a controllable switch array, which comprises M×M controllable switches 3110. The shifter 310 has M data input terminals and M data output terminals. The controllable switches 3110 can be implemented using MOS logic such as transmission gates, which can complete the transmission of 0 or 1 logic. For example, when the logic value is 1, the controllable switch 3110 is closed; when the logic value is 0, the controllable switch 3110 is turned off.

[0072] In each column, the i-th row controllable switch 3110 is controlled by the i-th shift indication signal Index output by the combinational logic circuit 320, where i ranges from 1 to M.

[0073] The input terminal 3111 of the controllable switch 3110 in the j-th column of each row is connected to the corresponding j-th data input terminal of the shifter 310, where j ranges from 1 to M.

[0074] The output terminal 3112 of the controllable switch 3110 in the i-th row and j-th column is connected to the corresponding k-th data output terminal of the shifter 310. When j+i≤M, k=j+i; when j+i>M, k=j+iM. For example, when i=4 and j=5, then k=4+5-8=1. That is, the output terminal 3112 of the controllable switch 3110 in each row is sequentially and cyclically connected to the corresponding data output terminals of the shifter 310.

[0075] For example, in Figure 7In the example with M=8, the eight controllable switches 3110 are controlled by corresponding eight-position shift indicator signals Index. Specifically, the controllable switches 3110 in the first row are all controlled by the first-position shift indicator signal Index1; the controllable switches 3110 in the second row are all controlled by the second-position shift indicator signal Index2; the controllable switches 3110 in the third row are all controlled by the third-position shift indicator signal Index3; the controllable switches 3110 in the fourth row are all controlled by the fourth-position shift indicator signal Index4; the controllable switches 3110 in the fifth row are all controlled by the fifth-position shift indicator signal Index5; the controllable switches 3110 in the sixth row are all controlled by the sixth-position shift indicator signal Index6; the controllable switches 3110 in the seventh row are all controlled by the seventh-position shift indicator signal Index7; and the controllable switches 3110 in the eighth row are all controlled by the eighth-position shift indicator signal Index8.

[0076] The input terminals 3111 of the eight controllable switches 3110 are respectively connected to the eight data input terminals of the shifter 310, and are used to receive the corresponding eight bits of the thermometer code. That is, the input terminals 3111 of the first column of controllable switches 3110 are respectively connected to the first data input terminal of the shifter 310, and are used to receive the first bit code D1 in the thermometer code; the input terminals 3111 of the second column of controllable switches 3110 are respectively connected to the second data input terminal of the shifter 310, and are used to receive the second bit code D2 in the thermometer code; the input terminals 3111 of the third column of controllable switches 3110 are respectively connected to the third data input terminal of the shifter 310, and are used to receive the third bit code D3 in the thermometer code; the input terminals 3111 of the fourth column of controllable switches 3110 are respectively connected to the eight data input terminals of the shifter 310, and are used to receive the corresponding eight bits of ... fifth column of controllable switches 3110 are respectively connected to the eight data input terminals of the shifter 310, and are used to receive the corresponding eight bits of the thermometer code; the input terminals 3111 of the sixth column of controllable switches 3110 are respectively connected to the eight data input terminals of the shifter 310, and are used to receive the corresponding eight bits of the thermometer code; the input terminals 3111 of The fourth data input terminal is connected to receive the fourth bit code D4 in the thermometer code; the input terminal 3111 of the controllable switch 3110 in the fifth column is connected to the fifth data input terminal of the shifter 310 to receive the fifth bit code D5 in the thermometer code; the input terminal 3111 of the controllable switch 3110 in the sixth column is connected to the sixth data input terminal of the shifter 310 to receive the sixth bit code D6 in the thermometer code; the input terminal 3111 of the controllable switch 3110 in the seventh column is connected to the seventh data input terminal of the shifter 310 to receive the seventh bit code D7 in the thermometer code; the input terminal 3111 of the controllable switch 3110 in the eighth column is connected to the eighth data input terminal of the shifter 310 to receive the eighth bit code D8 in the thermometer code.

[0077] Since the controllable switch 3110 in the first row is controlled by the first shift indication signal Index1, meaning it needs to shift 1 bit to the right, the output terminals 3112 of the 1st, 2nd, ..., 8th controllable switches 3110 in the first row are respectively connected to the 2nd, 3rd, ..., 1st data output terminals of the shifter 310. Correspondingly, since the controllable switch 3110 in the second row is controlled by the 2nd shift indication signal Index2, meaning it needs to shift 2 bits to the right, the output terminals 3112 of the 1st, 2nd, ..., 8th controllable switches 3110 in the second row are respectively connected to the 3rd, 4th, ..., 2nd data output terminals of the shifter 310; and so on. The controllable switch 3110 in row 7 is controlled by the shift indicator signal Index7, meaning it needs to shift 7 bits to the right. Therefore, the output terminals 3112 of the 1st, 2nd, ..., 8th controllable switches 3110 in row 7 are respectively connected to the 8th, 1st, ..., 7th data output terminals of the shifter 310. The controllable switch 3110 in row 8 is controlled by the shift indicator signal Index8, meaning it needs to shift 8 bits to the right. This means it does not need to shift. Therefore, the output terminals 3112 of the 1st, 2nd, ..., 8th controllable switches 3110 in row 8 are respectively connected to the 1st, 2nd, ..., 8th data output terminals of the shifter 310.

[0078] Only one row of controllable switches 3110 can be closed at any given time. When the i-th shift indicator signal Index is 1, the i-th row of controllable switches 3110 is closed, thus achieving a right shift of i bits. For example, when i = 8, it means that the previous DAC capacitor selection ended exactly at the last capacitor, so no shift is needed, i.e., no shift occurs when i = 8. When i = 6, i.e., ... Figure 6In the scenario shown, the 6th shift indicator signal Index6 = 1, indicating that a 6-bit shift is required next. At this time, only all eight controllable switches 3110 in the 6th row are closed, while all controllable switches 3110 in other rows are closed. Therefore, the output terminal 3112 of the controllable switch 3110 in the 6th row, 1st column is connected to the 7th data output terminal of the shifter 310. That is, the input terminal of the controllable switch 3110 in the 6th row, 1st column is connected to the 7th data output terminal of the shifter 310. Thus, the first bit code D1 in the thermometer code received at the input terminal 3111 of the controllable switch 3110 in the 6th row, 1st column is transmitted to the 7th data output terminal of the shifter 310, i.e., C. 7 = D1; The output terminal 3112 of the controllable switch 3110 in the 6th row and 2nd column is connected to the 8th data output terminal of the shifter 310. Therefore, the 2nd bit D2 of the thermometer code received at the input terminal 3111 of the controllable switch 3110 in the 6th row and 2nd column is transferred to the 8th data output terminal of the shifter 310, i.e., C8 = D2; ...; and so on. The output terminal 3112 of the controllable switch 3110 in the 6th row and 8th column is connected to the 6th data output terminal of the shifter 310. Therefore, the 8th bit D8 of the thermometer code received at the input terminal of the controllable switch 3110 in the 6th row and 8th column is transferred to the 6th data output terminal of the shifter 310, i.e., C6 = D8. Thus, the purpose of shifting 6 bits to the right is achieved.

[0079] The advantages of the shifter 310 in this application are: the output to input of the shifter 310 only passes through a single controllable switch 3110, and the logic for each bit from input to output is the same, meaning that each bit is in the same circuit environment, and no additional nonlinearity is introduced. Furthermore, the layout design of the shifter 310 can be neatly arranged, the design is simple, and the introduction of additional parasitics is very small, achieving good results.

[0080] The DWA algorithm implementation circuit 300 of this application can have at least the following beneficial technical effects:

[0081] First, the structure of this application is simple and easy to implement;

[0082] Secondly, this application saves on decoders, adders, and pointer registers, which greatly reduces circuit area and lowers costs.

[0083] Third, the circuit of this application has a fast response speed and can be applied to high-frequency circuits;

[0084] Fourth, the circuit timing of this application is simple, easy to control, and less prone to timing problems;

[0085] Fifth, the circuit design of this application is clear and easy to implement and modify, and easy to debug.

[0086] This application also provides an analog-to-digital converter. Figure 8 A schematic diagram of the structure of an analog-to-digital converter according to an embodiment of this application is shown. Figure 8 As shown, the analog-to-digital converter includes a modulator 500, a quantizer 400, a DWA algorithm implementation circuit 300 as described above, a digital signal processing circuit 600, and a capacitor array 100.

[0087] Modulator 500 can be, for example, a Sigma-Delta modulator, which is a type of analog integrator. The input of modulator 500 is used to receive analog input signals; the output of modulator 500 is connected to the input of quantizer 400.

[0088] The output of quantizer 400 is connected to the input of DWA algorithm implementation circuit 300; the output of DWA algorithm implementation circuit 300 is connected to one end of capacitor array 100. The other end of capacitor array 100 is connected to the feedback of modulator 500. Modulator 500 can integrate the difference between the received analog input signal and the analog signal fed back from capacitor array 100 and output the result to quantizer 400.

[0089] The digital signal processing circuit 600 may include, for example, a digital integrator. The digital signal processing circuit 600 is connected to the output terminal of the DWA algorithm implementation circuit 300 and is used to process the signal output by the DWA algorithm implementation circuit 300 and output a digital code.

[0090] The analog-to-digital converter of this application can have at least similar beneficial technical effects to the DWA algorithm implementation circuit 300 described above, so it will not be repeated here.

[0091] The DWA algorithm implementation circuit and analog-to-digital converter provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the DWA algorithm implementation circuit and analog-to-digital converter in the embodiments of this application. The descriptions of the embodiments above are only for helping to understand the core ideas of this application and are not intended to limit this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the spirit and principles of this application, and these improvements and modifications should all fall within the protection scope of the appended claims.

Claims

1. A DWA algorithm implementation circuit, characterized by, Includes shifters and combinational logic circuits, among which, The data input terminal of the shifter is used to receive the thermometer code output by the quantizer based on the first clock control signal; the data output terminal of the shifter is connected to the input terminal of the combinational logic circuit and serves as the output terminal of the DWA algorithm implementation circuit. The combinational logic circuit is used to connect the thermometer codes output by the shifter end to end, and perform combinational logic operations on the connected thermometer codes to generate a shift indication signal for the shifter. The shifter is used to perform a shift operation based on the shift indication signal.

2. The DWA algorithm implementation circuit of claim 1, wherein, The combinational logic circuit is used to identify the adjacent positions of the 1 code and the 0 code by performing combinational logic operations on two adjacent bits in the thermometer code when the thermometer code is not all 1 codes or not all 0 codes, so as to obtain the position where the 1 code ends; the position where the 1 code ends is used as the number of bits to be shifted in the thermometer code output by the quantizer next time, and the shift indication signal is output to the shifter.

3. The DWA algorithm implementation circuit of claim 2, wherein, The thermometer code has M bits, and the combinational logic circuit includes M first logic circuits. The i-th first logic circuit is used to perform a logical AND operation on the i-th bit of the thermometer code connected end to end with the inverted bit of the next bit, and output the i-th bit shift indication signal, where i ranges from 1 to M. The combinational logic circuit is used to determine the end position of the 1 code based on the M shift indication signals output by the M first logic circuits when the thermometer code is not all 1s or not all 0s.

4. The DWA algorithm implementation circuit of claim 3, wherein, The combinational logic circuit is used to identify the adjacent positions of 1 code and 0 code based on the M shift indication signals output by the M first logic circuits being 0 or 1, and to take the number of bits corresponding to the shift indication signal being 1 in the adjacent positions as the end position of 1 code.

5. The DWA algorithm implementation circuit of claim 3, wherein, The combinational logic circuit is also used to directly set the Mth shift indication signal output by the Mth first logic circuit to 1 when the thermometer code is all 1s or all 0s.

6. The DWA algorithm implementation circuit of claim 5, wherein, The combinational logic circuit further includes a second logic circuit, wherein... The second logic circuit is used to perform logical processing on the output of the Mth first logic circuit and the M-bit code of the thermometer code, so as to update the Mth shift indication signal corresponding to the output of the Mth first logic circuit according to the state of the M-bit code of the thermometer code. The combinational logic circuit is used to take the Mth bit shift indicator signal updated by the second logic circuit as the final Mth bit shift indicator signal.

7. The DWA algorithm implementation circuit of claim 6, wherein, The second logic circuit includes AND gates, NOR gates, and OR gates, wherein, The AND gate is used to perform a logical AND operation on the M-bit code of the thermometer code; The NOR gate is used to perform a logical OR-NOT operation on the M-bit code of the thermometer code; The three input terminals of the OR gate are respectively connected to the output terminal of the Mth first logic circuit, the output terminal of the AND gate, and the output terminal of the NOR gate. The output terminal of the OR gate serves as the output terminal of the second logic circuit, used to output the updated Mth shift indication signal.

8. The DWA algorithm implementation circuit of any one of claims 1 to 7, wherein, It also includes triggers, where, The data terminal of the flip-flop is connected to the output terminal of the combinational logic circuit, the clock control terminal of the flip-flop is used to receive the second clock control signal, and the output terminal of the flip-flop is connected to the control terminal of the shifter. The trigger is used to control whether to transmit the signal from the data terminal of the trigger to the output terminal of the trigger according to the second clock control signal.

9. The DWA algorithm implementation circuit of claim 8, wherein, The second clock control signal lags behind the first clock control signal by a predetermined phase difference.

10. The DWA algorithm implementation circuit of claim 8, wherein, The thermometer code has M bits, the shift indicator signal includes M bits, and the flip-flop is also used to receive a reset signal. The reset signal is used to reset the output of the flip-flop to a shift indicator signal where only the Mth bit is 1 after the DWA algorithm implementation circuit is powered on and before the rising edge of the second clock control signal arrives.

11. The DWA algorithm implementation circuit of claim 5, wherein, The shifter includes M×M controllable switches, and has M data input terminals and M data output terminals, wherein... The controllable switch in the i-th row of each column is controlled by the i-th shift indication signal output by the combinational logic circuit, where i ranges from 1 to M. The input terminal of the controllable switch in the j-th column of each row is connected to the j-th data input terminal of the shifter, where j ranges from 1 to M; The output terminals of the controllable switches in the i-th row and j-th column are respectively connected to the k-th data output terminal of the shifter, wherein when j+i≤M, k=j+i; when j+i>M, k=j+iM.

12. The DWA algorithm implementation circuit of claim 11, wherein, When the shift indicator signal of the i-th row is 1, the controllable switch of the i-th row is closed.

13. An analog-to-digital converter, characterized by Includes a modulator, a quantizer, a DWA algorithm implementation circuit as described in any one of claims 1 to 12, and a capacitor array, wherein, The input terminal of the modulator is used to receive analog input signals; the output terminal of the modulator is connected to the input terminal of the quantizer. The output of the quantizer is connected to the input of the DWA algorithm implementation circuit; the output of the DWA algorithm implementation circuit is connected to one end of the capacitor array. The other end of the capacitor array is connected to the feedback terminal of the modulator.

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